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Feature: STM32 watchdog timer control #1882

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merged 47 commits into from
Aug 6, 2024
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229b3be
stm32f1: Reworked the STM32F1 device identification structure to bett…
dragonmux Jul 9, 2024
889c684
stm32f1: Implemented support for halting at least the STM32F1 WDTs wh…
dragonmux Jul 9, 2024
5d279c5
stm32h7: Cleaned up a nomenclature issue in the private structure
dragonmux Jul 9, 2024
18e5dad
stm32f1: Sorted out DBGMCU handling for the GD32E5 parts
dragonmux Jul 9, 2024
65362cf
stm32f1: Fixed and updated all the references for the documentation t…
dragonmux Jul 9, 2024
4d084ae
stm32f1: Sorted out DBGMCU handling for the STM32F0 parts
dragonmux Jul 9, 2024
c69bfbc
stm32f1: Made use of the new DBGMCU machinary for the GD32F{1,2,3} pa…
dragonmux Jul 9, 2024
06d51a4
stm32f1: Properly handle the WDTs and WFI/WFE state for the DBGMCU wh…
dragonmux Jul 9, 2024
8f49985
stm32f1: More documentation links for parts supported by this impleme…
dragonmux Jul 9, 2024
4e85786
stm32f1: Added handling for the AT32F40x and AT32F41x parts' DBGMCUs
dragonmux Jul 9, 2024
8c9c2c6
stm32f1: More use of the base address macros to clean up all the magi…
dragonmux Jul 9, 2024
24b52d9
stm32f1: Added handling for the MM32L0 parts' DBGMCUs
dragonmux Jul 9, 2024
bd8bfe2
stm32f1: Added handling for the MM32F3 and MM32F5 parts' DBGMCUs
dragonmux Jul 9, 2024
01baa13
stm32f4: General cleanup an docs links for the implementation
dragonmux Jul 10, 2024
105dee0
stm32f4: Built DBGMCU support for the GD32F4 parts and improved the S…
dragonmux Jul 10, 2024
02bdb8f
stm32h5: Implemented support for halting the WDTs when debug halted, …
dragonmux Jul 10, 2024
0630e72
stm32g0: Cleaned up the docs references
dragonmux Jul 11, 2024
a390c63
stm32g0: Fixed a bug wit the erase_bank command specifying parameters…
dragonmux Jul 11, 2024
7904cdc
stm32g0: Fixed up the nomenclature for the ID codes to match the othe…
dragonmux Jul 11, 2024
6d0cedc
stm32g0: Systematically correced the nomenclature for `target` and `f…
dragonmux Jul 11, 2024
c17182d
stm32g0: Refactored the handling for the WDTs and WFI/WFE debugging s…
dragonmux Jul 11, 2024
99ebf84
stm32l4: Bought the copyright/attribution notice into compliance
dragonmux Jul 12, 2024
51a3254
stm32l4: Systematically correced the nomenclature for `target`, `flas…
dragonmux Jul 13, 2024
b5372e8
stm32l4: Refactored the handling for the WDTs and WFI/WFE debugging s…
dragonmux Jul 14, 2024
d99beb4
riscv_debug: Expose `riscv_attach()` and `riscv_detach()` in the arch…
dragonmux Jul 16, 2024
5c98da4
stm32f1: Fixed the GD32VF1 probe routine to use RISC-V suitable and s…
dragonmux Jul 16, 2024
34c5b46
stm32mp15: Nomenclature corrections for the DBGMCU definitions
dragonmux Jul 16, 2024
39d4353
stm32mp15: Renamed the Cortex-M4 attach and detach functions to disam…
dragonmux Jul 16, 2024
ad21cc5
stm32mp15: Refactored the DBGMCU handling and added support for prope…
dragonmux Jul 16, 2024
603b00a
stm32l4: Fixed up the consistency of the references the manuals
dragonmux Jul 17, 2024
2bb55af
stm32l0: Updated the attribution notice and reworked the top of file …
dragonmux Jul 17, 2024
7010e9d
stm32l0: Nomenclature harmonisation with the other STM32 target suppo…
dragonmux Jul 17, 2024
d0db0f3
stm32l0: Defined base address and sizing macros for the Flash and SRA…
dragonmux Jul 17, 2024
3e06790
stm32l0: Defined part identification macros to name the part ID numbers
dragonmux Jul 17, 2024
259de50
stm32l0: Split the probe function into two - one for L0 and one for L…
dragonmux Jul 17, 2024
21b728e
stm32l0: Implemented logic for controlling the DBGMCU and handling bo…
dragonmux Jul 20, 2024
a4b5d8f
stm32l0: Tidied up the logic for determining if a part is an L0 or an L1
dragonmux Jul 21, 2024
ad4f341
stm32l0: Begun refactoring the L1 probe code
dragonmux Jul 21, 2024
1b9ccb2
stm32l0: Implemented logic for properly determining the Flash size of…
dragonmux Jul 21, 2024
d655daa
stm32l0: Implemented logic for properly halting the WDTs and enabling…
dragonmux Jul 21, 2024
2bff033
stm32l0: Stripped out the protected attach/mass-erase implementations…
dragonmux Jul 21, 2024
8fa3386
stm32l0: Implemented the attach/detach logic for the L1's to deal wit…
dragonmux Jul 21, 2024
231584b
stm32l0: Implemented proper Flash registration tables for the L1 seri…
dragonmux Jul 28, 2024
c2f0b06
stm32l4: Device ID nomenclature corrections
dragonmux Aug 1, 2024
62d7ffd
stm32l4: Corrected the STM32U5 handling to pull the device ID from th…
dragonmux Aug 1, 2024
559bb7f
stm32l4: Correct handling of STM32U5 family devices for their DBGMCU …
dragonmux Aug 1, 2024
c4785d0
stm32h7: Nomenclature corrections for the DBGMCU definitions
dragonmux Aug 6, 2024
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1 change: 1 addition & 0 deletions src/target/cortexm.c
Original file line number Diff line number Diff line change
Expand Up @@ -585,6 +585,7 @@ bool cortexm_probe(adiv5_access_port_s *ap)
PROBE(stm32h7_probe);
PROBE(stm32mp15_cm4_probe);
PROBE(stm32l0_probe);
PROBE(stm32l1_probe);
PROBE(stm32l4_probe);
PROBE(stm32g0_probe);
break;
Expand Down
8 changes: 3 additions & 5 deletions src/target/riscv_debug.c
Original file line number Diff line number Diff line change
Expand Up @@ -142,6 +142,7 @@ static const char *const riscv_gpr_names[RV_GPRS_COUNT] = {
};

// clang-format on

typedef struct riscv_csr_descriptor {
const char *name;
const uint32_t csr_number; // fits in 16 bits actually (?)
Expand Down Expand Up @@ -257,9 +258,6 @@ static uint32_t riscv_hart_discover_isa(riscv_hart_s *hart);
static void riscv_hart_discover_triggers(riscv_hart_s *hart);
static void riscv_hart_memory_access_type(riscv_hart_s *hart);

static bool riscv_attach(target_s *target);
static void riscv_detach(target_s *target);

static const char *riscv_target_description(target_s *target);

static bool riscv_check_error(target_s *target);
Expand Down Expand Up @@ -811,7 +809,7 @@ bool riscv_config_trigger(riscv_hart_s *const hart, const uint32_t trigger, cons
return result;
}

static bool riscv_attach(target_s *const target)
bool riscv_attach(target_s *const target)
{
riscv_hart_s *const hart = riscv_hart_struct(target);
/* If the DMI requires special preparation, do that first */
Expand All @@ -825,7 +823,7 @@ static bool riscv_attach(target_s *const target)
return true;
}

static void riscv_detach(target_s *const target)
void riscv_detach(target_s *const target)
{
riscv_hart_s *const hart = riscv_hart_struct(target);
/* Once we get done and the user's asked us to detach, we need to resume the hart */
Expand Down
3 changes: 3 additions & 0 deletions src/target/riscv_debug.h
Original file line number Diff line number Diff line change
Expand Up @@ -234,6 +234,9 @@ riscv_match_size_e riscv_breakwatch_match_size(size_t size);
bool riscv_config_trigger(
riscv_hart_s *hart, uint32_t trigger, riscv_trigger_state_e mode, const void *config, const void *address);

bool riscv_attach(target_s *target);
void riscv_detach(target_s *target);

uint8_t riscv_mem_access_width(const riscv_hart_s *hart, target_addr_t address, size_t length);
void riscv32_unpack_data(void *dest, uint32_t data, uint8_t access_width);
uint32_t riscv32_pack_data(const void *src, uint8_t access_width);
Expand Down
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