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1. Synthetic-Training-Data-Generator-for-Tesseract-Arabic Synthetic-Training-Data-Generator-for-Tesseract-Arabic Public

   This is a synthetic training data generator for Tesseract 4.0+ Arabic

   Python 4 1

2. SAR-ADC-Controller SAR-ADC-Controller Public

   This is a SAR ADC Controller verilog implementation

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3. RCA-CLA-CSA-Signed-Unsigned-nxm-Multiplier RCA-CLA-CSA-Signed-Unsigned-nxm-Multiplier Public

   This is an implementation of some adders: Ripple Carry Adder, Carry Select Adder, and Carry Lookahead Adder. And nxm dynamic parallel multipliers: Signed, and Unsigned using Verilog

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4. VDCS-Prototype-4 VDCS-Prototype-4 Public

   This prototype is focused on library development

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5. Dwarf-RV32ic-andAssemblyTestGenerator Dwarf-RV32ic-andAssemblyTestGenerator Public

   This is a simulator + verilog RTL of a RV32i CPU with C extension support. The Repo also include a random test generator that was used to stress-test the CPU

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6. Serial-Parallel-Multiplier-Verilog Serial-Parallel-Multiplier-Verilog Public

   This is a Serial Parallel Multiplier coded in Verilog

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