Into neural net-native system on chip architectures.
Hi, I'm a computer engineering student at uw-madison focusing on digital design and architecture
- Madison, WI
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13:14
(UTC -05:00) - in/abhinav-nandwani-a4b48a218
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arm-llama2-asic
arm-llama2-asic PublicThis repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for efficient INT8 matrix multiplication and high-throughput infer…
Coq 6
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ece552-computer-architecture
ece552-computer-architecture Publicmips-r2000 based ISA microprocessor implementation at the RTL level.
Verilog 1
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