[ghdl synth] fix elaboration args

src/xeda/flows/ghdl/__init__.py

@@ -379,13 +379,6 @@ def synth_args(
         flags.extend(ss.generics_flags(design.rtl.generics))
         if one_shot_elab:
             flags += map(str, design.sources_of_type(SourceType.Vhdl, rtl=True, tb=False))
-            flags.append("-e")
-        if (
-            design.rtl.sources[-1].type == SourceType.Vhdl
-        ):  # add top if last source (top source) is VHDL
-            if not top and design.rtl.top:
-                top = (design.rtl.top,)
-            flags.extend(list(top))
         return flags
 
 

src/xeda/flows/yosys/templates/read_files.tcl

@@ -34,7 +34,7 @@ yosys read_verilog -sv -defer {{settings.read_verilog_flags|join(" ")}} {{define
 yosys log -stdout "** Elaborating VHDL files **"
 yosys plugin -i ghdl
 set ghdl_args "{{ghdl_args|join(" ")}}"
-yosys ghdl {*}$ghdl_args {{vhdl_files|join (" ")}} -e
+yosys ghdl {*}$ghdl_args {{vhdl_files|join (" ")}} -e {% if design.rtl.top %} {{design.rtl.top}} {% endif %}
 {% endif %}
 
 {%- if settings.liberty is defined %}

src/xeda/flows/yosys/yosys_fpga.py

@@ -96,7 +96,7 @@ def run(self) -> None:
             "yosys_fpga_synth.tcl",
             lstrip_blocks=True,
             trim_blocks=False,
-            ghdl_args=GhdlSynth.synth_args(ss.ghdl, self.design, one_shot_elab=False),
+            ghdl_args=GhdlSynth.synth_args(ss.ghdl, self.design, one_shot_elab=True),
             parameters=process_parameters(self.design.rtl.parameters),
             defines=[f"-D{k}" if v is None else f"-D{k}={v}" for k, v in ss.defines.items()],
             abc_constr_file=abc_constr_file,