Skip to content
View Vaibhav-Gunthe's full-sized avatar

Block or report Vaibhav-Gunthe

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Vaibhav-Gunthe/README.md

👋 Hi, I’m Vaibhav Gunthe

👀 I’m interested in VLSI design, neural computing, and AI hardware acceleration.
🌱 I’m currently learning Verilog, RTL design, and working on a Tiny NPU for AI inference.
💞️ I’m looking to collaborate on VLSI-based AI projects, FPGA designs, and digital hardware implementations....
📫 How to reach me: [gunthevaibhav@gmail.com]
⚡ Fun fact: I enjoy debugging hardware designs 🛠️ more than fixing software bugs 🐞!

Pinned Loading

  1. Verilog-Projects Verilog-Projects Public

    A collection of Verilog-based digital design projects, from basic gates to complex modules like ALUs, FSMs, and memory units. Ideal for learning RTL design and synthesis.

    Verilog 2