refactor(ICache): add ICacheMetaHelper reused by PrefetchPipe & CtrlUnit

OpenXiangShan · Mar 11, 2025 · c936f3b · c936f3b
1 parent 01719eb
commit c936f3b
Show file tree

Hide file tree

Showing 5 changed files with 31 additions and 21 deletions.
diff --git a/src/main/scala/xiangshan/frontend/icache/Helpers.scala b/src/main/scala/xiangshan/frontend/icache/Helpers.scala
@@ -95,7 +95,23 @@ trait ICacheEccHelper extends HasICacheParameters {
   }
 }
 
-trait ICacheDataSelHelper extends HasICacheParameters {
+trait ICacheMetaHelper extends HasICacheParameters {
+  def getWaymask(reqPAddr: UInt, metaPTag: Vec[UInt], metaValid: Vec[Bool]): UInt = {
+    require(metaPTag.length == nWays)
+    require(metaValid.length == nWays)
+    val reqPTag = get_phy_tag(reqPAddr)
+    VecInit((metaPTag zip metaValid).map { case (wayPTag, wayValid) =>
+      wayValid && (wayPTag === reqPTag)
+    }).asUInt
+  }
+
+  def getWaymask(reqPAddrVec: Vec[UInt], metaPTagVec: Vec[Vec[UInt]], metaValidVec: Vec[Vec[Bool]]): Vec[UInt] =
+    VecInit((reqPAddrVec zip metaPTagVec zip metaValidVec).map { case ((reqPAddr, metaPTag), metaValid) =>
+      getWaymask(reqPAddr, metaPTag, metaValid)
+    })
+}
+
+trait ICacheDataHelper extends HasICacheParameters {
   def bankOffBits: Int = log2Ceil(blockBytes / ICacheDataBanks)
 
   def getBankIdxLow(blkOffset: UInt): UInt =

diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala b/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala
@@ -43,7 +43,9 @@ class ICacheCtrlUnit(params: ICacheCtrlUnitParams)(implicit p: Parameters) exten
     concurrency = 1
   )
 
-  class ICacheCtrlUnitImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) with HasICacheParameters {
+  class ICacheCtrlUnitImp(wrapper: LazyModule) extends LazyModuleImp(wrapper)
+      with HasICacheParameters
+      with ICacheMetaHelper {
     class ICacheCtrlUnitIO(implicit p: Parameters) extends ICacheBundle {
       // ecc control
       val eccEnable: Bool = Output(Bool())
@@ -142,7 +144,7 @@ class ICacheCtrlUnit(params: ICacheCtrlUnitParams)(implicit p: Parameters) exten
 
     // inject position
     private val iVSetIdx = get_idx(eccIAddr.pAddr)
-    private val iPTag    = get_tag(eccIAddr.pAddr)
+    private val iPAddr   = eccIAddr.pAddr
     private val iWaymask =
       RegInit(0.U(nWays.W)) // read from metaArray, valid after iState === InjectFsmState.readMetaResp
 
@@ -167,7 +169,7 @@ class ICacheCtrlUnit(params: ICacheCtrlUnitParams)(implicit p: Parameters) exten
 
     io.metaWrite.req.valid := iState === InjectFsmState.WriteMeta
     io.metaWrite.req.bits.generate(
-      tag = iPTag,
+      tag = get_phy_tag(iPAddr),
       idx = iVSetIdx,
       waymask = iWaymask,
       bankIdx = iVSetIdx(0),
@@ -197,9 +199,7 @@ class ICacheCtrlUnit(params: ICacheCtrlUnitParams)(implicit p: Parameters) exten
       }
       is(InjectFsmState.ReadMetaResp) {
         // metaArray ensures resp is valid one cycle after req
-        val waymask = VecInit((0 until nWays).map { w =>
-          io.metaRead.resp.entryValid.head(w) && io.metaRead.resp.tags.head(w) === iPTag
-        }).asUInt
+        val waymask = getWaymask(iPAddr, io.metaRead.resp.tags.head, io.metaRead.resp.entryValid.head)
         iWaymask := waymask
         when(!waymask.orR) {
           // not hit, refuse to inject

diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheDataArray.scala b/src/main/scala/xiangshan/frontend/icache/ICacheDataArray.scala
@@ -20,7 +20,7 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import utility.mbist.MbistPipeline
 
-class ICacheDataArray(implicit p: Parameters) extends ICacheModule with ICacheEccHelper with ICacheDataSelHelper {
+class ICacheDataArray(implicit p: Parameters) extends ICacheModule with ICacheEccHelper with ICacheDataHelper {
   class ICacheDataArrayIO(implicit p: Parameters) extends ICacheBundle {
     val write: DataWriteBundle = Flipped(new DataWriteBundle)
     val read:  DataReadBundle  = Flipped(new DataReadBundle)

diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
@@ -34,7 +34,7 @@ import xiangshan.frontend.FtqToFetchBundle
 class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
     with ICacheEccHelper
     with ICacheAddrHelper
-    with ICacheDataSelHelper
+    with ICacheDataHelper
     with ICacheMissUpdateHelper {
 
   class ICacheMainPipeIO(implicit p: Parameters) extends ICacheBundle {

diff --git a/src/main/scala/xiangshan/frontend/icache/ICachePrefetchPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICachePrefetchPipe.scala
@@ -32,6 +32,7 @@ import xiangshan.frontend.ExceptionType
 
 class ICachePrefetchPipe(implicit p: Parameters) extends ICacheModule
     with ICacheAddrHelper
+    with ICacheMetaHelper
     with ICacheMissUpdateHelper {
 
   class ICachePrefetchPipeIO(implicit p: Parameters) extends ICacheBundle {
@@ -239,19 +240,12 @@ class ICachePrefetchPipe(implicit p: Parameters) extends ICacheModule
   private val s1_metaPTags  = fromMeta.tags
   private val s1_metaValids = fromMeta.entryValid
 
-  private def getWaymask(paddrs: Vec[UInt]): Vec[UInt] = {
-    val pTags = paddrs.map(get_phy_tag)
-    val tagEqVec =
-      VecInit((0 until PortNumber).map(p => VecInit((0 until nWays).map(w => s1_metaPTags(p)(w) === pTags(p)))))
-    val tagMatchVec = VecInit((0 until PortNumber).map { k =>
-      VecInit(tagEqVec(k).zipWithIndex.map { case (eq, w) => eq && s1_metaValids(k)(w) })
-    })
-    val waymasks = VecInit(tagMatchVec.map(_.asUInt))
-    waymasks
-  }
-
   private val s1_sramWaymasks = VecInit((0 until PortNumber).map { port =>
-    Mux(tlbValidPulse(port), getWaymask(s1_pAddrWire)(port), getWaymask(s1_pAddrReg)(port))
+    Mux(
+      tlbValidPulse(port),
+      getWaymask(s1_pAddrWire(port), s1_metaPTags(port), s1_metaValids(port)),
+      getWaymask(s1_pAddrReg(port), s1_metaPTags(port), s1_metaValids(port))
+    )
   })
 
   // select ecc code