init support for VxWorks-7 on Freescale i.MX6 #936

yanyan-wrs · 2016-07-25T03:34:54Z

Add changes to work with VxWorks as Rich OS:

added VxWorks specific SMC requests definition. OP-TEE is to be used as both a TEE and a Monitor for VxWorks, so additional SMC requests must be handled by OP-TEE.
added a new the hand-off protocol between loader and OP-TEE, that is, no hand-off at all. OP-TEE will not require loader to pass any arguments, instead, things such as paged data, NS entry and DT address are from configuration parameters. This hand-off is to be used by VxWorks.
Added the i.MX6 Sabre Lite board support.

jforissier · 2016-07-27T07:54:29Z

@yanyan-wrs the "close" and "re-open" buttons are working, there is no need to test them so often ;)

yanyan-wrs · 2016-08-05T03:25:49Z

@jforissier sorry, first time doing this. I thought I need to "close" the pull request to add new staffs. By the way, i noticed there has been no comment or action taken for this pull request, so, what's the holding up, am I doing something the wrong way?

jforissier · 2016-08-05T06:54:01Z

@yanyan-wrs no problem ;)
The reason why this PR is not moving forward is because several people in our team are on vacation currently, so we are lacking reviewers. But don't worry we will definitely look at this as soon as possible.

etienne-lms · 2016-08-10T21:56:36Z

core/arch/arm/kernel/generic_entry_a32.S

@@ -425,6 +445,9 @@ UNWIND(	.cantunwind)

 	bl	plat_cpu_reset_late

+    /* this core just comes out of reset, discard undefined l1 contents */


Minor issue of indentation of comment.

accepted and fixed

jenswi-linaro · 2016-08-18T08:54:49Z

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

yanyan-wrs · 2016-09-05T09:21:35Z

@NightEugene
I updated a new version, which supports Linux SMP. Now I have removed the vxWorks specific SMC requests to make it an generic secondary core boot request for any Rich OS.

I tested with both SabreLite and SabreSD board, everything is fine.
Following is how to do it:

1 Update the latest git code, and build OP-TEE with following confgurations:

CFG_BUILT_IN_ARGS=y 
CFG_PAGEABLE_ADDR=0 
CFG_NS_ENTRY_ADDR=0x12000000 
CFG_DT_ADDR=0x18000000 
CFG_TEE_GDB_BOOT=y 
CFG_DT=y 
CFG_BOOT_SECONDARY_REQUEST=y 
PLATFORM=imx-mx6qsabrelite

2 Pretend the tee as an Linux uImage. This is to let u-boot pass r0-r2 as if it is booting a Linux, and with the CFG_TEE_GDB_BOOT option above, OP-TEE will pass r0-r3 to the real Rich OS Linux.

mkimage -A arm -O linux -C none -a 0x4dffffe4 -e 0x4e000000 -d tee.bin uTee

3 Modify the SMP boot code of Linux, in linux/arch/arm/mach-imx/platsmp.c:
add extra header and definitions:

#include <linux/arm-smccc.h>

#define OPTEE_SMC_CALLID_BOOT_SECONDARY       12
#define OPTEE_SMC_BOOT_SECONDARY  \
    ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, \
                ARM_SMCCC_OWNER_TRUSTED_OS, OPTEE_SMC_CALLID_BOOT_SECONDARY)

4 change the imx_boot_secondary. NOTE: the original code set the entry as v7_secondary_startup, which has made an access to an diagnostic co processor, but it is not accessible from NS, so we just entry secondary_startup instead of v7_secondary_startup.

static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
#if 0
    imx_set_cpu_jump(cpu, v7_secondary_startup);
    imx_enable_cpu(cpu, true);
#endif
#if 1
    struct arm_smccc_res  res;
    arm_smccc_smc(OPTEE_SMC_BOOT_SECONDARY,
        cpu, virt_to_phys(secondary_startup),
        0, 0, 0, 0, 0, &res);
#endif
return 0;
}

5 You may also need to change the NS L2 initialization code, if not fixed already, as you pointed out before.

6 u-boot command, for sabresd:

tftp 0x12000000 zImage
tftp 0x18000000 imx6q-sabresd.dtb 
tftp 0x20000000 uTee
setenv bootargs console=ttymxc0,115200 root=/dev/mmcblk0p2 rootwait rw
bootm 0x20000000 - 0x18000000

for sabrelite:

tftp 0x12000000 zImage
tftp 0x18000000 imx6q-sabrelite.dtb 
tftp 0x20000000 uTee
setenv bootargs console=ttymxc1,115200 root=/dev/mmcblk0p2 rootwait rw
bootm 0x20000000 - 0x18000000

yanyan-wrs · 2016-09-06T00:52:31Z

Hi everyone, sorry for the repeated changes here. I had intended to support VxWorks only, however, with help from @NightEugene, Linux Rich OS is also supported, with the existing u-boot setup and some patches to the Linux kernel regarding Non-Secure executing.
To support both Linux and VxWorks, I added a generic OP-TEE Trusted OS SMC Request:

/*
 * Release of secondary cores
 *
 * OP-TEE in secure world is in charge of the release process of secondary
 * cores. The Rich OS issue the this request to ask OP-TEE to boot up the
 * secondary cores, go through the OP-TEE per-core initialization, and then
 * switch to the Non-secure world with the Rich OS provided entry address.
 *
 * Call register usage:
 * a0   SMC Function ID, OPTEE_SMC_BOOT_SECONDARY
 * a1   smp cpu index
 * a2   NS entry address low
 * a3   NS entry address high
 * a4-7 Not used
 *
 * Normal return register usage:
 * a0   OPTEE_SMC_RETURN_OK
 * a1-7 Preserved
 *
 * Not idle return register usage:
 * a0   OPTEE_SMC_RETURN_EBUSY
 * a1-7 Preserved
 */
#define OPTEE_SMC_FUNCID_BOOT_SECONDARY  12
#define OPTEE_SMC_BOOT_SECONDARY \
    OPTEE_SMC_FAST_CALL_VAL(OPTEE_SMC_FUNCID_BOOT_SECONDARY)

With this added request, both Linux and VxWorks Rich OSes can ask for OP-TEE to release the secondary cores thus enter SMP execution.
This change is final from my part, please review it.

jenswi-linaro · 2016-09-06T07:16:05Z

core/arch/arm/include/sm/optee_smc.h

+ * Call register usage:
+ * a0	SMC Function ID, OPTEE_SMC_BOOT_SECONDARY
+ * a1   smp cpu index
+ * a2   NS entry address low


To harmonize better with the other descriptions please rephrase as:

a2 Upper 32-bits of 64-bit NS entry address a3 Lower 32-bits of 64-bit NS entry address

Any particular reason the lower bits was first?
Please add a comment about what can be expected of CPSR also.

NightEugene · 2016-09-06T07:56:37Z

@yanyan-wrs
Thanks very much for your help! Now everything works fine. Only CAAM (Cryptographic Acceleration and Assurance Module) doesn't work, but this is a separate issue.

For my i.MX6Q SabreAuto board I maked few changes:

#define UART3_BASE              0x021F0000

#define CONSOLE_UART_BASE       UART3_BASE
#define CONSOLE_UART_PA_BASE    UART3_BASE

#define DRAM0_BASE              0x10000000
#define DRAM0_SIZE              0x80000000

#define CFG_DDR_TEETZ_RESERVED_START    0x8E000000
#define CFG_DDR_TEETZ_RESERVED_SIZE     0x02000000

jenswi-linaro · 2016-09-07T09:26:10Z

core/arch/arm/kernel/generic_entry_a32.S

+	/* get ns entry from ns_entry_addrs array */
+	bl  get_core_pos
+	ldr r1, =ns_entry_addrs
+	add r1, r1, r0, lsl #2	/* paddr_t is 4 bytes in 32-bit system */


The size of paddr_t is not guaranteed to be 4 bytes on a 32-bit system. It would be better to use the uint32_t type instead for ns_entry_addrs[] as anything larger than that doesn't make sense on a 32-bit system.

Please update this comment too.

jenswi-linaro · 2016-09-13T07:57:47Z

I'm OK with this now. @MrVan, do you have more comments?

MrVan · 2016-09-19T05:48:39Z

@jenswi-linaro Sorry for late reply. I am ok with it.

jenswi-linaro · 2016-09-19T07:06:27Z

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

jforissier · 2016-09-19T07:38:22Z

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

MrVan · 2016-09-21T07:15:19Z

Reviewed-by: Peng Fan peng.fan@nxp.com

yanyan-wrs · 2016-09-22T06:41:22Z

Should I rebase and squash the changes before merge?

jforissier · 2016-09-22T06:46:24Z

@yanyan-wrs yes, please squash the commits, add the 'Reviewed-by:' tags, and rebase on top of optee_os master. Thanks!

jforissier · 2016-09-26T19:29:29Z

@yanyan-wrs ping! I can tag the commits and rebase + merge myself, if you prefer, but then the PR will show up as "closed" rather than "merged" which is not so good.

yanyan-wrs · 2016-09-27T01:06:01Z

Sorry for the delay, I encountered some issue in the final testing (turned out to be issue #1071). Now the PR is ready.

Signed-off-by: Yan Yan <yan.yan@windriver.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>

jforissier · 2016-09-27T17:22:11Z

@yanyan-wrs @MrVan thanks for your contribution.

yanyan-wrs closed this Jul 26, 2016

yanyan-wrs reopened this Jul 27, 2016

yanyan-wrs closed this Jul 27, 2016

yanyan-wrs reopened this Jul 27, 2016

yanyan-wrs closed this Jul 27, 2016

yanyan-wrs reopened this Jul 27, 2016

etienne-lms reviewed Aug 10, 2016
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yanyan-wrs force-pushed the vxworks_support branch from 734b207 to 2ffd2f8 Compare September 6, 2016 00:38

yanyan-wrs force-pushed the vxworks_support branch 2 times, most recently from bd7c9a8 to 2bc86a6 Compare September 6, 2016 05:43

jenswi-linaro reviewed Sep 6, 2016
View reviewed changes

jenswi-linaro reviewed Sep 7, 2016
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yanyan-wrs force-pushed the vxworks_support branch from 22c654e to e0f073d Compare September 8, 2016 03:15

yanyan-wrs force-pushed the vxworks_support branch from e0f073d to e9615fb Compare September 27, 2016 01:02

Add the i.MX6 Quad SABRE board support (PLATFORM=imx)

6d96f20

Signed-off-by: Yan Yan <yan.yan@windriver.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>

yanyan-wrs force-pushed the vxworks_support branch from e9615fb to 6d96f20 Compare September 27, 2016 09:09

jforissier merged commit 6d96f20 into OP-TEE:master Sep 27, 2016

NightEugene mentioned this pull request Oct 7, 2016

boot without ATF #960

Closed

jeffy1009 mentioned this pull request Jan 23, 2017

Booting with Sabrelite board #1284

Closed

kdy1029 mentioned this pull request Feb 16, 2017

Porting i.MX6SX #1357

Closed

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init support for VxWorks-7 on Freescale i.MX6 #936

init support for VxWorks-7 on Freescale i.MX6 #936

yanyan-wrs commented Jul 25, 2016

jforissier commented Jul 27, 2016

yanyan-wrs commented Aug 5, 2016

jforissier commented Aug 5, 2016

etienne-lms Aug 10, 2016

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yanyan-wrs commented Sep 22, 2016

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jforissier commented Sep 26, 2016

yanyan-wrs commented Sep 27, 2016

jforissier commented Sep 27, 2016

		@@ -425,6 +445,9 @@ UNWIND( .cantunwind)

		bl plat_cpu_reset_late

		/* this core just comes out of reset, discard undefined l1 contents */

init support for VxWorks-7 on Freescale i.MX6 #936

init support for VxWorks-7 on Freescale i.MX6 #936

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