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(stm32) drivers: firewall: add RISAB internal memory firewall controller #7063

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merged 9 commits into from
Nov 4, 2024
Merged

(stm32) drivers: firewall: add RISAB internal memory firewall controller #7063

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a6e29b4
plat-stm32mp2: add VDERAM SYSCFG support
GseoC Oct 1, 2024
bd5abbe
plat-stm32mp2: add RISAB1/2 base addresses in platform configuration
GseoC Oct 1, 2024
ce44156
dt-bindings: add stm32mp25 RISAB bindings
GseoC Oct 1, 2024
4a82435
drivers: stm32_risab: add RISAB internal memory firewall driver
GseoC Oct 1, 2024
c11c610
plat-stm32mp2: default enable RISAB on stm32mp2 platforms
GseoC Oct 1, 2024
ab4e3ab
dts: stm32: add RISAB nodes in the stm32mp251 SoC DT file
GseoC Oct 1, 2024
37ef57a
dts: stm32: add RISAB configurations for the stm32mp257f-ev1 platform
GseoC Oct 1, 2024
46aaaca
dts: stm32: move firewall dt-bindings include at SoC level
GseoC Oct 1, 2024
4b24994
plat-stm32mp2: force CFG_DRIVERS_FIREWALL when supporting RIF control…
GseoC Oct 1, 2024
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52 changes: 52 additions & 0 deletions core/arch/arm/dts/stm32mp251.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,10 @@
*/

#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/firewall/stm32mp25-rif.h>
#include <dt-bindings/firewall/stm32mp25-rifsc.h>
#include <dt-bindings/firewall/stm32mp25-risaf.h>
#include <dt-bindings/firewall/stm32mp25-risab.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>

Expand Down Expand Up @@ -181,6 +184,55 @@
status = "disabled";
};

risab1: risab@420f0000 {
compatible = "st,stm32mp25-risab";
reg = <0x420f0000 0x1000>;
clocks = <&rcc CK_ICN_LS_MCU>;
st,mem-map = <0xa000000 0x20000>;
#access-controller-cells = <1>;
};

risab2: risab@42100000 {
compatible = "st,stm32mp25-risab";
reg = <0x42100000 0x1000>;
clocks = <&rcc CK_ICN_LS_MCU>;
st,mem-map = <0xa020000 0x20000>;
#access-controller-cells = <1>;
};

risab3: risab@42110000 {
compatible = "st,stm32mp25-risab";
reg = <0x42110000 0x1000>;
clocks = <&rcc CK_ICN_LS_MCU>;
st,mem-map = <0xa040000 0x20000>;
#access-controller-cells = <1>;
};

risab4: risab@42120000 {
compatible = "st,stm32mp25-risab";
reg = <0x42120000 0x1000>;
clocks = <&rcc CK_ICN_LS_MCU>;
st,mem-map = <0xa060000 0x20000>;
#access-controller-cells = <1>;
};

risab5: risab@42130000 {
compatible = "st,stm32mp25-risab";
reg = <0x42130000 0x1000>;
clocks = <&rcc CK_ICN_LS_MCU>;
st,mem-map = <0xa080000 0x20000>;
#access-controller-cells = <1>;
};

risab6: risab@42140000 {
compatible = "st,stm32mp25-risab";
reg = <0x42140000 0x1000>;
clocks = <&rcc CK_ICN_LS_MCU>;
st,mem-map = <0xa0a0000 0x20000>;
#access-controller-cells = <1>;
status = "disabled";
};

serc: serc@44080000 {
compatible = "st,stm32mp25-serc";
reg = <0x44080000 0x1000>;
Expand Down
36 changes: 36 additions & 0 deletions core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-resmem.dtsi
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Expand Up @@ -9,6 +9,42 @@
#size-cells = <2>;
ranges;

/* Internal RAM reserved memory declaration */
tfa_bl31: tfa-bl31@a000000 {
reg = <0x0 0xa000000 0x0 0x20000>;
no-map;
};

hpdma_lli: hpdma-lli@a020000 {
reg = <0x0 0xa020000 0x0 0x20000>;
no-map;
};

bsec_mirror: bsec-mirror@a040000 {
reg = <0x0 0xa040000 0x0 0x1000>;
no-map;
};

cm33_sram1: cm33-sram1@a041000 {
reg = <0x0 0xa041000 0x0 0x1f000>;
no-map;
};

cm33_sram2: cm33-sram2@a060000 {
reg = <0x0 0xa060000 0x0 0x20000>;
no-map;
};

cm33_retram: cm33-retram@a080000 {
reg = <0x0 0xa080000 0x0 0x1f000>;
no-map;
};

ddr_param: ddr-param@a09f000 {
reg = <0x0 0xa09f000 0x0 0x1000>;
no-map;
};

/* PCIe reserved memory declaration */
pcie_device: pcie-device@10000000 {
reg = <0x0 0x10000000 0x0 0x10000000>;
Expand Down
51 changes: 51 additions & 0 deletions core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi
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Expand Up @@ -374,6 +374,57 @@
>;
};

&tfa_bl31 {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_SEC, RIF_UNUSED, RIF_CFEN, RIF_CID1_BF, RIF_CID1_BF, RIF_CID1_BF)>;
};

&hpdma_lli {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_NSEC, RIF_PRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
};

&bsec_mirror {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_SEC, RIF_NPRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
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RIF_NPRIV expected here? I would rther expect RIF_PRIV.
Same question for cm33_retram (line 398) and ddr_param (line 402).

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@GseoC GseoC Oct 24, 2024 •
edited
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Let's keep it like this for now, to align with downstream and later make the change accordingly, if necessary

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ok

};

&cm33_sram1 {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_NSEC, RIF_NPRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
};

&cm33_sram2 {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_NSEC, RIF_NPRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
};

&cm33_retram {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_SEC, RIF_NPRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
};

&ddr_param {
st,protreg = <RISABPROT(RIF_DDCID_DIS, RIF_UNUSED, RIF_SEC, RIF_NPRIV, RIF_CFDIS, RIF_UNUSED, RIF_UNUSED, RIF_UNUSED)>;
};

&risab1 {
memory-region = <&tfa_bl31>;
};

&risab2 {
memory-region = <&hpdma_lli>;
};

&risab3 {
st,srwiad;
memory-region = <&bsec_mirror>, <&cm33_sram1>;
};

&risab4 {
st,srwiad;
memory-region = <&cm33_sram2>;
};

&risab5 {
st,srwiad;
memory-region = <&cm33_retram>, <&ddr_param>;
};

&mm_ospi1 {
st,protreg = <RISAFPROT(RISAF_REG_ID(1), RIF_CID1_BF | RIF_CID2_BF, RIF_CID1_BF | RIF_CID2_BF, 0, RIF_NSEC, RIF_ENC_DIS, RIF_BREN_EN)>;
};
Expand Down
3 changes: 0 additions & 3 deletions core/arch/arm/dts/stm32mp257f-ev1.dts
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Expand Up @@ -6,9 +6,6 @@

/dts-v1/;
#include <dt-bindings/clock/stm32mp25-clksrc.h>
#include <dt-bindings/firewall/stm32mp25-rif.h>
#include <dt-bindings/firewall/stm32mp25-rifsc.h>
#include <dt-bindings/firewall/stm32mp25-risaf.h>
#include "stm32mp257.dtsi"
#include "stm32mp257f-ev1-ca35tdcid-rcc.dtsi"
#include "stm32mp257f-ev1-ca35tdcid-resmem.dtsi"
Expand Down
4 changes: 4 additions & 0 deletions core/arch/arm/plat-stm32mp2/conf.mk
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Expand Up @@ -62,6 +62,7 @@ CFG_STM32_IAC ?= y
CFG_STM32_IPCC ?= y
CFG_STM32_RIF ?= y
CFG_STM32_RIFSC ?= y
CFG_STM32_RISAB ?= y
CFG_STM32_RISAF ?= y
CFG_STM32_RNG ?= y
CFG_STM32_SERC ?= y
Expand Down Expand Up @@ -104,3 +105,6 @@ endif

# Default enable firewall support
CFG_DRIVERS_FIREWALL ?= y
ifeq ($(call cfg-one-enabled, CFG_STM32_RISAB CFG_STM32_RIFSC),y)
$(call force,CFG_DRIVERS_FIREWALL,y)
endif
2 changes: 2 additions & 0 deletions core/arch/arm/plat-stm32mp2/platform_config.h
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Expand Up @@ -56,6 +56,8 @@
#define RIFSC_BASE 0x42080000
#define RISAF4_BASE 0x420d0000
#define RISAF5_BASE 0x420e0000
#define RISAB1_BASE 0x420f0000
#define RISAB2_BASE 0x42100000
#define RISAB6_BASE 0x42140000
#define BSEC3_BASE 0x44000000
#define IWDG2_BASE 0x44002000
Expand Down
11 changes: 11 additions & 0 deletions core/arch/arm/plat-stm32mp2/stm32_sysconf.h
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Expand Up @@ -20,6 +20,17 @@ enum syscon_banks {
#define SYSCON_ID(bank, offset) (((bank) << 16) | \
((offset) & GENMASK_32(15, 0)))

/*
* SYSCFG register offsets (base relative)
*/
#define SYSCFG_VDERAMCR SYSCON_ID(SYSCON_SYSCFG, 0x1800)

/*
* SYSCFG_VDERAMCR register offsets
*/
#define VDERAMCR_VDERAM_EN BIT(0)
#define VDERAMCR_MASK BIT(0)

/*
* A35SSC register offsets (base relative)
*/
Expand Down
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