🎓 Electronics System Engineering Graduate | VLSI & FPGA Enthusiast | Class of 2025
📍 NIELIT Aurangabad
I'm Gaurav, a passionate Electronics Engineering graduate specializing in VLSI Design, FPGA Prototyping, and Embedded Hardware Systems. I enjoy building high-impact digital designs and bringing them to life through RTL coding, verification, and real-time FPGA testing. My projects reflect a deep interest in digital logic, hardware security, and embedded intelligence.
Here on my GitHub, you’ll find hardware design and system-level projects like:
- 🔐 AES-128 Hardware Encryption
- 🔁 SPI Protocol using Verilog
- 📶 Dual-Frequency Sine Wave Generator (PL+PS in Vivado)
- 🧠 Branch Prediction using 2-bit Saturating Counter
- 💾 Memory Bank System
- 📡 Beamforming on FPGA using Array Processing
- 🔧 RTL & Verification using SystemVerilog + UVM
- 💡 ASIC Frontend Design Flow
- 🧬 Secure Hardware Architectures
- 🛠️ FPGA-Based Prototyping
- 📊 Static Timing Analysis, STA/DRC Sign-off
- 🧠 Embedded AI + Edge Design Flow
- 🏗️ Digital SoC Architecture Design
C C++ Python Verilog SystemVerilog TCL Perl
Vivado ISE Design Suite Icarus Verilog GTKWave
Yosys Sky130 PDK GHDL Bamboo EDA Esim
Fusion Compiler ICVWB Linux (Ubuntu) Git
- RTL Design and Functional Verification
- FPGA Prototyping (Zynq ZCU104, Basys3)
- ASIC Digital Frontend (Synthesis, Floorplan, STA)
- UVM-Based Verification Methodology
- Power Grid Design and Clock Domain Crossing
- Hardware Security Design (AES, Custom ISA, etc.)
- 📧 Email: gauravdhak2003@gmail.com
- 📝 Hashnode Blog
- 🐦 Twitter / X
If you're exploring domains like semiconductor design, hardware security, or AI hardware acceleration, I’d love to connect or collaborate on meaningful projects. Always open to contributing and learning!
“Logic is not just design — it's how you bring life into silicon.”