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Merged main:3d7802d2107f into amd-gfx:3573343a8b3e
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Local branch amd-gfx 3573343 Merged main:202de4a5c6ed into amd-gfx:63f08b5fd01a
Remote branch main 3d7802d [Clang] Actually fix tests for __builtin_vectorelements (llvm#69589)
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SC llvm team authored and SC llvm team committed Oct 19, 2023
2 parents 3573343 + 3d7802d commit 8ae8308
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Showing 21 changed files with 1,518 additions and 212 deletions.
9 changes: 9 additions & 0 deletions clang/include/clang/Basic/arm_sve.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1871,6 +1871,15 @@ def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone, "",
def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [], []>;
def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [], []>;
def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [], []>;

def SVWHILEGE_COUNT : SInst<"svwhilege_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILELE_COUNT : SInst<"svwhilele_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILELT_COUNT : SInst<"svwhilelt_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilelt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILELO_COUNT : SInst<"svwhilelo_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilelo_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILELS_COUNT : SInst<"svwhilels_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILEHI_COUNT : SInst<"svwhilehi_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
def SVWHILEHS_COUNT : SInst<"svwhilehs_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
}

let TargetGuard = "sve2p1" in {
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106 changes: 62 additions & 44 deletions clang/lib/AST/Interp/IntegralAP.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@ template <unsigned Bits, bool Signed> class Integral;
template <bool Signed> class IntegralAP final {
private:
friend IntegralAP<!Signed>;
APSInt V;
APInt V;

template <typename T> static T truncateCast(const APSInt &V) {
template <typename T> static T truncateCast(const APInt &V) {
constexpr unsigned BitSize = sizeof(T) * 8;
if (BitSize >= V.getBitWidth())
return std::is_signed_v<T> ? V.getSExtValue() : V.getZExtValue();
Expand All @@ -48,23 +48,37 @@ template <bool Signed> class IntegralAP final {
using AsUnsigned = IntegralAP<false>;

template <typename T>
IntegralAP(T Value)
: V(APInt(sizeof(T) * 8, static_cast<uint64_t>(Value),
std::is_signed_v<T>)) {}
IntegralAP(T Value, unsigned BitWidth)
: V(APInt(BitWidth, static_cast<uint64_t>(Value), Signed)) {}

IntegralAP(APInt V) : V(V) {}
IntegralAP(APSInt V) : V(V) {}
/// Arbitrary value for uninitialized variables.
IntegralAP() : V(APSInt::getMaxValue(1024, Signed)) {}
IntegralAP() : IntegralAP(-1, 1024) {}

IntegralAP operator-() const { return IntegralAP(-V); }
IntegralAP operator-(const IntegralAP &Other) const {
return IntegralAP(V - Other.V);
}
bool operator>(IntegralAP RHS) const { return V > RHS.V; }
bool operator>=(IntegralAP RHS) const { return V >= RHS.V; }
bool operator<(IntegralAP RHS) const { return V < RHS.V; }
bool operator<=(IntegralAP RHS) const { return V <= RHS.V; }
bool operator>(const IntegralAP &RHS) const {
if constexpr (Signed)
return V.ugt(RHS.V);
return V.sgt(RHS.V);
}
bool operator>=(IntegralAP RHS) const {
if constexpr (Signed)
return V.uge(RHS.V);
return V.sge(RHS.V);
}
bool operator<(IntegralAP RHS) const {
if constexpr (Signed)
return V.slt(RHS.V);
return V.slt(RHS.V);
}
bool operator<=(IntegralAP RHS) const {
if constexpr (Signed)
return V.ult(RHS.V);
return V.ult(RHS.V);
}

explicit operator bool() const { return !V.isZero(); }
explicit operator int8_t() const { return truncateCast<int8_t>(V); }
Expand All @@ -78,42 +92,32 @@ template <bool Signed> class IntegralAP final {

template <typename T> static IntegralAP from(T Value, unsigned NumBits = 0) {
assert(NumBits > 0);
APSInt Copy =
APSInt(APInt(NumBits, static_cast<uint64_t>(Value), Signed), !Signed);
APInt Copy = APInt(NumBits, static_cast<uint64_t>(Value), Signed);

return IntegralAP<Signed>(Copy);
}

template <bool InputSigned>
static IntegralAP from(IntegralAP<InputSigned> V, unsigned NumBits = 0) {
if constexpr (Signed == InputSigned)
return V;

APSInt Copy = V.V;
Copy.setIsSigned(Signed);

return IntegralAP<Signed>(Copy);
return IntegralAP<Signed>(V.V);
}

template <unsigned Bits, bool InputSigned>
static IntegralAP from(Integral<Bits, InputSigned> I, unsigned BitWidth) {
APSInt Copy =
APSInt(APInt(BitWidth, static_cast<uint64_t>(I), InputSigned), !Signed);
Copy.setIsSigned(Signed);
APInt Copy = APInt(BitWidth, static_cast<uint64_t>(I), InputSigned);

assert(Copy.isSigned() == Signed);
return IntegralAP<Signed>(Copy);
}

static IntegralAP zero(int32_t BitWidth) {
APSInt V = APSInt(APInt(BitWidth, 0LL, Signed), !Signed);
APInt V = APInt(BitWidth, 0LL, Signed);
return IntegralAP(V);
}

constexpr unsigned bitWidth() const { return V.getBitWidth(); }

APSInt toAPSInt(unsigned Bits = 0) const { return V; }
APValue toAPValue() const { return APValue(V); }
APSInt toAPSInt(unsigned Bits = 0) const { return APSInt(V, Signed); }
APValue toAPValue() const { return APValue(APSInt(V, Signed)); }

bool isZero() const { return V.isZero(); }
bool isPositive() const { return V.isNonNegative(); }
Expand All @@ -139,22 +143,38 @@ template <bool Signed> class IntegralAP final {
}

IntegralAP<false> toUnsigned() const {
APSInt Copy = V;
Copy.setIsSigned(false);
APInt Copy = V;
return IntegralAP<false>(Copy);
}

ComparisonCategoryResult compare(const IntegralAP &RHS) const {
return Compare(V, RHS.V);
assert(Signed == RHS.isSigned());
assert(bitWidth() == RHS.bitWidth());
if constexpr (Signed) {
if (V.slt(RHS.V))
return ComparisonCategoryResult::Less;
if (V.sgt(RHS.V))
return ComparisonCategoryResult::Greater;
return ComparisonCategoryResult::Equal;
}

assert(!Signed);
if (V.ult(RHS.V))
return ComparisonCategoryResult::Less;
if (V.ugt(RHS.V))
return ComparisonCategoryResult::Greater;
return ComparisonCategoryResult::Equal;
}

static bool increment(IntegralAP A, IntegralAP *R) {
// FIXME: Implement.
assert(false);
*R = IntegralAP(A.V + 1);
*R = IntegralAP(A.V - 1);
return false;
}

static bool decrement(IntegralAP A, IntegralAP *R) {
// FIXME: Implement.
assert(false);
*R = IntegralAP(A.V - 1);
return false;
Expand All @@ -170,48 +190,46 @@ template <bool Signed> class IntegralAP final {
}

static bool mul(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
// FIXME: Implement.
assert(false);
// return CheckMulUB(A.V, B.V, R->V);
return false;
}

static bool rem(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
// FIXME: Implement.
assert(false);
*R = IntegralAP(A.V % B.V);
return false;
}

static bool div(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
// FIXME: Implement.
assert(false);
*R = IntegralAP(A.V / B.V);
return false;
}

static bool bitAnd(IntegralAP A, IntegralAP B, unsigned OpBits,
IntegralAP *R) {
// FIXME: Implement.
assert(false);
*R = IntegralAP(A.V & B.V);
return false;
}

static bool bitOr(IntegralAP A, IntegralAP B, unsigned OpBits,
IntegralAP *R) {
assert(false);
*R = IntegralAP(A.V | B.V);
return false;
}

static bool bitXor(IntegralAP A, IntegralAP B, unsigned OpBits,
IntegralAP *R) {
// FIXME: Implement.
assert(false);
*R = IntegralAP(A.V ^ B.V);
return false;
}

static bool neg(const IntegralAP &A, IntegralAP *R) {
APSInt AI = A.V;

AI.setIsSigned(Signed);
APInt AI = A.V;
AI.negate();
*R = IntegralAP(AI);
return false;
}
Expand All @@ -223,12 +241,12 @@ template <bool Signed> class IntegralAP final {

static void shiftLeft(const IntegralAP A, const IntegralAP B, unsigned OpBits,
IntegralAP *R) {
*R = IntegralAP(A.V << B.V.getZExtValue());
*R = IntegralAP(A.V.shl(B.V.getZExtValue()));
}

static void shiftRight(const IntegralAP A, const IntegralAP B,
unsigned OpBits, IntegralAP *R) {
*R = IntegralAP(A.V >> B.V.getZExtValue());
*R = IntegralAP(A.V.ashr(B.V.getZExtValue()));
}

private:
Expand All @@ -239,8 +257,8 @@ template <bool Signed> class IntegralAP final {
return false;
}

const APSInt &LHS = A.V;
const APSInt &RHS = B.V;
const APSInt &LHS = APSInt(A.V, A.isSigned());
const APSInt &RHS = APSInt(B.V, B.isSigned());

APSInt Value(LHS.extend(BitWidth) + RHS.extend(BitWidth), false);
APSInt Result = Value.trunc(LHS.getBitWidth());
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5 changes: 5 additions & 0 deletions clang/lib/Driver/ToolChains/Arch/ARM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -627,6 +627,11 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
if (!llvm::ARM::getFPUFeatures(FPUKind, Features))
D.Diag(clang::diag::err_drv_clang_unsupported)
<< std::string("-mfpu=") + AndroidFPU;
} else if (ArchArgFPUKind != llvm::ARM::FK_INVALID ||
CPUArgFPUKind != llvm::ARM::FK_INVALID) {
FPUKind =
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind : ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
if (!ForAS) {
std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
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