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Config: Enable multiblock by default Vixl Simulator run #7084: Pull request #4327 opened by bylaws
February 4, 2025 16:51 7m 34s bylaws:mbdef
bylaws:mbdef
February 4, 2025 16:51 7m 34s
Frontend: Split blocks at jump target boundaries Vixl Simulator run #7083: Pull request #4326 opened by bylaws
February 4, 2025 16:51 2m 40s bylaws:mbfast2
bylaws:mbfast2
February 4, 2025 16:51 2m 40s
FEXCore: Don't copy IR after compilation Vixl Simulator run #7082: Pull request #4325 opened by bylaws
February 4, 2025 16:47 4m 0s bylaws:ircopy2
bylaws:ircopy2
February 4, 2025 16:47 4m 0s
FEXCore/JIT: Pass Softfloat arguments as vector registers Vixl Simulator run #7081: Pull request #4324 synchronize by Sonicadvance1
February 4, 2025 01:47 3m 32s Sonicadvance1:vector_reg_x87
Sonicadvance1:vector_reg_x87
February 4, 2025 01:47 3m 32s
FEXCore/JIT: Pass Softfloat arguments as vector registers Vixl Simulator run #7080: Pull request #4324 synchronize by Sonicadvance1
February 3, 2025 23:48 3m 30s Sonicadvance1:vector_reg_x87
Sonicadvance1:vector_reg_x87
February 3, 2025 23:48 3m 30s
FEXCore/JIT: Pass Softfloat arguments as vector registers Vixl Simulator run #7079: Pull request #4324 synchronize by Sonicadvance1
February 3, 2025 23:42 4m 48s Sonicadvance1:vector_reg_x87
Sonicadvance1:vector_reg_x87
February 3, 2025 23:42 4m 48s
FEXCore/JIT: Pass Softfloat arguments as vector registers Vixl Simulator run #7078: Pull request #4324 opened by Sonicadvance1
February 3, 2025 23:39 5m 33s Sonicadvance1:vector_reg_x87
Sonicadvance1:vector_reg_x87
February 3, 2025 23:39 5m 33s
FEXCore/JIT: Encode the JITRIPReconstructionEntries using variable length integer Vixl Simulator run #7077: Pull request #4302 synchronize by Sonicadvance1
February 3, 2025 19:55 17m 34s Sonicadvance1:vl_jit_reconstruction
Sonicadvance1:vl_jit_reconstruction
February 3, 2025 19:55 17m 34s
FEX: Implements new sampling based stats Vixl Simulator run #7076: Pull request #4291 synchronize by Sonicadvance1
February 3, 2025 19:54 13m 27s Sonicadvance1:profile_stats
Sonicadvance1:profile_stats
February 3, 2025 19:54 13m 27s
GdbServer: Implement new netstream that can be interrupted Vixl Simulator run #7075: Pull request #4223 synchronize by Sonicadvance1
February 3, 2025 19:54 8m 9s Sonicadvance1:netstream_timeout
Sonicadvance1:netstream_timeout
February 3, 2025 19:54 8m 9s
Merge pull request #4322 from Sonicadvance1/protect_first_page_altstack Vixl Simulator run #7074: Commit 62cfc26 pushed by Sonicadvance1
February 3, 2025 19:53 6m 6s main
main
February 3, 2025 19:53 6m 6s
SignalDelegator: Protect first page of the altstack Vixl Simulator run #7073: Pull request #4322 opened by Sonicadvance1
February 3, 2025 07:23 5m 9s Sonicadvance1:protect_first_page_altstack
Sonicadvance1:protect_first_page_altstack
February 3, 2025 07:23 5m 9s
Merge pull request #4315 from neobrain/refactor_irdumper_const Vixl Simulator run #7072: Commit 713ebf1 pushed by Sonicadvance1
January 31, 2025 22:57 17m 22s main
main
January 31, 2025 22:57 17m 22s
Merge pull request #4317 from neobrain/change_fexserver_close_timeout Vixl Simulator run #7071: Commit 26e50ef pushed by Sonicadvance1
January 31, 2025 22:56 12m 48s main
main
January 31, 2025 22:56 12m 48s
Merge pull request #4316 from neobrain/fix_check_catch2_version Vixl Simulator run #7070: Commit c892899 pushed by Sonicadvance1
January 31, 2025 22:56 7m 51s main
main
January 31, 2025 22:56 7m 51s
Merge pull request #4318 from neobrain/fix_allocator_format_string Vixl Simulator run #7069: Commit e1f378c pushed by Sonicadvance1
January 31, 2025 22:56 3m 17s main
main
January 31, 2025 22:56 3m 17s
Allocator: Fix format string Vixl Simulator run #7068: Pull request #4318 opened by neobrain
January 31, 2025 14:30 11m 59s neobrain:fix_allocator_format_string
neobrain:fix_allocator_format_string
January 31, 2025 14:30 11m 59s
FEXServer: Lower close timeout Vixl Simulator run #7067: Pull request #4317 opened by neobrain
January 31, 2025 14:27 10m 15s neobrain:change_fexserver_close_timeout
neobrain:change_fexserver_close_timeout
January 31, 2025 14:27 10m 15s
CMake: Check for compatible Catch2 versions Vixl Simulator run #7066: Pull request #4316 opened by neobrain
January 31, 2025 14:24 9m 48s neobrain:fix_check_catch2_version
neobrain:fix_check_catch2_version
January 31, 2025 14:24 9m 48s
IRDumper: Allow const RA data Vixl Simulator run #7065: Pull request #4315 opened by neobrain
January 31, 2025 14:22 5m 41s neobrain:refactor_irdumper_const
neobrain:refactor_irdumper_const
January 31, 2025 14:22 5m 41s
FEXCore/JIT: Encode the JITRIPReconstructionEntries using variable length integer Vixl Simulator run #7064: Pull request #4302 synchronize by Sonicadvance1
January 30, 2025 23:08 4m 14s Sonicadvance1:vl_jit_reconstruction
Sonicadvance1:vl_jit_reconstruction
January 30, 2025 23:08 4m 14s
Merge pull request #4313 from pmatos/StartupSleepname Vixl Simulator run #7063: Commit 55cbb0b pushed by Sonicadvance1
January 30, 2025 15:44 8m 27s main
main
January 30, 2025 15:44 8m 27s
Merge pull request #4311 from pmatos/RevertPredRA Vixl Simulator run #7062: Commit db7fb56 pushed by Sonicadvance1
January 30, 2025 15:41 7m 42s main
main
January 30, 2025 15:41 7m 42s
Merge pull request #4309 from pmatos/3DnowSkip Vixl Simulator run #7061: Commit 2bed744 pushed by Sonicadvance1
January 30, 2025 15:40 3m 22s main
main
January 30, 2025 15:40 3m 22s
Merge pull request #4314 from neobrain/fix_tso_ldr_bitmask Vixl Simulator run #7060: Commit 0019bde pushed by Sonicadvance1
January 30, 2025 14:32 3m 20s main
main
January 30, 2025 14:32 3m 20s
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