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Enhance protocol stacks with advanced timing and synchronization management.
1 parent 57c9c93 commit 6ee003a

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3 files changed

+112
-59
lines changed

3 files changed

+112
-59
lines changed

‎src/can_protocol/can_controller.vhd

+4-2
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,9 @@ entity can_controller is
1010
tx : out STD_LOGIC;
1111
data_in : in STD_LOGIC_VECTOR(63 downto 0);
1212
data_out : out STD_LOGIC_VECTOR(63 downto 0);
13-
data_valid : out STD_LOGIC
13+
data_valid : out STD_LOGIC;
14+
sync : in STD_LOGIC;
15+
bit_time : in STD_LOGIC_VECTOR(15 downto 0)
1416
);
1517
end can_controller;
1618

@@ -34,7 +36,7 @@ begin
3436
crc <= (others => '0');
3537
tx <= '1';
3638
data_valid <= '0';
37-
elsif rising_edge(clk) then
39+
elsif rising_edge(clk) and sync = '1' then
3840
case state is
3941
when IDLE =>
4042
if rx = '0' then -- Start of Frame detected

‎src/lin_protocol/lin_protocol.vhd

+36-57
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,9 @@ entity lin_controller is
1010
tx : out STD_LOGIC;
1111
data_in : in STD_LOGIC_VECTOR(63 downto 0);
1212
data_out : out STD_LOGIC_VECTOR(63 downto 0);
13-
data_valid : out STD_LOGIC
13+
data_valid : out STD_LOGIC;
14+
sync : in STD_LOGIC;
15+
bit_time : in STD_LOGIC_VECTOR(15 downto 0)
1416
);
1517
end lin_controller;
1618

@@ -25,11 +27,9 @@ architecture Behavioral of lin_controller is
2527
signal checksum : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
2628

2729
constant SYNC_BYTE : STD_LOGIC_VECTOR(7 downto 0) := x"55";
28-
constant BIT_TIME : integer := 50; -- Assuming 20kbps LIN speed with 1MHz clock
2930

3031
begin
3132
process(clk, rst)
32-
variable bit_time_counter : integer range 0 to BIT_TIME-1 := 0;
3333
begin
3434
if rst = '1' then
3535
state <= IDLE;
@@ -41,83 +41,62 @@ begin
4141
checksum <= (others => '0');
4242
tx <= '1';
4343
data_valid <= '0';
44-
elsif rising_edge(clk) then
44+
elsif rising_edge(clk) and sync = '1' then
4545
case state is
4646
when IDLE =>
4747
tx <= '1';
4848
if rx = '0' then -- Start bit detected
4949
state <= SYNC;
5050
bit_counter <= 0;
51-
bit_time_counter := 0;
5251
end if;
5352

5453
when SYNC =>
55-
if bit_time_counter = BIT_TIME-1 then
56-
bit_time_counter := 0;
57-
if bit_counter < 8 then
58-
shift_reg <= shift_reg(6 downto 0) & rx;
59-
bit_counter <= bit_counter + 1;
54+
if bit_counter < 8 then
55+
shift_reg <= shift_reg(6 downto 0) & rx;
56+
bit_counter <= bit_counter + 1;
57+
else
58+
if shift_reg = SYNC_BYTE then
59+
state <= IDENTIFIER;
60+
bit_counter <= 0;
6061
else
61-
if shift_reg = SYNC_BYTE then
62-
state <= IDENTIFIER;
63-
bit_counter <= 0;
64-
else
65-
state <= IDLE;
66-
end if;
62+
state <= IDLE;
6763
end if;
68-
else
69-
bit_time_counter := bit_time_counter + 1;
7064
end if;
7165

7266
when IDENTIFIER =>
73-
if bit_time_counter = BIT_TIME-1 then
74-
bit_time_counter := 0;
75-
if bit_counter < 6 then
76-
identifier <= identifier(4 downto 0) & rx;
77-
bit_counter <= bit_counter + 1;
78-
else
79-
state <= DATA;
80-
bit_counter <= 0;
81-
byte_counter <= 0;
82-
end if;
67+
if bit_counter < 6 then
68+
identifier <= identifier(4 downto 0) & rx;
69+
bit_counter <= bit_counter + 1;
8370
else
84-
bit_time_counter := bit_time_counter + 1;
71+
state <= DATA;
72+
bit_counter <= 0;
73+
byte_counter <= 0;
8574
end if;
8675

8776
when DATA =>
88-
if bit_time_counter = BIT_TIME-1 then
89-
bit_time_counter := 0;
90-
if bit_counter < 8 then
91-
shift_reg <= shift_reg(6 downto 0) & rx;
92-
bit_counter <= bit_counter + 1;
93-
else
94-
data_buffer((7-byte_counter)*8+7 downto (7-byte_counter)*8) <= shift_reg;
95-
byte_counter <= byte_counter + 1;
96-
bit_counter <= 0;
97-
if byte_counter = 7 then
98-
state <= CHECKSUM;
99-
end if;
100-
end if;
77+
if bit_counter < 8 then
78+
shift_reg <= shift_reg(6 downto 0) & rx;
79+
bit_counter <= bit_counter + 1;
10180
else
102-
bit_time_counter := bit_time_counter + 1;
81+
data_buffer((7-byte_counter)*8+7 downto (7-byte_counter)*8) <= shift_reg;
82+
byte_counter <= byte_counter + 1;
83+
bit_counter <= 0;
84+
if byte_counter = 7 then
85+
state <= CHECKSUM;
86+
end if;
10387
end if;
10488

10589
when CHECKSUM =>
106-
if bit_time_counter = BIT_TIME-1 then
107-
bit_time_counter := 0;
108-
if bit_counter < 8 then
109-
checksum <= checksum(6 downto 0) & rx;
110-
bit_counter <= bit_counter + 1;
111-
else
112-
-- Verify checksum (simplified)
113-
if checksum = x"AA" then -- Example checksum
114-
data_out <= data_buffer;
115-
data_valid <= '1';
116-
end if;
117-
state <= IDLE;
118-
end if;
90+
if bit_counter < 8 then
91+
checksum <= checksum(6 downto 0) & rx;
92+
bit_counter <= bit_counter + 1;
11993
else
120-
bit_time_counter := bit_time_counter + 1;
94+
-- Verify checksum (simplified)
95+
if checksum = x"AA" then -- Example checksum
96+
data_out <= data_buffer;
97+
data_valid <= '1';
98+
end if;
99+
state <= IDLE;
121100
end if;
122101
end case;
123102
end if;

‎src/timing_sync_manager.vhd

+72
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
1+
library IEEE;
2+
use IEEE.STD_LOGIC_1164.ALL;
3+
use IEEE.NUMERIC_STD.ALL;
4+
5+
entity timing_sync_manager is
6+
Port (
7+
clk : in STD_LOGIC;
8+
rst : in STD_LOGIC;
9+
protocol_select : in STD_LOGIC_VECTOR(1 downto 0);
10+
can_sync : out STD_LOGIC;
11+
lin_sync : out STD_LOGIC;
12+
flexray_sync : out STD_LOGIC;
13+
can_bit_time : out STD_LOGIC_VECTOR(15 downto 0);
14+
lin_bit_time : out STD_LOGIC_VECTOR(15 downto 0);
15+
flexray_cycle_time : out STD_LOGIC_VECTOR(31 downto 0)
16+
);
17+
end timing_sync_manager;
18+
19+
architecture Behavioral of timing_sync_manager is
20+
constant CAN_BIT_TIME : unsigned(15 downto 0) := to_unsigned(1000, 16); -- 1us for 1Mbps
21+
constant LIN_BIT_TIME : unsigned(15 downto 0) := to_unsigned(50000, 16); -- 50us for 20kbps
22+
constant FLEXRAY_CYCLE_TIME : unsigned(31 downto 0) := to_unsigned(5000000, 32); -- 5ms cycle time
23+
24+
signal can_counter : unsigned(15 downto 0) := (others => '0');
25+
signal lin_counter : unsigned(15 downto 0) := (others => '0');
26+
signal flexray_counter : unsigned(31 downto 0) := (others => '0');
27+
28+
begin
29+
process(clk, rst)
30+
begin
31+
if rst = '1' then
32+
can_counter <= (others => '0');
33+
lin_counter <= (others => '0');
34+
flexray_counter <= (others => '0');
35+
can_sync <= '0';
36+
lin_sync <= '0';
37+
flexray_sync <= '0';
38+
elsif rising_edge(clk) then
39+
-- CAN timing
40+
if can_counter = CAN_BIT_TIME - 1 then
41+
can_counter <= (others => '0');
42+
can_sync <= '1';
43+
else
44+
can_counter <= can_counter + 1;
45+
can_sync <= '0';
46+
end if;
47+
48+
-- LIN timing
49+
if lin_counter = LIN_BIT_TIME - 1 then
50+
lin_counter <= (others => '0');
51+
lin_sync <= '1';
52+
else
53+
lin_counter <= lin_counter + 1;
54+
lin_sync <= '0';
55+
end if;
56+
57+
-- FlexRay timing
58+
if flexray_counter = FLEXRAY_CYCLE_TIME - 1 then
59+
flexray_counter <= (others => '0');
60+
flexray_sync <= '1';
61+
else
62+
flexray_counter <= flexray_counter + 1;
63+
flexray_sync <= '0';
64+
end if;
65+
end if;
66+
end process;
67+
68+
can_bit_time <= std_logic_vector(CAN_BIT_TIME);
69+
lin_bit_time <= std_logic_vector(LIN_BIT_TIME);
70+
flexray_cycle_time <= std_logic_vector(FLEXRAY_CYCLE_TIME);
71+
72+
end Behavioral;

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