Optimize a few high-frequency functions

Author: vintagepc

hw/arm/prusa/stm32_common/stm32_adc.c

@@ -345,7 +345,7 @@ static void stm32_adc_schedule_next(COM_STRUCT_NAME(Adc) *s) {
 	}
 
 	// Calculate the clock rate
-	uint64_t clock = stm32_rcc_if_get_periph_freq(&s->parent);
+	uint64_t clock = s->parent.clock_freq;
 
 	if (s->adcc)
 	{

hw/arm/prusa/stm32_common/stm32_common.c

@@ -14,10 +14,6 @@
 #include "stm32_rcc_if.h"
 #include "stm32_shared.h"
 
-DECLARE_CLASS_CHECKERS(STM32PeripheralClass, STM32_PERIPHERAL, TYPE_STM32_PERIPHERAL);
-
-DECLARE_INSTANCE_CHECKER(STM32Peripheral, STM32_PERIPHERAL, TYPE_STM32_PERIPHERAL);
-
 static bool create_if_not_exist(const char* default_name, uint32_t file_size)
 {
 	bool exists = true;
@@ -178,6 +174,15 @@ extern DeviceState* stm32_soc_get_periph(DeviceState* soc, stm32_periph_t id)
 	return s->perhiperhals[id];
 }
 
+static void stm32_peripheral_clock_change(void *opaque, int n, int level)
+{
+    STM32Peripheral *p = STM32_PERIPHERAL(opaque);
+    p->clock_enabled = stm32_rcc_if_check_periph_clk(p);
+    p->clock_freq = stm32_rcc_if_get_periph_freq(p);
+    STM32PeripheralClass *c = STM32_PERIPHERAL_GET_CLASS(opaque);
+    if (c->clock_update)
+        c->clock_update(p);
+}
 
 static void stm32_peripheral_rcc_reset(void *opaque, int n, int level)
 {
@@ -274,6 +279,10 @@ extern void stm32_soc_realize_peripheral(DeviceState* soc_state, stm32_periph_t
 		 	sysbus_mmio_map(SYS_BUS_DEVICE(s->perhiperhals[id]), 0, cfg->base_addr);
 		}
 	}
+    if (stm32_rcc_if_has_clk(STM32_PERIPHERAL(s->perhiperhals[id])))
+    {
+        stm32_rcc_if_set_periph_clk_irq(STM32_PERIPHERAL(s->perhiperhals[id]), qdev_get_gpio_in_named(s->perhiperhals[id],"clock-change",0));
+    }
 	for (const int *irq = cfg->irq; *irq != -1; irq++)
 	{
 		sysbus_connect_irq(SYS_BUS_DEVICE(s->perhiperhals[id]), irq-(cfg->irq), qdev_get_gpio_in(s->cpu, *irq));
@@ -300,6 +309,7 @@ extern void stm32_soc_realize_all_peripherals(DeviceState *soc_state,Error **err
 static void stm32_peripheral_instance_init(Object* obj)
 {
 	qdev_init_gpio_in_named(DEVICE(obj),  stm32_peripheral_rcc_reset, "rcc-reset",1);
+    qdev_init_gpio_in_named(DEVICE(obj),  stm32_peripheral_clock_change, "clock-change",1);
 	STM32Peripheral *s = STM32_PERIPHERAL(obj);
     qdev_init_gpio_out_named(DEVICE(obj),s->dmar,"dmar",2);
 }

hw/arm/prusa/stm32_common/stm32_common.h

@@ -34,6 +34,9 @@ typedef struct STM32Peripheral
 
 	struct STM32COMRccState* rcc; // RCC interfacing with clocktree.
 
+    // The clock frequency as output from the RCC
+    uint32_t clock_freq;
+    bool clock_enabled;
 	/* DMA IRQ. To send a periperhal DMA Request, set the level to the peripheral's data register.
 	* The DMA controller will check against its active streams for a match. and service it if one is found.
 	* Use index 1 if this is meant to be a write (M2P) or "ready for data" case - some peripherals have
@@ -43,6 +46,8 @@ typedef struct STM32Peripheral
 
 } STM32Peripheral;
 
+DECLARE_INSTANCE_CHECKER(STM32Peripheral, STM32_PERIPHERAL, TYPE_STM32_PERIPHERAL);
+
 enum DMAR_TYPE {
 	DMAR_TYPE_BEGIN,
 	DMAR_P2M = 0, // Read operation, i.e. DMA takes data from the device.
@@ -58,8 +63,12 @@ enum EXTI_TRANS {
 typedef struct STM32PeripheralClass
 {
 	SysBusDeviceClass parent;
+    // A handler to set a callback if the input clock changes.
+    void (*clock_update)(STM32Peripheral *p);
 } STM32PeripheralClass;
 
+DECLARE_CLASS_CHECKERS(STM32PeripheralClass, STM32_PERIPHERAL, TYPE_STM32_PERIPHERAL);
+
 // Common class data for variant storage.
 
 // Machine class templates:

hw/arm/prusa/stm32_common/stm32_crc.c

@@ -140,7 +140,7 @@ static unsigned long crctable[256] =
 };
 
 typedef struct COM_CLASS_NAME(Crc) {
-	SysBusDeviceClass parent_class;
+	STM32PeripheralClass parent_class;
     stm32_reginfo_t var_reginfo[RI_END];
 } COM_CLASS_NAME(Crc);
 

hw/arm/prusa/stm32_common/stm32_dma.c

@@ -143,7 +143,7 @@ enum interrupt_bits
 static const uint8_t dma_xfer_size_b[4] = {1, 2, 4, 0};
 
 typedef struct COM_CLASS_NAME(Dma) {
-	SysBusDeviceClass parent_class;
+	STM32PeripheralClass parent_class;
     stm32_reginfo_t var_reginfo[RI_END];
 } COM_CLASS_NAME(Dma);
 

hw/arm/prusa/stm32_common/stm32_gpio.c

@@ -69,7 +69,7 @@ typedef struct COM_STRUCT_NAME(Gpio) {
 } COM_STRUCT_NAME(Gpio);
 
 typedef struct COM_CLASS_NAME(Gpio) {
-	SysBusDeviceClass parent_class;
+	STM32PeripheralClass parent_class;
     stm32_reginfo_t var_reginfo[MAX_GPIO_BANKS][RI_END];
 } COM_CLASS_NAME(Gpio);
 

hw/arm/prusa/stm32_common/stm32_iwdg.c

@@ -135,7 +135,7 @@ static void stm32_common_iwdg_update(COM_STRUCT_NAME(Iwdg) *s){
     if (!s->started){
         return;
     }
-    uint32_t clkrate = stm32_rcc_if_get_periph_freq(&s->parent);
+    uint32_t clkrate = s->parent.clock_freq;
 	if (clkrate == 0)
 	{
 		qemu_log_mask(LOG_GUEST_ERROR,"ERR: Attempted to enable IWDG with LSI clock disabled!\n");

hw/arm/prusa/stm32_common/stm32_rcc.c

@@ -76,6 +76,18 @@ bool stm32_rcc_if_check_periph_clk(STM32Peripheral *p)
     return true;
 }
 
+bool stm32_rcc_if_has_clk(STM32Peripheral *p)
+{
+	if (p->rcc == NULL)
+	{
+		return 0;
+	}
+	COM_STRUCT_NAME(Rcc) *s = STM32COM_RCC(p->rcc);
+    Clk_t* clk = &s->pclocks[p->periph];
+
+    return clk->is_initialized;
+}
+
 void stm32_rcc_if_set_periph_clk_irq(
         STM32Peripheral *p,
         qemu_irq periph_irq)

hw/arm/prusa/stm32_common/stm32_rcc_if.h

@@ -30,6 +30,9 @@ extern uint32_t stm32_rcc_if_get_periph_freq(STM32Peripheral *p);
 // Checks if a clock is enabled and prints a guest error if not
 extern bool stm32_rcc_if_check_periph_clk(STM32Peripheral *p);
 
+// Checks if a clock is initialized and prints a guest error if not
+extern bool stm32_rcc_if_has_clk(STM32Peripheral *p);
+
 /* Sets the IRQ to be called when the specified peripheral clock changes
  * frequency. */
 extern void stm32_rcc_if_set_periph_clk_irq(

hw/arm/prusa/stm32_common/stm32_usart.c

@@ -315,7 +315,7 @@ static const uint16_t PRESCALE_DIV[] = {
 /* Update the baud rate based on the USART's peripheral clock frequency. */
 static void stm32_common_usart_baud_update(COM_STRUCT_NAME(Usart) *s)
 {
-    uint32_t clk_freq = stm32_rcc_if_get_periph_freq(&s->parent);
+    uint32_t clk_freq = s->parent.clock_freq;
 
     uint64_t ns_per_bit;
 

hw/arm/prusa/stm32f407/stm32_uart.c

@@ -67,9 +67,10 @@
 /* HELPER FUNCTIONS */
 
 /* Update the baud rate based on the USART's peripheral clock frequency. */
-static void stm32_uart_baud_update(Stm32Uart *s)
+static void stm32_uart_baud_update(STM32Peripheral *p)
 {
-    uint32_t clk_freq = stm32_rcc_if_get_periph_freq(&s->parent);
+    Stm32Uart *s = STM32_UART(p);
+    uint32_t clk_freq = s->parent.clock_freq;
 
     uint64_t ns_per_bit;
 
@@ -101,19 +102,6 @@ static void stm32_uart_baud_update(Stm32Uart *s)
 #endif
 }
 
-/* Handle a change in the peripheral clock. */
-static void stm32_uart_clk_irq_handler(void *opaque, int n, int level)
-{
-    Stm32Uart *s = STM32_UART(opaque);
-
-    assert(n == 0);
-
-    /* Only update the BAUD rate if the IRQ is being set. */
-    if(level) {
-        stm32_uart_baud_update(s);
-    }
-}
-
 /* Routine which updates the USART's IRQ.  This should be called whenever
  * an interrupt-related flag is updated.
  */
@@ -523,7 +511,7 @@ static void stm32_uart_write(void *opaque, hwaddr addr,
             break;
         case USART_BRR_OFFSET:
             s->regs[addr] = data;
-            stm32_uart_baud_update(s);
+            stm32_uart_baud_update(STM32_PERIPHERAL(s));
             break;
         case USART_CR1_OFFSET:
 		case USART_CR3_OFFSET:
@@ -583,10 +571,6 @@ static void stm32_uart_init(Object *obj)
         timer_new_ns(QEMU_CLOCK_VIRTUAL,
                   (QEMUTimerCB *)stm32_uart_idle_timer_expire, s);
 
-    /* Register handlers to handle updates to the USART's peripheral clock. */
-    s->clk_irq =
-          qemu_allocate_irqs(stm32_uart_clk_irq_handler, (void *)s, 1);
-	stm32_rcc_if_set_periph_clk_irq(&s->parent, s->clk_irq[0]);
 
     //stm32_uart_connect(s, &s->chr);
 
@@ -662,6 +646,9 @@ static void stm32_uart_class_init(ObjectClass *klass, void *data)
     device_class_set_props(dc, stm32_uart_properties);
     dc->realize = stm32_uart_realize;
     dc->vmsd = &vmstate_stm32_uart;
+
+    STM32PeripheralClass *k = STM32_PERIPHERAL_CLASS(klass);
+    k->clock_update = stm32_uart_baud_update;
 }
 
 static TypeInfo stm32_uart_info = {

hw/arm/prusa/stm32f407/stm32f2xx_tim.c

@@ -110,14 +110,14 @@ enum OCxM_val
 static uint32_t
 f2xx_tim_period(f2xx_tim *s, uint64_t multiplier)
 {
-    uint64_t clock_freq = stm32_rcc_if_get_periph_freq(&s->parent);
+    uint64_t clock_freq = s->parent.clock_freq;
     clock_freq/= (s->defs.PSC+1);
     return muldiv64(1000000000ULL,multiplier,clock_freq);
 }
 
 static inline int64_t f2xx_tim_ns_to_ticks(f2xx_tim *s, int64_t t)
 {
-    uint64_t clock_freq = stm32_rcc_if_get_periph_freq(&s->parent);
+    uint64_t clock_freq = s->parent.clock_freq;
 	if (clock_freq == 0)
 		return 0;
 	else

hw/arm/prusa/stm32f407/stm32f4xx_adc.c

@@ -174,6 +174,9 @@ struct STM32F4XXADCState {
 
     uint8_t adc_sequence_position, adc_next_seq_pos;
 
+    // Pre-computed conversion times
+    uint64_t adc_conv_times_ns[ADC_NUM_REG_CHANNELS];
+
     QEMUTimer* next_eoc;
 };
 
@@ -194,6 +197,8 @@ typedef union {
     } QEMU_PACKED;
 } adc_smpr_t;
 
+static const uint16_t adc_smpr_map[] = { 3, 15, 28, 56, 84, 112, 144, 480 };
+
 static void stm32f4xx_adc_reset(DeviceState *dev)
 {
     STM32F4XXADCState *s = STM32F4xx_ADC(dev);
@@ -210,29 +215,6 @@ static void stm32f4xx_adc_reset(DeviceState *dev)
 		timer_del(s->next_eoc);
 }
 
-static uint16_t adc_lookup_smpr(uint8_t value) {
-    switch (value) {
-        case 0:
-            return 3;
-        case 1:
-            return 15;
-        case 2:
-            return 28;
-        case 3:
-            return 56;
-        case 4:
-            return 84;
-        case 5:
-            return 112;
-        case 6:
-            return 144;
-        case 7:
-            return 480;
-        default:
-            assert(false);
-            return 0;
-    }
-}
 
 static uint32_t stm32f4xx_adc_get_value(STM32F4XXADCState *s)
 {
@@ -241,7 +223,8 @@ static uint32_t stm32f4xx_adc_get_value(STM32F4XXADCState *s)
     // I'm not sure why this is yet - some sort of built in oversampling
     // that is enabled in non-DMA mode?
     if (!s->defs.CR2.DMA) {
-        s->defs.DR*=(adc_lookup_smpr(s->adc_smprs[channel])+1);
+        assert(s->adc_smprs[channel] < ARRAY_SIZE(adc_smpr_map));
+        s->defs.DR*=(adc_smpr_map[s->adc_smprs[channel]]+1);
     }
 
     // Mask: RES 0..3 == 12..6 bit mask.
@@ -261,32 +244,33 @@ static void stm32f4xx_adc_data_in(void *opaque, int n, int level){
     // printf("ADC: Ch %d new data: %d\n",n, level);
 }
 
-static void stm32f4xx_adc_schedule_next(STM32F4XXADCState *s) {
-    if (!s->defs.CR2.ADON)
-        return;
-    s->defs.CR2.SWSTART = 0;
-    // Calculate the clock rate
-    uint64_t clock = stm32_rcc_if_get_periph_freq(&s->parent);
-
+static void stm32f4xx_adc_recalc_times(STM32F4XXADCState *s) {
+    // Get the clock rate
+    uint64_t clock = s->parent.clock_freq;
     clock /= stm32f4xx_adcc_get_adcpre(s->common);
-
-    // #bits:
     uint32_t conv_cycles = (12U - (s->defs.CR1.RES<<1U));
-    uint8_t channel = s->adc_sequence[s->adc_next_seq_pos];
-    conv_cycles += adc_lookup_smpr(s->adc_smprs[channel]);
-
-    uint64_t delay_ns = 1000000000000U / (clock/conv_cycles);
-    if (s->parent.periph == STM32_P_ADC3)
-	{
+    for (int i=0; i<ADC_NUM_REG_CHANNELS; i++)
+    {
+        assert(s->adc_smprs[i] < ARRAY_SIZE(adc_smpr_map));
+        uint32_t ch_conv_cycles = conv_cycles + adc_smpr_map[s->adc_smprs[i]];
+        s->adc_conv_times_ns[i] = 1000000000000U / (clock/ch_conv_cycles);
+        if (s->parent.periph == STM32_P_ADC3)
+        {
 		// Yes, this is an ugly-ass hack. The above calc is off by 1000 and I still need to determine
 		// how to deal with the other channels bogging down the simulation when they run at the "real" specified rate.
-		delay_ns /= 1000;
+	    	 s->adc_conv_times_ns[i] /= 1000;
 		//printf("ADC conversion: %u cycles @ %"PRIu64" Hz (%lu nSec)\n", conv_cycles, clock, delay_ns);
-	}
-    timer_mod_ns(s->next_eoc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)+delay_ns);
-
+	    }
+    }
 }
 
+static void stm32f4xx_adc_schedule_next(STM32F4XXADCState *s) {
+    if (!s->defs.CR2.ADON)
+        return;
+    s->defs.CR2.SWSTART = 0;
+    uint8_t channel = s->adc_sequence[s->adc_next_seq_pos];
+    timer_mod_ns(s->next_eoc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)+s->adc_conv_times_ns[channel]);
+}
 
 static uint64_t stm32f4xx_adc_read(void *opaque, hwaddr addr,
                                      unsigned int size)
@@ -359,7 +343,7 @@ static void stm32f4xx_adc_update_sequence(STM32F4XXADCState *s)
 static void stm32f4xx_adc_convert(STM32F4XXADCState *s)
 {
     uint8_t channel = s->adc_sequence[s->adc_sequence_position];
-    qemu_irq_pulse(s->irq_read[channel]); // Toggle the data read request IRQ. The receiver can opt to send a new value (or do nothing)
+    qemu_irq_raise(s->irq_read[channel]); // Toggle the data read request IRQ. The receiver can opt to send a new value (or do nothing)
 }
 
 static void stm32f4xx_adc_update_irqs(STM32F4XXADCState *s, int level) {
@@ -424,8 +408,17 @@ static void stm32f4xx_adc_write(void *opaque, hwaddr addr,
     }
 
     switch (addr) {
-        case RI_SR:
         case RI_CR1:
+            {
+                uint8_t old_res = s->defs.CR1.RES;
+                s->regs[addr] = value;
+                if (s->defs.CR1.RES != old_res)
+                {
+                    stm32f4xx_adc_recalc_times(s);
+                }
+            }
+            break;
+        case RI_SR:
         case RI_HTR:
         case RI_LTR:
             s->regs[addr] = value;
@@ -450,6 +443,7 @@ static void stm32f4xx_adc_write(void *opaque, hwaddr addr,
             {
                 s->adc_smprs[10+i] = (value >> (3*i)) & 0x7;
             }
+            stm32f4xx_adc_recalc_times(s);
             break;
         case RI_SMPR2:
             // if (value!=0) printf("FIXME: Nonzero sample time\n");
@@ -458,7 +452,7 @@ static void stm32f4xx_adc_write(void *opaque, hwaddr addr,
             {
                 s->adc_smprs[i] = (value >> (3*i)) & 0x7;
             }
-            break;
+            stm32f4xx_adc_recalc_times(s);
             break;
         case RI_JOFR1 ... RI_JOFR4:
             s->regs[addr] = (value & 0xFFF);