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4 | 4 | - F4xx series,
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5 | 5 | - F2xx series (? - it's modelled off the Pebble QEMU version which supports this.),
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6 | 6 |
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7 |
| - Copyright 2021 VintagePC <https://github.com/vintagepc/> |
| 7 | + Copyright 2021-2 VintagePC <https://github.com/vintagepc/> |
8 | 8 |
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9 | 9 | This file is part of Mini404.
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10 | 10 |
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22 | 22 | along with Mini404. If not, see <http://www.gnu.org/licenses/>.
|
23 | 23 | */
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24 | 24 |
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25 |
| -#include "stm32_f2xx_f4xx_dma.h" |
| 25 | +#include "qemu/osdep.h" |
26 | 26 | #include "hw/irq.h"
|
27 | 27 | #include "migration/vmstate.h"
|
28 | 28 | #include "sysemu/dma.h"
|
29 | 29 | #include "qemu/log.h"
|
| 30 | +#include "hw/sysbus.h" |
| 31 | +#include "qemu/timer.h" |
| 32 | +#include "exec/memory.h" |
| 33 | +#include "stm32_common.h" |
| 34 | +#include "stm32_shared.h" |
| 35 | + |
| 36 | +#define STM32_F2xx_DMA_MAX_CHAN 8 |
| 37 | +#define STM32_F2xx_DMA_CHAN_REGS 6 |
| 38 | + |
| 39 | +#define R_DMA_MAX (4+(STM32_F2xx_DMA_MAX_CHAN*STM32_F2xx_DMA_CHAN_REGS)) |
| 40 | + |
| 41 | +OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XX_STRUCT_NAME(Dma), STM32F4xx_DMA); |
| 42 | + |
| 43 | +#define _STM32_DMA_INT_BITSET(chan) \ |
| 44 | + REG_B32(_JOIN2R(FEIF,chan)); \ |
| 45 | + REG_R(1); \ |
| 46 | + REG_B32(_JOIN2R(DMEIF,chan)); \ |
| 47 | + REG_B32(_JOIN2R(TEIF,chan)); \ |
| 48 | + REG_B32(_JOIN2R(HTIF,chan)); \ |
| 49 | + REG_B32(_JOIN2R(TCIF,chan)); |
| 50 | + |
| 51 | + |
| 52 | +REGDEF_BLOCK_BEGIN() |
| 53 | + _STM32_DMA_INT_BITSET(0) |
| 54 | + _STM32_DMA_INT_BITSET(1) |
| 55 | + REG_R(4); |
| 56 | + _STM32_DMA_INT_BITSET(2) |
| 57 | + _STM32_DMA_INT_BITSET(3) |
| 58 | + REG_R(4); |
| 59 | +REGDEF_BLOCK_END(dma, low_int) |
| 60 | + |
| 61 | +REGDEF_BLOCK_BEGIN() |
| 62 | + _STM32_DMA_INT_BITSET(4) |
| 63 | + _STM32_DMA_INT_BITSET(5) |
| 64 | + REG_R(4); |
| 65 | + _STM32_DMA_INT_BITSET(6) |
| 66 | + _STM32_DMA_INT_BITSET(7) |
| 67 | + REG_R(4); |
| 68 | +REGDEF_BLOCK_END(dma, high_int) |
| 69 | + |
| 70 | +#undef _STM32_DMA_INT_BITSET |
| 71 | + |
| 72 | +REGDEF_BLOCK_BEGIN() |
| 73 | + REG_B32(EN); |
| 74 | + REG_B32(DMEIE); |
| 75 | + REG_B32(TEIE); |
| 76 | + REG_B32(HTIE); |
| 77 | + REG_B32(TCIE); |
| 78 | + REG_B32(PFCTRL); |
| 79 | + REG_K32(DIR,2); |
| 80 | + REG_B32(CIRC); |
| 81 | + REG_B32(PINC); |
| 82 | + REG_B32(MINC); |
| 83 | + REG_K32(PSIZE,2); |
| 84 | + REG_K32(MSIZE,2); |
| 85 | + REG_B32(PINCOS); |
| 86 | + REG_K32(PL,2); |
| 87 | + REG_B32(DBM); |
| 88 | + REG_B32(CT); |
| 89 | + REG_R(1); |
| 90 | + REG_K32(PBURST,2); |
| 91 | + REG_K32(MBURST,2); |
| 92 | + REG_K32(CHSEL,3); |
| 93 | + REG_R(4); |
| 94 | +REGDEF_BLOCK_END(dma, sxcr) |
| 95 | + |
| 96 | +REGDEF_BLOCK_BEGIN() |
| 97 | + REG_K32(FTH,2); |
| 98 | + REG_B32(DMDIS); |
| 99 | + REG_K32(FS,3); |
| 100 | + REG_R(1); |
| 101 | + REG_B32(FEIE); |
| 102 | + REG_R(24); |
| 103 | +REGDEF_BLOCK_END(dma, sxfcr) |
| 104 | + |
| 105 | +#define _STM32_DMA_CHAN_BLK(x) \ |
| 106 | + REGDEF_NAME(dma, sxcr) _JOIN2R(SCR,x); \ |
| 107 | + REG_S32(NDTR, 16) _JOIN2R(SNDTR,x); \ |
| 108 | + uint32_t _JOIN2R(SPAR,x); \ |
| 109 | + uint32_t _JOIN2R(SM0AR,x); \ |
| 110 | + uint32_t _JOIN2R(SM1AR,x); \ |
| 111 | + REGDEF_NAME(dma, sxfcr) _JOIN2R(SFCR,x); |
| 112 | + |
| 113 | + |
| 114 | + |
| 115 | +typedef struct STM32F2XX_STRUCT_NAME(Dma) { |
| 116 | + STM32Peripheral parent; |
| 117 | + MemoryRegion iomem; |
| 118 | + |
| 119 | + union { |
| 120 | + struct { |
| 121 | + REGDEF_NAME(dma, low_int) LISR; //0x00 |
| 122 | + REGDEF_NAME(dma, high_int) HISR; //0x04 |
| 123 | + REGDEF_NAME(dma, low_int) LIFCR; //0x08 |
| 124 | + REGDEF_NAME(dma, high_int) HIFCR; //0x0C |
| 125 | + _STM32_DMA_CHAN_BLK(0) //0x10 - 0x24 |
| 126 | + _STM32_DMA_CHAN_BLK(1) //0x28 - 0x3C |
| 127 | + _STM32_DMA_CHAN_BLK(2) //0x40 - 0x54 |
| 128 | + _STM32_DMA_CHAN_BLK(3) //0x58 - 0x6C |
| 129 | + _STM32_DMA_CHAN_BLK(4) //0x70 - 0x84 |
| 130 | + _STM32_DMA_CHAN_BLK(5) //0x88 - 0x9C |
| 131 | + _STM32_DMA_CHAN_BLK(6) //0xA0 - 0xB4 |
| 132 | + _STM32_DMA_CHAN_BLK(7) //0xB8 - 0xCC |
| 133 | + } defs; |
| 134 | + uint32_t raw[R_DMA_MAX]; |
| 135 | + } regs; |
| 136 | + |
| 137 | + uint32_t original_ndtrs[STM32_F2xx_DMA_MAX_CHAN]; |
| 138 | + |
| 139 | + qemu_irq irq[STM32_F2xx_DMA_MAX_CHAN]; |
| 140 | + |
| 141 | +} STM32F2XX_STRUCT_NAME(Dma); |
30 | 142 |
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31 | 143 | enum reg_index {
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32 | 144 | RI_LISR,
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@@ -484,4 +596,3 @@ stm32_f2xx_f4xx_dma_register_types(void)
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484 | 596 | }
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485 | 597 |
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486 | 598 | type_init(stm32_f2xx_f4xx_dma_register_types)
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487 |
| - |
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