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Modified for Instant as associated type in emulator-hal (#6)
* Modified for Instant as associated type in emulator-hal * Updated emulator-hal to latest
1 parent 97aef5d commit 6e7e315

11 files changed

+36
-35
lines changed

‎emulator/core/src/memory.rs

+3-2
Original file line numberDiff line numberDiff line change
@@ -388,7 +388,7 @@ pub fn dump_slice(data: &[u8], mut count: usize) {
388388

389389
pub fn dump_memory<Bus, Address, Instant>(bus: &mut Bus, clock: Instant, addr: Address, count: Address)
390390
where
391-
Bus: BusAccess<Address, Instant>,
391+
Bus: BusAccess<Address, Instant = Instant>,
392392
Address: From<u64> + Into<u64> + Copy,
393393
Instant: Copy,
394394
{
@@ -416,7 +416,8 @@ use emulator_hal::bus::{self, BusAccess};
416416

417417
impl bus::Error for Error {}
418418

419-
impl BusAccess<u64, Instant> for &mut dyn Addressable {
419+
impl BusAccess<u64> for &mut dyn Addressable {
420+
type Instant = Instant;
420421
type Error = Error;
421422

422423
fn read(&mut self, now: Instant, addr: Address, data: &mut [u8]) -> Result<usize, Self::Error> {

‎emulator/cpus/m68k/src/debugger.rs

+5-5
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,9 @@ pub enum M68kInfo {
2828
State,
2929
}
3030

31-
impl<Bus, BusError, Instant, Writer> Inspect<M68kAddress, Instant, Bus, Writer> for M68k<Instant>
31+
impl<Bus, BusError, Instant, Writer> Inspect<M68kAddress, Bus, Writer> for M68k<Instant>
3232
where
33-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
33+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
3434
BusError: bus::Error,
3535
Writer: fmt::Write,
3636
{
@@ -57,9 +57,9 @@ where
5757
}
5858

5959
/// Control the execution of a CPU device for debugging purposes
60-
impl<Bus, BusError, Instant, Writer> Debug<M68kAddress, Instant, Bus, Writer> for M68k<Instant>
60+
impl<Bus, BusError, Instant, Writer> Debug<M68kAddress, Bus, Writer> for M68k<Instant>
6161
where
62-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
62+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
6363
BusError: bus::Error,
6464
Instant: time::Instant,
6565
Writer: fmt::Write,
@@ -103,7 +103,7 @@ pub struct M68kDebugger {
103103

104104
impl<'a, Bus, BusError, Instant> M68kCycleExecutor<'a, Bus, Instant>
105105
where
106-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
106+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
107107
Instant: Copy,
108108
{
109109
pub fn check_breakpoints(&mut self) -> Result<(), M68kError<BusError>> {

‎emulator/cpus/m68k/src/decode.rs

+5-5
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ pub struct M68kDecoder<Instant> {
4141

4242
pub struct InstructionDecoding<'a, Bus, Instant>
4343
where
44-
Bus: BusAccess<M68kAddress, Instant>,
44+
Bus: BusAccess<M68kAddress, Instant = Instant>,
4545
{
4646
pub(crate) bus: &'a mut Bus,
4747
pub(crate) memory: &'a mut M68kBusPort<Instant>,
@@ -81,7 +81,7 @@ where
8181
start: u32,
8282
) -> Result<(), M68kError<Bus::Error>>
8383
where
84-
Bus: BusAccess<M68kAddress, Instant>,
84+
Bus: BusAccess<M68kAddress, Instant = Instant>,
8585
{
8686
self.init(is_supervisor, start);
8787
let mut decoding = InstructionDecoding {
@@ -95,7 +95,7 @@ where
9595

9696
pub fn dump_disassembly<Bus>(&mut self, bus: &mut Bus, memory: &mut M68kBusPort<Instant>, start: u32, length: u32)
9797
where
98-
Bus: BusAccess<M68kAddress, Instant>,
98+
Bus: BusAccess<M68kAddress, Instant = Instant>,
9999
{
100100
let mut next = start;
101101
while next < (start + length) {
@@ -117,7 +117,7 @@ where
117117

118118
pub fn dump_decoded<Bus>(&mut self, clock: Instant, bus: &mut Bus)
119119
where
120-
Bus: BusAccess<M68kAddress, Instant>,
120+
Bus: BusAccess<M68kAddress, Instant = Instant>,
121121
{
122122
let ins_data: Result<String, M68kError<Bus::Error>> = (0..((self.end - self.start) / 2))
123123
.map(|offset| Ok(format!("{:04x} ", bus.read_beu16(clock, self.start + (offset * 2)).unwrap())))
@@ -128,7 +128,7 @@ where
128128

129129
impl<'a, Bus, Instant> InstructionDecoding<'a, Bus, Instant>
130130
where
131-
Bus: BusAccess<M68kAddress, Instant>,
131+
Bus: BusAccess<M68kAddress, Instant = Instant>,
132132
Instant: Copy,
133133
{
134134
#[inline]

‎emulator/cpus/m68k/src/execute.rs

+6-6
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ where
6161
#[inline]
6262
pub fn begin<Bus>(self, cpu: &mut M68k<Instant>, bus: Bus) -> M68kCycleExecutor<'_, Bus, Instant>
6363
where
64-
Bus: BusAccess<M68kAddress, Instant>,
64+
Bus: BusAccess<M68kAddress, Instant = Instant>,
6565
{
6666
cpu.stats.cycle_number = cpu.stats.cycle_number.wrapping_add(1);
6767

@@ -74,9 +74,9 @@ where
7474
}
7575
}
7676

77-
impl<Bus, BusError, Instant> Step<M68kAddress, Instant, Bus> for M68k<Instant>
77+
impl<Bus, BusError, Instant> Step<M68kAddress, Bus> for M68k<Instant>
7878
where
79-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
79+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
8080
BusError: bus::Error,
8181
Instant: time::Instant,
8282
{
@@ -110,7 +110,7 @@ where
110110

111111
pub struct M68kCycleExecutor<'a, Bus, Instant>
112112
where
113-
Bus: BusAccess<M68kAddress, Instant>,
113+
Bus: BusAccess<M68kAddress, Instant = Instant>,
114114
{
115115
pub state: &'a mut M68kState,
116116
pub bus: Bus,
@@ -120,7 +120,7 @@ where
120120

121121
impl<'a, Bus, Instant> M68kCycleExecutor<'a, Bus, Instant>
122122
where
123-
Bus: BusAccess<M68kAddress, Instant>,
123+
Bus: BusAccess<M68kAddress, Instant = Instant>,
124124
Instant: Copy,
125125
{
126126
pub fn end(self) -> M68kCycle<Instant> {
@@ -130,7 +130,7 @@ where
130130

131131
impl<'a, Bus, Instant> M68kCycleExecutor<'a, Bus, Instant>
132132
where
133-
Bus: BusAccess<M68kAddress, Instant>,
133+
Bus: BusAccess<M68kAddress, Instant = Instant>,
134134
Instant: Copy,
135135
{
136136
#[inline]

‎emulator/cpus/m68k/src/memory.rs

+9-9
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ where
173173
data: &mut [u8],
174174
) -> Result<(), M68kError<BusError>>
175175
where
176-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
176+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
177177
{
178178
let addr = addr & self.address_mask;
179179
for i in (0..data.len()).step_by(self.data_bytewidth) {
@@ -193,7 +193,7 @@ where
193193
data: &[u8],
194194
) -> Result<(), M68kError<BusError>>
195195
where
196-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
196+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
197197
{
198198
let addr = addr & self.address_mask;
199199
for i in (0..data.len()).step_by(self.data_bytewidth) {
@@ -207,7 +207,7 @@ where
207207

208208
fn read_sized<Bus, BusError>(&mut self, bus: &mut Bus, addr: M68kAddress, size: Size) -> Result<u32, M68kError<BusError>>
209209
where
210-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
210+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
211211
{
212212
let mut data = [0; 4];
213213
match size {
@@ -226,7 +226,7 @@ where
226226
value: u32,
227227
) -> Result<(), M68kError<BusError>>
228228
where
229-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
229+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
230230
{
231231
let data = value.to_be_bytes();
232232
match size {
@@ -244,7 +244,7 @@ where
244244
size: Size,
245245
) -> Result<u32, M68kError<BusError>>
246246
where
247-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
247+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
248248
{
249249
self.start_request(is_supervisor, addr, size, MemAccess::Read, MemType::Data, false)?;
250250
self.read_sized(bus, addr, size)
@@ -259,7 +259,7 @@ where
259259
value: u32,
260260
) -> Result<(), M68kError<BusError>>
261261
where
262-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
262+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
263263
{
264264
self.start_request(is_supervisor, addr, size, MemAccess::Write, MemType::Data, false)?;
265265
self.write_sized(bus, addr, size, value)
@@ -272,7 +272,7 @@ where
272272
addr: u32,
273273
) -> Result<u16, M68kError<BusError>>
274274
where
275-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
275+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
276276
{
277277
self.request.instruction(is_supervisor, addr)?;
278278
Ok(self.read_sized(bus, addr, Size::Word)? as u16)
@@ -285,7 +285,7 @@ where
285285
addr: u32,
286286
) -> Result<u32, M68kError<BusError>>
287287
where
288-
Bus: BusAccess<M68kAddress, Instant, Error = BusError>,
288+
Bus: BusAccess<M68kAddress, Instant = Instant, Error = BusError>,
289289
{
290290
self.request.instruction(is_supervisor, addr)?;
291291
self.read_sized(bus, addr, Size::Long)
@@ -327,7 +327,7 @@ fn validate_address<BusError>(addr: u32) -> Result<u32, M68kError<BusError>> {
327327

328328
pub fn dump_memory<Bus, Address, Instant>(bus: &mut Bus, clock: Instant, addr: Address, count: Address)
329329
where
330-
Bus: BusAccess<Address, Instant>,
330+
Bus: BusAccess<Address, Instant = Instant>,
331331
Address: From<u32> + Into<u32> + Copy,
332332
Instant: Copy,
333333
{

‎emulator/cpus/m68k/src/moa.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ impl Steppable for M68k<Instant> {
1010
let cycle = M68kCycle::new(self, system.clock);
1111

1212
let mut bus = system.bus.borrow_mut();
13-
let mut adapter: bus::BusAdapter<u32, u64, Instant, &mut dyn Addressable, Error> =
13+
let mut adapter: bus::BusAdapter<u32, u64, &mut dyn Addressable, Error> =
1414
bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
1515

1616
let mut executor = cycle.begin(self, &mut adapter);
@@ -99,7 +99,7 @@ impl Debuggable for M68k<Instant> {
9999
let mut memory = M68kBusPort::from_info(&self.info, system.clock);
100100

101101
let mut bus = system.bus.borrow_mut();
102-
let mut adapter: bus::BusAdapter<u32, u64, Instant, &mut dyn Addressable, Error> =
102+
let mut adapter: bus::BusAdapter<u32, u64, &mut dyn Addressable, Error> =
103103
bus::BusAdapter::new(&mut *bus, |addr| addr as u64, |err| err);
104104

105105
decoder.dump_disassembly(&mut adapter, &mut memory, addr as u32, count as u32);

‎emulator/cpus/m68k/tests/decode_tests.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -81,10 +81,10 @@ fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, Me
8181
(cpu, cycle, memory)
8282
}
8383

84-
fn load_memory<Bus: BusAccess<u32, Instant>>(memory: &mut Bus, data: &[u16]) {
84+
fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(memory: &mut Bus, data: &[u16]) {
8585
let mut addr = INIT_ADDR;
8686
for word in data {
87-
memory.write_beu16(Instant::START, addr, *word).unwrap();
87+
memory.write_beu16(Bus::Instant::START, addr, *word).unwrap();
8888
addr += 2;
8989
}
9090
}

‎emulator/cpus/m68k/tests/execute_tests.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ fn build_state(state: &TestState) -> M68kState {
7676
new_state
7777
}
7878

79-
fn load_memory<Bus: BusAccess<u32, Instant>>(bus: &mut Bus, data: &[u16]) {
79+
fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
8080
for i in 0..data.len() {
8181
bus.write_beu16(Instant::START, (i << 1) as u32, data[i]).unwrap();
8282
}

‎emulator/cpus/m68k/tests/musashi_timing_tests.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, Me
2929
(cpu, cycle, memory)
3030
}
3131

32-
fn load_memory<Bus: BusAccess<u32, Instant>>(bus: &mut Bus, data: &[u16]) {
32+
fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
3333
let mut addr = INIT_ADDR;
3434
for word in data {
3535
bus.write_beu16(Instant::START, addr, *word).unwrap();

‎emulator/cpus/m68k/tests/timing_tests.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ fn init_decode_test(cputype: M68kType) -> (M68k<Instant>, M68kCycle<Instant>, Me
4343
(cpu, cycle, memory)
4444
}
4545

46-
fn load_memory<Bus: BusAccess<u32, Instant>>(bus: &mut Bus, data: &[u16]) {
46+
fn load_memory<Bus: BusAccess<u32, Instant = Instant>>(bus: &mut Bus, data: &[u16]) {
4747
let mut addr = INIT_ADDR;
4848
for word in data {
4949
bus.write_beu16(Instant::START, addr, *word).unwrap();

‎emulator/libraries/emulator-hal

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