Repository with SystemVerilog modules developed in the CADEMICS SV for design and verification course by SBMicro and Cadence Design Systems
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Apr 12, 2024 - SystemVerilog
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digital-ic-design
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This repository is all about design and verification...
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Nov 25, 2024 - SystemVerilog
A hardware implementation of a deep learning accelerator using SystemVerilog/Verilog, designed for efficient neural network inference. This project implements a systolic array-based matrix multiplication unit with various activation functions and supporting components.
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Mar 15, 2025 - SystemVerilog
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