Verilog: multiple port/wire/reg declarations per line results in misanalysis

[birdybro]

From this discussion here I was referred to this repository:

github-linguist/linguist#6169

Here's an example of what I mean in the title:

https://github.com/birdybro/Nand2Tetris_MiSTer/blob/master/rtl/structural/ALU.v#L35

This is valid syntax, it's just easier than putting something like this there:

module c_ALU
(
input zx,
input nx,
);