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somhisomhi
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SoCkit port
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‎Readme.md

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# Template core for [SoCkit (MiSTer) Platform](https://github.com/sockitfpga/MiSTer_SoCkit)
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Ported by @somhi from https://github.com/MiSTer-devel/Template_MiSTer
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Follows original README.
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# Template core for MiSTer
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## General description

‎mycore.qsf

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@@ -13,15 +13,15 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
@@ -50,6 +50,16 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
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set_global_assignment -name SEED 1
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
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#enable it only if 8bit indexed mode is used in core
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VERILOG_FILE sys/I2C_Controller.v
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set_global_assignment -name VERILOG_FILE sys/I2C_AV_Config.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎mycore_Q13.qpf

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This file was deleted.

‎mycore_Q13.qsf

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This file was deleted.

‎mycore_Q13.srf

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This file was deleted.

‎sys/I2C_AV_Config.v

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module I2C_AV_Config ( //Host Side
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iCLK,
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iRST_N,
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// I2C Side
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oI2C_SCLK,
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oI2C_SDAT
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);
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// Host Side
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input iCLK;
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input iRST_N;
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// I2C Side
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output oI2C_SCLK;
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inout oI2C_SDAT;
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// Internal Registers/Wires
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reg [15:0] mI2C_CLK_DIV;
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reg [23:0] mI2C_DATA;
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reg mI2C_CTRL_CLK;
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reg mI2C_GO;
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wire mI2C_END;
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wire mI2C_ACK;
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reg [15:0] LUT_DATA;
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reg [3:0] LUT_INDEX;
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reg [1:0] mSetup_ST;
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// Clock Setting
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parameter CLK_Freq = 24000000; // 24 MHz
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parameter I2C_Freq = 20000; // 20 KHz
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// LUT Data Number
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parameter LUT_SIZE = 11;
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// Audio Data Index
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parameter Dummy_DATA = 0;
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parameter SET_LIN_L = 1;
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parameter SET_LIN_R = 2;
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parameter SET_HEAD_L = 3;
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parameter SET_HEAD_R = 4;
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parameter A_PATH_CTRL = 5;
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parameter D_PATH_CTRL = 6;
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parameter POWER_ON = 7;
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parameter SET_FORMAT = 8;
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parameter SAMPLE_CTRL = 9;
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parameter SET_ACTIVE = 10;
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///////////////////// I2C Control Clock ////////////////////////
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always@(posedge iCLK or negedge iRST_N) begin
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if(!iRST_N) begin
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mI2C_CTRL_CLK <= 1'd0;
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mI2C_CLK_DIV <= 16'd0;
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end else begin
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if (mI2C_CLK_DIV < (CLK_Freq/I2C_Freq))
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mI2C_CLK_DIV <= mI2C_CLK_DIV + 16'd1;
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else begin
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mI2C_CLK_DIV <= 16'd0;
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mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
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end
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end
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end
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////////////////////////////////////////////////////////////////////
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I2C_Controller u0 (
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.CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
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.I2C_SCLK(oI2C_SCLK), // I2C CLOCK
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.I2C_SDAT(oI2C_SDAT), // I2C DATA
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.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
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.GO(mI2C_GO), // GO transfor
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.END(mI2C_END), // END transfor
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.ACK(mI2C_ACK), // ACK
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.RESET(iRST_N)
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);
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////////////////////////////////////////////////////////////////////
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////////////////////// Config Control ////////////////////////////
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always@(posedge mI2C_CTRL_CLK or negedge iRST_N) begin
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if(!iRST_N) begin
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LUT_INDEX <= 4'd0;
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mSetup_ST <= 2'd0;
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mI2C_GO <= 1'd0;
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end else begin
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if(LUT_INDEX < LUT_SIZE) begin
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case(mSetup_ST)
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0: begin
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mI2C_DATA <= {8'h34,LUT_DATA};
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mI2C_GO <= 1'd1;
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mSetup_ST <= 2'd1;
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end
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1: begin
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if(mI2C_END) begin
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if(!mI2C_ACK)
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mSetup_ST <= 2'd2;
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else
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mSetup_ST <= 2'd0;
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mI2C_GO <= 1'd0;
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end
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end
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2: begin
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LUT_INDEX <= LUT_INDEX + 4'd1;
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mSetup_ST <= 2'd0;
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end
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endcase
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end
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end
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end
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////////////////////////////////////////////////////////////////////
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///////////////////// Config Data LUT //////////////////////////
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always @ (*)
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begin
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case(LUT_INDEX)
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// Audio Config Data
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Dummy_DATA : LUT_DATA <= 16'h0000;
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SET_LIN_L : LUT_DATA <= 16'h009A;//16'h001A; //R0 LINVOL = 1Ah (+4.5bB)
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SET_LIN_R : LUT_DATA <= 16'h029A;//16'h021A; //R1 RINVOL = 1Ah (+4.5bB)
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SET_HEAD_L : LUT_DATA <= 16'h0479; //R2 LHPVOL = 7Bh (+2dB)
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SET_HEAD_R : LUT_DATA <= 16'h0679; //R3 RHPVOL = 7Bh (+2dB)
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A_PATH_CTRL : LUT_DATA <= 16'h08D2;//16'h08F8; //R4 DACSEL = 1
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D_PATH_CTRL : LUT_DATA <= 16'h0A06; //R5 DEEMP = 11 (48 KHz)
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//POWER_ON : LUT_DATA <= 16'h0C00; //R6 all powered ON
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POWER_ON : LUT_DATA <= 16'h0C20; //R6 internal oscilator MCLK powered down
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//SET_FORMAT : LUT_DATA <= 16'h0E01; //R7 FORMAT=01,16 bit format left justified
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SET_FORMAT : LUT_DATA <= 16'h0E02; //R7 FORMAT=10,16 bit format I2S
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//SAMPLE_CTRL : LUT_DATA <= 16'h1009; //R8 48KHz,USB-mode
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SAMPLE_CTRL : LUT_DATA <= 16'h1008; //R8 48KHz,Normal mode, clkdiv2=0
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SET_ACTIVE : LUT_DATA <= 16'h1201; //R9 ACTIVE
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default : LUT_DATA <= 16'h0000;
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endcase
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end
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////////////////////////////////////////////////////////////////////
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endmodule
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‎sys/I2C_Controller.v

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module I2C_Controller (
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CLOCK,
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I2C_SCLK, //I2C CLOCK
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I2C_SDAT, //I2C DATA
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I2C_DATA, //DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
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GO, //GO transfor
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END, //END transfor
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ACK, //ACK
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RESET,
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//TEST
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SD_COUNTER,
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SDO
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);
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input CLOCK;
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input [23:0]I2C_DATA;
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input GO;
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input RESET;
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inout I2C_SDAT;
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output I2C_SCLK;
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output END;
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output ACK;
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//TEST
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output [5:0] SD_COUNTER;
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output SDO;
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reg SDO;
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reg SCLK;
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reg END;
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reg [23:0]SD;
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reg [5:0]SD_COUNTER;
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wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK : 1'd0 );
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wire I2C_SDAT=SDO ? 1'bz : 1'b0 ;
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reg ACK1,ACK2,ACK3;
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wire ACK=ACK1 | ACK2 |ACK3;
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//--I2C COUNTER
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always @(negedge RESET or posedge CLOCK ) begin
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if (!RESET) SD_COUNTER=6'b111111;
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else begin
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if (GO==0)
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SD_COUNTER=0;
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else
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if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER + 6'd1;
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end
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end
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//----
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always @(negedge RESET or posedge CLOCK ) begin
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if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end
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else
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case (SD_COUNTER)
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6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
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//start
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6'd1 : begin SD=I2C_DATA;SDO=0;end
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6'd2 : SCLK=0;
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//SLAVE ADDR
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6'd3 : SDO=SD[23];
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6'd4 : SDO=SD[22];
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6'd5 : SDO=SD[21];
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6'd6 : SDO=SD[20];
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6'd7 : SDO=SD[19];
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6'd8 : SDO=SD[18];
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6'd9 : SDO=SD[17];
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6'd10 : SDO=SD[16];
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6'd11 : SDO=1'b1;//ACK
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//SUB ADDR
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6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
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6'd13 : SDO=SD[14];
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6'd14 : SDO=SD[13];
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6'd15 : SDO=SD[12];
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6'd16 : SDO=SD[11];
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6'd17 : SDO=SD[10];
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6'd18 : SDO=SD[9];
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6'd19 : SDO=SD[8];
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6'd20 : SDO=1'b1;//ACK
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//DATA
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6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
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6'd22 : SDO=SD[6];
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6'd23 : SDO=SD[5];
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6'd24 : SDO=SD[4];
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6'd25 : SDO=SD[3];
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6'd26 : SDO=SD[2];
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6'd27 : SDO=SD[1];
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6'd28 : SDO=SD[0];
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6'd29 : SDO=1'b1;//ACK
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//stop
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6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
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6'd31 : SCLK=1'b1;
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6'd32 : begin SDO=1'b1; END=1; end
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endcase
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end
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endmodule
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