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‎Cores/Deca_Interface_Test_Template/Deca_Interface_Test.qpf

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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# Date created = 21:43:57 January 08, 2021
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "17.1"
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DATE = "21:43:57 January 08, 2021"
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# Revisions
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PROJECT_REVISION = "Deca_Interface_Test"

‎Cores/Deca_Interface_Test_Template/Deca_Interface_Test.qsf

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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# Date created = 21:43:57 January 08, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# gpio_sega_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSXFC6D6F31C6
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set_global_assignment -name TOP_LEVEL_ENTITY Deca_Interface_Test
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:43:57 JANUARY 08, 2021"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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#============================================================
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set_location_assignment PIN_K14 -to CLK_50
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set_location_assignment PIN_AE9 -to RESET
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set_location_assignment PIN_AF10 -to BOARD_LEDS[0]
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set_location_assignment PIN_AD10 -to BOARD_LEDS[1]
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set_location_assignment PIN_AE11 -to BOARD_LEDS[2]
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set_location_assignment PIN_AD7 -to BOARD_LEDS[3]
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# assign GPIO0_D[4] = PS2_KEYBOARD_CLK; //HSMC_CLKIN_n1 PIN_AB27
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set_location_assignment PIN_AB27 -to PS2_KEYBOARD_CLK
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# assign GPIO0_D[5] = PS2_KEYBOARD_DAT; //HSMC_RX _n[7] PIN_F8
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set_location_assignment PIN_F8 -to PS2_KEYBOARD_DAT
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# assign GPIO0_D[6] = PS2_MOUSE_CLK; //HSMC_CLKIN_p1 PIN_AA26
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set_location_assignment PIN_AA26 -to PS2_MOUSE_CLK
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# assign GPIO0_D[7] = PS2_MOUSE_DAT; //HSMC_RX _p[7] PIN_F9
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set_location_assignment PIN_F9 -to PS2_MOUSE_DAT
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# assign GPIO0_D[8] = UART_RXD; //HSMC_TX _n[7] PIN_B3
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set_location_assignment PIN_B3 -to UART_RXD
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# assign GPIO0_D[9] = UART_TXD; //HSMC_RX _n[6] PIN_G8
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set_location_assignment PIN_G8 -to UART_TXD
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# assign GPIO0_D[10] = JOY1_B2_P9; //HSMC_TX _p[7] PIN_C3
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set_location_assignment PIN_C3 -to JOY1_B2_P9
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# assign GPIO0_D[11] = JOY1_B1_P6; //HSMC_RX _p[6] PIN_H8
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set_location_assignment PIN_H8 -to JOY1_B1_P6
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# assign GPIO0_D[12] = JOY1_UP; //HSMC_TX _n[6] PIN_D4
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set_location_assignment PIN_D4 -to JOY1_UP
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# assign GPIO0_D[13] = JOY1_DOWN; //HSMC_RX _n[5] PIN_H7
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set_location_assignment PIN_H7 -to JOY1_DOWN
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# POWER PINS
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# assign GPIO0_D[16] = JOY1_LEFT; //HSMC_TX _p[6] PIN_E4
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set_location_assignment PIN_E4 -to JOY1_LEFT
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# assign GPIO0_D[17] = JOY1_RIGHT; //HSMC_RX _p[5] PIN_J7
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set_location_assignment PIN_J7 -to JOY1_RIGHT
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# assign GPIO0_D[18] = JOYX_SEL_O; //HSMC_TX _n[5] PIN_E2
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set_location_assignment PIN_E2 -to JOYX_SEL_O
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# assign GPIO0_D[19] = PMOD1[0]; //HSMC_RX _n[4] PIN_K8
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set_location_assignment PIN_K8 -to PMOD1[0]
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# assign GPIO0_D[20] = PMOD1[1]; //HSMC_TX _p[5] PIN_E3
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set_location_assignment PIN_E3 -to PMOD1[1]
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# assign GPIO0_D[21] = PMOD1[2]; //HSMC_RX _p[4] PIN_K7
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set_location_assignment PIN_K7 -to PMOD1[2]
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# assign GPIO0_D[22] = PMOD1[3]; //HSMC_CLKOUT_n1 PIN_E6
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set_location_assignment PIN_E6 -to PMOD1[3]
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# assign GPIO0_D[23] = PMOD1[4]; //HSMC_RX _n[3] PIN_J9
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set_location_assignment PIN_J9 -to PMOD1[4]
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# assign GPIO0_D[24] = PMOD1[5]; //HSMC_CLKOUT_p1 PIN_E7
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set_location_assignment PIN_E7 -to PMOD1[5]
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# assign GPIO0_D[25] = PMOD1[6]; //HSMC_RX _p[3] PIN_J10
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set_location_assignment PIN_J10 -to PMOD1[6]
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# assign GPIO0_D[26] = PMOD1[7]; //HSMC_TX _n[4] PIN_C4
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set_location_assignment PIN_C4 -to PMOD1[7]
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#============================================================
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_LEDS[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_LEDS[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_LEDS[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BOARD_LEDS[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOY1_B1_P6
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOY1_B2_P9
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOY1_DOWN
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOY1_LEFT
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOY1_RIGHT
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOY1_UP
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to JOYX_SEL_O
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PMOD1[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KEYBOARD_CLK
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KEYBOARD_DAT
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MOUSE_CLK
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MOUSE_DAT
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
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#============================================================
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set_global_assignment -name SDC_FILE Deca_Interface_Test.sdc
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set_global_assignment -name VERILOG_FILE Deca_Interface_Test.v
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#============================================================
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎Cores/Deca_Interface_Test_Template/Deca_Interface_Test.sdc

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create_clock -name "CLK_50" -period 20.000ns [get_ports {CLK_50}]
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derive_pll_clocks
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derive_clock_uncertainty

‎Cores/Deca_Interface_Test_Template/Deca_Interface_Test.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Module Name: Deca_Interface_Test
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// Create Date: 05/05/2022
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// Description:
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//
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Deca_Interface_Test(
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input CLK_50,
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input RESET, // KEY0
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// LED output
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output [3:0] BOARD_LEDS, // LED0..3
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// PS2
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input PS2_KEYBOARD_CLK,
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input PS2_KEYBOARD_DAT,
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input PS2_MOUSE_CLK,
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input PS2_MOUSE_DAT,
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// UART
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input UART_RXD,
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input UART_TXD, //output
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// JOYSTICK
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input JOY1_B2_P9,
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input JOY1_B1_P6,
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input JOY1_UP,
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input JOY1_DOWN,
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input JOY1_LEFT,
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input JOY1_RIGHT,
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input JOYX_SEL_O, //output
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//Pmod MicroSD
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inout [7:0] PMOD1
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);
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assign BOARD_LEDS[0] = PS2_KEYBOARD_CLK;
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assign BOARD_LEDS[1] = PS2_KEYBOARD_DAT;
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assign BOARD_LEDS[2] = PS2_MOUSE_CLK;
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assign BOARD_LEDS[3] = PS2_MOUSE_DAT;
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// assign BOARD_LEDS[0] = UART_RXD;
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// assign BOARD_LEDS[1] = UART_TXD;
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// assign BOARD_LEDS[2] = JOY1_B2_P9;
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// assign BOARD_LEDS[3] = JOY1_B1_P6;
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// assign BOARD_LEDS[0] = JOY1_UP;
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// assign BOARD_LEDS[1] = JOY1_DOWN;
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// assign BOARD_LEDS[2] = JOY1_LEFT;
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// assign BOARD_LEDS[3] = JOY1_RIGHT;
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// assign BOARD_LEDS[0] = JOYX_SEL_O;
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// assign BOARD_LEDS[1] = PMOD1[0];
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// assign BOARD_LEDS[2] = PMOD1[1];
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// assign BOARD_LEDS[3] = PMOD1[2];
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// assign BOARD_LEDS[0] = PMOD1[3];
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// assign BOARD_LEDS[1] = PMOD1[4];
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// assign BOARD_LEDS[2] = PMOD1[5];
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// assign BOARD_LEDS[3] = PMOD1[6];
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// assign BOARD_LEDS[0] = PMOD1[7];
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// assign BOARD_LEDS[0] = PS2_KEYBOARD_CLK || UART_RXD || JOY1_UP || JOYX_SEL_O || PMOD1[3] || PMOD1[7] || ~RESET;
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// assign BOARD_LEDS[1] = PS2_KEYBOARD_DAT || UART_TXD || JOY1_DOWN || PMOD1[0] || PMOD1[4] || ~RESET;
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// assign BOARD_LEDS[2] = PS2_MOUSE_CLK || JOY1_B2_P9 || JOY1_LEFT || PMOD1[1] || PMOD1[5] || ~RESET;
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// assign BOARD_LEDS[3] = PS2_MOUSE_DAT || JOY1_B1_P6 || JOY1_RIGHT || PMOD1[2] || PMOD1[6] || ~RESET;
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endmodule

‎Cores/MemTest/README.md

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# MemTest - Utility to test SDRAM daughter board - SOCKIT PORT
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Memtest by Somhic ported from Neptuno https://github.com/neptuno-fpga/MemTest_Mister, which was ported from Multicore 2, which was already ported from original Memory tester for MiSTer (https://github.com/MiSTer-devel/MemTest_MiSTer).
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**Features:**
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* VGA video output
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**Additional hardware**:
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- SDRAM module for testing.
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- PS/2 Keyboard connected to GPIO
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**STATUS**:
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- 22/04/22 Sockit Port. **Only does the test at fixed 120 MHz frecuency**
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- Does not work with 128 MB memory modules.
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**Compiling:**
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* Load project in /synth/sockit/memtest_sockit.qpf
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* sof file already included in /synth/sockit/output_files/
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**Pinout connections:**
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See qsf file
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## Memtest screen:
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![MemTest screen](memtest.png)
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1. Auto mode indicator (animated)
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2. Test time passed in minutes
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3. Current memory module frequency in MHz
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4. Memory module size:
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* 0 - no memory board
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* 1 - 32 MB
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* 2 - 64 MB
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* 3 - 128 MB
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5. Number of of passed test cycles (each cycle is 32 MB)
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6. Number of failed tests.
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## Controls (keyboard)
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* Up - increase frequency ~~(KEY0 BUTTON)~~
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* Down - decrease frequency ~~(KEY1 BUTTON)~~
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* ESC - reset the test
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* A - auto mode, detecting the maximum frequency for module being tested. Test starts from maximum frequency. With every error frequency will be decreased. [~~SW1 SWITCH~~]
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Test is passed if amount of errors is 0. For quick test let it run for 10 minutes in auto mode. If you want to be sure, let it run for 1-2 hours.
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Board should pass at least 130 MHz clock test. Any higher clock will assure the higher quality of the board.

‎Cores/MemTest/memtest.png

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‎Cores/MemTest/src/README.md

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# MemTest - Utility to test SDRAM daughter board.
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## Memtest screen:
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![MemTest screen](img/memtest.png)
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1. Auto mode indicator (animated),
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2. Test time passed in minutes,
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3. Current memory module frequency in MHz,
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4. Memory module size:
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* 0 - no memory board detected
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* 1 - 32 MB
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* 2 - 64 MB
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* 3 - 128 MB
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5. Number of of passed test cycles (each cycle is 32 MB),
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6. Number of failed tests.
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## Controls (keyboard)
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* Up - increase frequency
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* Down - decrease frequency
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* Enter - reset the test
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* A - auto mode, detecting the maximum frequency for module being tested. Test starts from maximum frequency.
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With every error frequency will be decreased.
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Test is passed if amount of errors is 0. For quick test let it run for 10 minutes in auto mode. If you want to be sure, let it run for 1-2 hours.
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Board should pass at least 130 MHz clock test. Any higher clock will assure the higher quality of the board.

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