Skip to content

Latest commit

 

History

History
29 lines (20 loc) · 529 Bytes

_Info.md

File metadata and controls

29 lines (20 loc) · 529 Bytes

RTL Modules

The inidividual RTL modules developed for this project are as follows and they also equip with corresponding testbenches.

  1. SM Core
    1. Scheduler
      1. Control Unit
      2. Program Counter
      3. PStack
    2. SP Core
      1. ALU
      2. Multiplexer
      3. Register
  2. Data Memory
  3. Instruction Memory
  4. Memory Controller

Scheduler

Scheduler

SPCore Bank

n_spcore

SPCore

SPCore