drivers: caam: Add register map changes for Era 10

Era 10 changes the register map.

The updates that affect the drivers:
-new version registers are added

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

Author: Ruchika Gupta

core/drivers/crypto/caam/hal/common/hal_ctrl.c

@@ -10,30 +10,59 @@
 #include <registers/ctrl_regs.h>
 #include <registers/version_regs.h>
 
+uint8_t caam_hal_ctrl_era(vaddr_t baseaddr)
+{
+	/* Read the number of instance */
+	uint32_t val = io_caam_read32(baseaddr + CCBVID);
+
+	return GET_CCBVID_CAAM_ERA(val);
+}
+
 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr)
 {
 	uint32_t val = 0;
+	uint8_t jrnum = 0;
 
-	val = io_caam_read32(baseaddr + CHANUM_MS);
+	if (caam_hal_ctrl_era(baseaddr) < 10) {
+		val = io_caam_read32(baseaddr + CHANUM_MS);
+		jrnum = GET_CHANUM_MS_JRNUM(val);
+	} else {
+		val = io_caam_read32(baseaddr + JR_VERSION);
+		jrnum = GET_JR_VERSION_JRNUM(val);
+	}
 
-	return GET_CHANUM_MS_JRNUM(val);
+	return jrnum;
 }
 
 uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr)
 {
 	uint32_t val = 0;
 
-	/* Read the number of instance */
-	val = io_caam_read32(baseaddr + CHANUM_LS);
+	if (caam_hal_ctrl_era(baseaddr) < 10) {
+		/* Read the number of instance */
+		val = io_caam_read32(baseaddr + CHANUM_LS);
+
+		if (GET_CHANUM_LS_MDNUM(val)) {
+			/* Hashing is supported */
+			val = io_caam_read32(baseaddr + CHAVID_LS);
+			val &= BM_CHAVID_LS_MDVID;
+			if (val == CHAVID_LS_MDVID_LP256)
+				return TEE_MAIN_ALGO_SHA256;
+
+			return TEE_MAIN_ALGO_SHA512;
+		}
+	} else {
+		/* Read the number of instance */
+		val = io_caam_read32(baseaddr + MDHA_VERSION);
 
-	if (GET_CHANUM_LS_MDNUM(val)) {
-		/* Hashing is supported */
-		val = io_caam_read32(baseaddr + CHAVID_LS);
-		val &= BM_CHAVID_LS_MDVID;
-		if (val == CHAVID_LS_MDVID_LP256)
-			return TEE_MAIN_ALGO_SHA256;
+		if (GET_MDHA_VERSION_MDNUM(val)) {
+			/* Hashing is supported */
+			val &= BM_MDHA_VERSION_MDVID;
+			if (val == MDHA_VERSION_MDVID_LP256)
+				return TEE_MAIN_ALGO_SHA256;
 
-		return TEE_MAIN_ALGO_SHA512;
+			return TEE_MAIN_ALGO_SHA512;
+		}
 	}
 
 	return UINT8_MAX;
@@ -42,18 +71,15 @@ uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr)
 uint8_t caam_hal_ctrl_pknum(vaddr_t baseaddr)
 {
 	uint32_t val = 0;
+	uint8_t pknum = 0;
 
-	val = io_caam_read32(baseaddr + CHANUM_LS);
-
-	return GET_CHANUM_LS_PKNUM(val);
-}
-
-uint8_t caam_hal_ctrl_era(vaddr_t baseaddr)
-{
-	uint32_t val = 0;
-
-	/* Read the number of instance */
-	val = io_caam_read32(baseaddr + CCBVID);
+	if (caam_hal_ctrl_era(baseaddr) < 10) {
+		val = io_caam_read32(baseaddr + CHANUM_LS);
+		pknum = GET_CHANUM_LS_PKNUM(val);
+	} else {
+		val = io_caam_read32(baseaddr + PKHA_VERSION);
+		pknum = GET_PKHA_VERSION_PKNUM(val);
+	}
 
-	return GET_CCBVID_CAAM_ERA(val);
+	return pknum;
 }

core/drivers/crypto/caam/hal/common/hal_rng.c

@@ -5,6 +5,7 @@
  * Brief   CAAM Random Number Generator Hardware Abstration Layer.
  *         Implementation of primitives to access HW.
  */
+#include <caam_hal_ctrl.h>
 #include <caam_hal_rng.h>
 #include <caam_io.h>
 #include <caam_status.h>
@@ -13,15 +14,23 @@
 
 bool caam_hal_rng_instantiated(vaddr_t baseaddr)
 {
-	uint32_t chavid_ls = 0;
+	uint32_t vid = 0;
 	uint32_t nb_sh = 0;
 	uint32_t status = 0;
 
-	chavid_ls = io_caam_read32(baseaddr + CHAVID_LS);
 
 	/* RNG version < 4 and RNG state handle is already instantiated */
-	if (GET_CHAVID_LS_RNGVID(chavid_ls) < 4)
-		return true;
+	if (caam_hal_ctrl_era(baseaddr) < 10) {
+		vid = io_caam_read32(baseaddr + CHAVID_LS);
+
+		if (GET_CHAVID_LS_RNGVID(vid) < 4)
+			return true;
+	} else {
+		vid = io_caam_read32(baseaddr + RNG_VERSION);
+
+		if (GET_RNG_VERSION_VID(vid) < 4)
+			return true;
+	}
 
 	/* Get the Number of State Handles */
 	nb_sh = caam_hal_rng_get_nb_sh(baseaddr);

core/drivers/crypto/caam/hal/common/registers/version_regs.h

@@ -43,5 +43,28 @@
 #define BM_CHANUM_LS_MDNUM              SHIFT_U32(0xF, 12)
 #define GET_CHANUM_LS_MDNUM(val)	(((val) & BM_CHANUM_LS_MDNUM) >> 12)
 
+/* PKHA Version for Era > 10 */
+#define PKHA_VERSION			0x0E8C
+#define BM_PKHA_VERSION_PKNUM		0xFF
+#define GET_PKHA_VERSION_PKNUM(val)	(((val) & BM_PKHA_VERSION_PKNUM))
+
+/* MDHA Version for Era > 10 */
+#define MDHA_VERSION			0xE94
+#define BM_MDHA_VERSION_MDNUM		0xFF
+#define GET_MDHA_VERSION_MDNUM(val)	(((val) & BM_MDHA_VERSION_MDNUM))
+#define BM_MDHA_VERSION_MDVID		SHIFT_U32(0xFF, 24)
+
+#define MDHA_VERSION_MDVID_LP256	SHIFT_U32(0, 24)
+
+/* RNG Version for Era > 10 */
+#define RNG_VERSION			0x0EF8
+#define BM_RNG_VERSION_VID	        SHIFT_U32(0xFF, 24)
+#define GET_RNG_VERSION_VID(val)	(((val) & BM_RNG_VERSION_VID))
+
+/* JR Version for Era > 10 */
+#define JR_VERSION			0x0EF8
+#define BM_JR_VERSION_JRNUM		0xFF
+#define GET_JR_VERSION_JRNUM(val)	(((val) & BM_JR_VERSION_JRNUM))
+
 #endif /* __VERSION_REGS_H__ */