Initial commit

Author: ritik99

AddRoundKey.v

@@ -0,0 +1,30 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:08:49 10/22/2017 
+// Design Name: 
+// Module Name:    AddRoundKey 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module addroundkey(input [127 : 0] data, output [127:0] out, input [127:0] key, input clk);
+
+generate
+genvar i;
+for(i = 0; i < 128; i = i + 1)
+begin: h
+assign out[i] = data[i]^key[i];
+end
+endgenerate
+endmodule

MixColumns.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:56:33 10/22/2017 
+// Design Name: 
+// Module Name:    MixColumns 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module MixColumns(input [127 : 0] data, output reg [127:0] mixcolumns, input clk);
+    //wire reg [31 : 0] w0, w1, w2, w3;
+    //wire reg [31 : 0] ws0, ws1, ws2, ws3;
+      assign w0 = data[127 : 096];
+      assign w1 = data[095 : 064];
+      assign w2 = data[063 : 032];
+      assign w3 = data[031 : 000];
+
+      assign ws0 = mixw(w0);
+      assign ws1 = mixw(w1);
+      assign ws2 = mixw(w2);
+      assign ws3 = mixw(w3);
+		
+	 function [31 : 0] mixw(input [31 : 0] w);
+    reg [7 : 0] b0, b1, b2, b3;
+    reg [7 : 0] mb0, mb1, mb2, mb3;
+    begin
+      b0 = w[31 : 24];
+      b1 = w[23 : 16];
+      b2 = w[15 : 08];
+      b3 = w[07 : 00];
+
+      mb0 = gm2(b0) ^ gm3(b1) ^ b2      ^ b3;
+      mb1 = b0      ^ gm2(b1) ^ gm3(b2) ^ b3;
+      mb2 = b0      ^ b1      ^ gm2(b2) ^ gm3(b3);
+      mb3 = gm3(b0) ^ b1      ^ b2      ^ gm2(b3);
+
+      mixw = {mb0, mb1, mb2, mb3};
+    end
+  endfunction
+  
+  function [7 : 0] gm2(input [7 : 0] op);
+    begin
+      gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
+    end
+  endfunction
+
+  function [7 : 0] gm3(input [7 : 0] op);
+    begin
+      gm3 = gm2(op) ^ op;
+    end
+  endfunction
+
+	always@(posedge clk)
+  assign mixcolumns = {ws0, ws1, ws2, ws3};
+
+	 
+
+endmodule

ShiftRows.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:54:04 10/22/2017 
+// Design Name: 
+// Module Name:    ShiftRows 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ShiftRows(data,out, clk);
+input [127:0] data;
+input clk;
+output reg [127:0] out;
+reg [31:0] t0, t1, t2, t3;
+reg [31:0] ws0, ws1, ws2, ws3;
+
+always@(posedge clk)
+begin
+t0 = data[127:096];
+t1 = data[095 : 064];
+t2 = data[063 : 032];
+t3 = data[031 : 000];
+
+ws0 = {t0[31 : 24], t1[23 : 16], t2[15 : 08], t3[07 : 00]};
+ws1 = {t1[31 : 24], t2[23 : 16], t3[15 : 08], t0[07 : 00]};
+ws2 = {t2[31 : 24], t3[23 : 16], t0[15 : 08], t1[07 : 00]};
+ws3 = {t3[31 : 24], t0[23 : 16], t1[15 : 08], t2[07 : 00]};
+
+out = {ws0, ws1, ws2, ws3};
+end
+endmodule