rcar: scif: Implement SCIF driver

Currently, this flow is IMSG --> console_putc(). If we want to use SCIF,
please enable CFG_SCIF=y.

But, logging function will be turned off if CFG_SCIF=y.

Signed-off-by: Anh Vo <anh.vo.vx@renesas.com>

Author: AnhVoRVC

core/arch/arm/plat-rcar/conf.mk

@@ -106,9 +106,6 @@ endif
 core-platform-cflags += -DPLATFORM_RCAR
 core-platform-cflags += -DMMU_DIRECT_MAPPING
 
-# Not covered by compile - /core/arch/arm/kernel/trace_ext.c
-WITH_TRACE_EXT := n
-
 # Compiler switch - Debug log(Linux terminal log)
 RCAR_DEBUG_LOG ?= 0
 ifneq ($(RCAR_DEBUG_LOG),0)

core/arch/arm/plat-rcar/main.c

@@ -251,7 +251,10 @@ register_ddr(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE);
 #endif /* !CFG_CORE_RESERVED_SHM */
 // #endif
 
-// static struct scif_uart_data console_data __nex_bss;  //use rcar_logging feature instead
+#ifdef CFG_SCIF
+static struct scif_uart_data console_data __nex_bss;
+#endif
+
 static void main_hook_gic_add(struct itr_chip *chip, size_t it, uint32_t type, uint32_t prio)
 {
 	uint32_t exceptions;
@@ -274,9 +277,12 @@ uint32_t rcar_prr_value __nex_bss;
 
 void plat_console_init(void)
 {
-	/* No Operation */
-	// scif_uart_init(&console_data, CONSOLE_UART_BASE);
-	// register_serial_console(&console_data.chip);
+#ifdef CFG_SCIF
+	scif_uart_init(&console_data, SCIF2_BASE);
+	/* Register struct chip (handler func) to framework (console.c)*/
+	register_serial_console(&console_data.chip);
+	IMSG("Init SCIF driver before mmu enable");
+#endif
 }
 
 #ifdef CFG_RCAR_ROMAPI
@@ -307,7 +313,9 @@ void boot_primary_init_intc(void)
 	gic_data.chip.ops = (const struct itr_ops *)&main_itr_ops;
 
 	// Initialize logging feature
+#ifndef CFG_SCIF
 	log_buf_init();
+#endif
 }
 
 void boot_secondary_init_intc(void)

core/arch/arm/plat-rcar/platform_config.h

@@ -95,6 +95,7 @@
 #define ROMAPI_BASE		(0xEB100000U)	/* MaskROM API address	*/
 #define RPC_BASE		(0xEE200000U)	/* RPC address		*/
 // #define PRR_BASE		(0xFFF00000U)	/* Product Register address */
+#define SCIF2_BASE 		(0xE6E88000U)	/* SCIF2 base address */
 #define RPC_ADDR_MAP_BASE	(0x08000000U)	/* RPC Internal address	*/
 #define RPC_ADDR_MAP_SIZE	(0x04000000U)	/* RPC Address Map size */
 

core/arch/arm/plat-rcar/sub.mk

@@ -15,8 +15,12 @@ srcs-y += rcar_maskrom.c
 srcs-y += rcar_suspend_to_ram.c
 srcs-y += rcar_mutex.c
 
-# Copy the base file - /core/arch/arm/kernel/
+ifneq ($(CFG_SCIF),y)
 srcs-y += trace_ext.c
+WITH_TRACE_EXT := n
+else
+WITH_TRACE_EXT := y
+endif
 
 subdirs-y += drivers
 subdirs-y += tee

core/drivers/scif.c

@@ -40,6 +40,7 @@
 #define SCSCR_TE		BIT(5)
 #define SCFSR_TDFE		BIT(5)
 #define SCFSR_TEND		BIT(6)
+#define TRANS_END_CHECK         (uint16_t)(SCFSR_TEND | SCFSR_TDFE)
 
 #define SCFDR_T_SHIFT		8
 
@@ -57,18 +58,22 @@ static void scif_uart_flush(struct serial_chip *chip)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	while (!(io_read16(base + SCIF_SCFSR) & SCFSR_TEND))
+	while ((TRANS_END_CHECK & io_read16(base + SCIF_SCFSR)) != TRANS_END_CHECK)
+	{
 		;
+	}
 }
 
 static void scif_uart_putc(struct serial_chip *chip, int ch)
 {
 	vaddr_t base = chip_to_base(chip);
 
-	/* Wait until there is space in the FIFO */
-	while ((io_read16(base + SCIF_SCFDR) >> SCFDR_T_SHIFT) >=
-		SCIF_TX_FIFO_SIZE)
+	/* Check that transfer is completed */
+	while ((TRANS_END_CHECK & io_read16(base + SCIF_SCFSR)) != TRANS_END_CHECK)
+	{
 		;
+	}
+
 	io_write8(base + SCIF_SCFTDR, ch);
 	io_clrbits16(base + SCIF_SCFSR, SCFSR_TEND | SCFSR_TDFE);
 }