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Add support for 2712D0 variant #5847

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merged 8 commits into from
Jan 15, 2024
Merged

Add support for 2712D0 variant #5847

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8be0890
ARM: dts: bcm2712: Prune the non-D0 hardware
pelwell Nov 16, 2023
fc55485
ARM: dts: Add BCM2712 D0 dts
pelwell Nov 15, 2023
b38c066
ARM: dts: overlays: Add a bcm2712d0 overlay
pelwell Nov 16, 2023
1c8424e
pinctrl: bcm2712: Fix for sparse GPIOs
pelwell Nov 15, 2023
937d1d6
pinctrl: bcm2712: Fix for the first valid GPIO
pelwell Nov 30, 2023
6596684
vc4/hvs: Add support for D0 register changes
popcornmix Nov 14, 2023
554337c
vc4/hvs: Updates to support D0 alpha and csc changes
popcornmix Jan 12, 2024
1b67356
vc4/hdmi: Update MAI_THR for D0
popcornmix Nov 16, 2023
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2 changes: 0 additions & 2 deletions arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,6 @@
#define spi6 _spi6
#define uart0 _uart0
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This commit could go before the addition of the bcm2712d0 variant, to avoid modifying it.

#define uart2 _uart2
#define uart3 _uart3
#define uart4 _uart4
#define uart5 _uart5

#include "bcm2712.dtsi"
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66 changes: 0 additions & 66 deletions arch/arm/boot/dts/broadcom/bcm2712.dtsi
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Expand Up @@ -197,28 +197,6 @@
status = "disabled";
};

uart3: serial@7d001600 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x7d001600 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart>,
<&clk_vpu>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
status = "disabled";
};

uart4: serial@7d001800 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x7d001800 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart>,
<&clk_vpu>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
status = "disabled";
};

uart5: serial@7d001a00 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x7d001a00 0x200>;
Expand Down Expand Up @@ -543,17 +521,6 @@
status = "disabled";
};

uartc: serial@7d50e000 {
compatible = "brcm,bcm7271-uart";
reg = <0x7d50e000 0x20>;
reg-names = "uart";
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
skip-init;
status = "disabled";
};

aon_intr: interrupt-controller@7d510600 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7d510600 0x30>;
Expand Down Expand Up @@ -1103,30 +1070,6 @@
brcm,msi-pci-addr = <0xff 0xffffe000>;
};

genet: ethernet@1300000 {
compatible = "brcm,bcm2711-genet-v5";
reg = <0x10 0x01300000 0x0 0x20010>;
#address-cells = <0x1>;
#size-cells = <0x0>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
phy-mode = "rgmii";
fixed-link = <0x0 0x1 0x3e8 0x0 0x0>;
phy-speed = <0x3e8>;
phy-id = <0x101>;
phy-type = <0x6>;
local-mac-address = [ 00 10 18 d8 45 de ];
device_type = "network";

genet_mdio: mdio@e14 {
compatible = "brcm,genet-mdio-v5";
reg = <0xe14 0x8>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
};

syscon_piarbctl: syscon@400018 {
compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd";
reg = <0x10 0x00400018 0x0 0x18>;
Expand Down Expand Up @@ -1189,15 +1132,6 @@
status = "disabled";
};

sdio0: mmc@1108000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x10 0x01108000 0x0 0x100>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_emmc2>;
mmc-ddr-3_3v;
status = "disabled";
};

bcm_reset: reset-controller@1504318 {
compatible = "brcm,brcmstb-reset";
reg = <0x10 0x01504318 0x0 0x30>;
Expand Down
107 changes: 107 additions & 0 deletions arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
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@@ -0,0 +1,107 @@
// SPDX-License-Identifier: GPL-2.0
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This whole commit could be dropped now that we have the bcm2712d0 overlay, unless we're catering for upstream preferences.

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Yeah, I was thinking it will be wanted in future for upstream.

#include "bcm2712-rpi-5-b.dts"

&gio {
brcm,gpio-bank-widths = <32 4>;

gpio-line-names =
"", // GPIO_000
"2712_BOOT_CS_N", // GPIO_001
"2712_BOOT_MISO", // GPIO_002
"2712_BOOT_MOSI", // GPIO_003
"2712_BOOT_SCLK", // GPIO_004
"", // GPIO_005
"", // GPIO_006
"", // GPIO_007
"", // GPIO_008
"", // GPIO_009
"", // GPIO_010
"", // GPIO_011
"", // GPIO_012
"", // GPIO_013
"PCIE_SDA", // GPIO_014
"PCIE_SCL", // GPIO_015
"", // GPIO_016
"", // GPIO_017
"-", // GPIO_018
"-", // GPIO_019
"PWR_GPIO", // GPIO_020
"2712_G21_FS", // GPIO_021
"-", // GPIO_022
"-", // GPIO_023
"BT_RTS", // GPIO_024
"BT_CTS", // GPIO_025
"BT_TXD", // GPIO_026
"BT_RXD", // GPIO_027
"WL_ON", // GPIO_028
"BT_ON", // GPIO_029
"WIFI_SDIO_CLK", // GPIO_030
"WIFI_SDIO_CMD", // GPIO_031
"WIFI_SDIO_D0", // GPIO_032
"WIFI_SDIO_D1", // GPIO_033
"WIFI_SDIO_D2", // GPIO_034
"WIFI_SDIO_D3"; // GPIO_035
};

&gio_aon {
brcm,gpio-bank-widths = <15 6>;

gpio-line-names =
"RP1_SDA", // AON_GPIO_00
"RP1_SCL", // AON_GPIO_01
"RP1_RUN", // AON_GPIO_02
"SD_IOVDD_SEL", // AON_GPIO_03
"SD_PWR_ON", // AON_GPIO_04
"SD_CDET_N", // AON_GPIO_05
"SD_FLG_N", // AON_GPIO_06
"", // AON_GPIO_07
"2712_WAKE", // AON_GPIO_08
"2712_STAT_LED", // AON_GPIO_09
"", // AON_GPIO_10
"", // AON_GPIO_11
"PMIC_INT", // AON_GPIO_12
"UART_TX_FS", // AON_GPIO_13
"UART_RX_FS", // AON_GPIO_14
"", // AON_GPIO_15
"", // AON_GPIO_16

// Pad bank0 out to 32 entries
"", "", "", "", "", "", "", "", "", "", "", "", "", "", "",

"HDMI0_SCL", // AON_SGPIO_00
"HDMI0_SDA", // AON_SGPIO_01
"HDMI1_SCL", // AON_SGPIO_02
"HDMI1_SDA", // AON_SGPIO_03
"PMIC_SCL", // AON_SGPIO_04
"PMIC_SDA"; // AON_SGPIO_05
};

&pinctrl {
compatible = "brcm,bcm2712d0-pinctrl";
reg = <0x7d504100 0x20>;
};

&pinctrl_aon {
compatible = "brcm,bcm2712d0-aon-pinctrl";
reg = <0x7d510700 0x1c>;
};

&vc4 {
compatible = "brcm,bcm2712d0-vc6";
};

&uart10 {
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
};

&spi10 {
dmas = <&dma40 3>, <&dma40 4>;
};

&hdmi0 {
dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
};

&hdmi1 {
dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
};
1 change: 1 addition & 0 deletions arch/arm/boot/dts/overlays/Makefile
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Expand Up @@ -34,6 +34,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
audiosense-pi.dtbo \
audremap.dtbo \
balena-fin.dtbo \
bcm2712d0.dtbo \
camera-mux-2port.dtbo \
camera-mux-4port.dtbo \
cap1106.dtbo \
Expand Down
6 changes: 6 additions & 0 deletions arch/arm/boot/dts/overlays/README
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Expand Up @@ -826,6 +826,12 @@ Load: dtoverlay=balena-fin
Params: <None>


Name: bcm2712d0
Info: Overlay encapsulating the BCM2712 C0->D0 differences
Load: dtoverlay=bcm2712d0
Params: <None>


Name: bmp085_i2c-sensor
Info: This overlay is now deprecated - see i2c-sensor
Load: <Deprecated>
Expand Down
75 changes: 75 additions & 0 deletions arch/arm/boot/dts/overlays/bcm2712d0-overlay.dts
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@@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
compatible = "brcm,bcm2712";

fragment@0 {
target = <&gio>;
__overlay__ {
brcm,gpio-bank-widths = <32 4>;
};
};

fragment@1 {
target = <&gio_aon>;
__overlay__ {
brcm,gpio-bank-widths = <15 6>;
};
};

fragment@2 {
target = <&pinctrl>;
__overlay__ {
compatible = "brcm,bcm2712d0-pinctrl";
reg = <0x7d504100 0x20>;
};
};

fragment@3 {
target = <&pinctrl_aon>;
__overlay__ {
compatible = "brcm,bcm2712d0-aon-pinctrl";
reg = <0x7d510700 0x1c>;
};
};

fragment@4 {
target = <&vc4>;
__overlay__ {
compatible = "brcm,bcm2712d0-vc6";
};
};

fragment@5 {
target = <&uart10>;
__overlay__ {
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
};
};

fragment@6 {
target = <&spi10>;
__overlay__ {
dmas = <&dma40 3>, <&dma40 4>;
};
};

fragment@7 {
target = <&hdmi0>;
__overlay__ {
dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
};
};

fragment@8 {
target = <&hdmi1>;
__overlay__ {
dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
};
};
};
1 change: 1 addition & 0 deletions arch/arm64/boot/dts/broadcom/Makefile
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Expand Up @@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4s.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-5-b.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2712d0-rpi-5-b.dtb

subdir-y += bcmbca
subdir-y += northstar2
Expand Down
2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
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@@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0
#include "../../../../arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts"
8 changes: 7 additions & 1 deletion drivers/gpu/drm/vc4/vc4_drv.c
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Expand Up @@ -322,9 +322,13 @@ static int vc4_drm_bind(struct device *dev)
struct device_node *node;
struct drm_crtc *crtc;
enum vc4_gen gen;
bool step_d0 = false;
int ret = 0;

if (of_device_is_compatible(dev->of_node, "brcm,bcm2712-vc6"))
if (of_device_is_compatible(dev->of_node, "brcm,bcm2712d0-vc6")) {
gen = VC4_GEN_6;
step_d0 = true;
} else if (of_device_is_compatible(dev->of_node, "brcm,bcm2712-vc6"))
gen = VC4_GEN_6;
else if (of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5"))
gen = VC4_GEN_5;
Expand Down Expand Up @@ -355,6 +359,7 @@ static int vc4_drm_bind(struct device *dev)
if (IS_ERR(vc4))
return PTR_ERR(vc4);
vc4->gen = gen;
vc4->step_d0 = step_d0;
vc4->dev = dev;

drm = &vc4->base;
Expand Down Expand Up @@ -494,6 +499,7 @@ static void vc4_platform_drm_remove(struct platform_device *pdev)
static const struct of_device_id vc4_of_match[] = {
{ .compatible = "brcm,bcm2711-vc5", },
{ .compatible = "brcm,bcm2712-vc6", },
{ .compatible = "brcm,bcm2712d0-vc6", },
{ .compatible = "brcm,bcm2835-vc4", },
{ .compatible = "brcm,cygnus-vc4", },
{},
Expand Down
7 changes: 7 additions & 0 deletions drivers/gpu/drm/vc4/vc4_drv.h
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Expand Up @@ -92,6 +92,7 @@ struct vc4_dev {
struct device *dev;

enum vc4_gen gen;
bool step_d0;

unsigned int irq;

Expand Down Expand Up @@ -714,6 +715,12 @@ struct vc4_crtc_state {
writel(val, hvs->regs + (offset)); \
} while (0)

#define HVS_READ6(offset) \
HVS_READ(hvs->vc4->step_d0 ? SCALER6_ ## offset : SCALER6D0_ ## offset) \

#define HVS_WRITE6(offset, val) \
HVS_WRITE(hvs->vc4->step_d0 ? SCALER6_ ## offset : SCALER6D0_ ## offset, val) \

#define VC4_REG32(reg) { .name = #reg, .offset = reg }

struct vc4_exec_info {
Expand Down
8 changes: 7 additions & 1 deletion drivers/gpu/drm/vc4/vc4_hdmi.c
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Expand Up @@ -2597,7 +2597,13 @@ static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
VC4_HDMI_AUDIO_PACKET_CEA_MASK);

/* Set the MAI threshold */
if (vc4->gen >= VC4_GEN_5)
if (vc4->gen >= VC4_GEN_5 && vc4->step_d0)
HDMI_WRITE(HDMI_MAI_THR,
VC4_SET_FIELD(0x10, VC4_D0_HD_MAI_THR_PANICHIGH) |
VC4_SET_FIELD(0x10, VC4_D0_HD_MAI_THR_PANICLOW) |
VC4_SET_FIELD(0x1c, VC4_D0_HD_MAI_THR_DREQHIGH) |
VC4_SET_FIELD(0x1c, VC4_D0_HD_MAI_THR_DREQLOW));
else if (vc4->gen >= VC4_GEN_5)
HDMI_WRITE(HDMI_MAI_THR,
VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
Expand Down
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