Memory Verilog designs from Project F, including ROM, block ram, and SPRAM. You can freely build on these MIT licensed designs. Get an overview of the whole lib from the Verilog Library blog.
- rom_async.sv - asynchronous ROM in logic (no clock)
- rom_sync.sv - synchronous ROM in logic (uses clock)
- bram_sdp.sv - simple dual-port block RAM (one read port, one write port)
- ice40/spram.sv - iCE40 single port RAM (16-bit data width)
- ice40/spram_nibble.sv - iCE40 single port RAM (4-bit data width)
Find other modules in the Library.
The following blog posts document and make use of these memory modules:
- Practical ROM usage: Hardware Spites
- Practical BRAM usage: Lines & Triangles
- SPRAM on iCE40 FPGA - learn how to use SPRAM with Yosys and contrast it with Block RAM
- Initialize Memory in Verilog - use
$readmemhand$readmembto initialize the contents of ROM or RAM
These memory modules share similar parameters:
WIDTH- data width in bits (may be renamedDATAWin future)DEPTH- memory depth (number of elements)INIT_F- data file to load into memory at initializationADDRW- address width; by default this is calculated with$clog2(DEPTH)
These modules use a little SystemVerilog to make Verilog more pleasant, see the main Library README for details.