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| 1 | +# Copyright (c) 2020 Project CHIP Authors |
| 2 | +# |
| 3 | +# Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | +# you may not use this file except in compliance with the License. |
| 5 | +# You may obtain a copy of the License at |
| 6 | +# |
| 7 | +# http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | +# |
| 9 | +# Unless required by applicable law or agreed to in writing, software |
| 10 | +# distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | +# See the License for the specific language governing permissions and |
| 13 | +# limitations under the License. |
| 14 | + |
| 15 | +import("//build_overrides/build.gni") |
| 16 | + |
| 17 | +if (current_cpu == "riscv") { |
| 18 | + declare_args() { |
| 19 | + # Build file to import for RISCV defaults. |
| 20 | + riscv_platform_config = "" |
| 21 | + } |
| 22 | + |
| 23 | + # Allow platforms to override how RISCV architecture flags are chosen by |
| 24 | + # providing a file to import. |
| 25 | + if (riscv_platform_config != "") { |
| 26 | + _platform_defaults = { |
| 27 | + import(riscv_platform_config) |
| 28 | + } |
| 29 | + } |
| 30 | + |
| 31 | + _defaults = { |
| 32 | + riscv_arch = "" |
| 33 | + riscv_cpu = "" |
| 34 | + riscv_tune = "" |
| 35 | + riscv_fpu = "" |
| 36 | + riscv_float_abi = "" |
| 37 | + riscv_abi = "" |
| 38 | + |
| 39 | + # Update defaults with platform values, if any. |
| 40 | + if (riscv_platform_config != "") { |
| 41 | + forward_variables_from(_platform_defaults, "*") |
| 42 | + } |
| 43 | + } |
| 44 | + |
| 45 | + declare_args() { |
| 46 | + # RISCV architecture (value for -march flag). |
| 47 | + riscv_arch = _defaults.riscv_arch |
| 48 | + |
| 49 | + # RISCV CPU (value for -mcpu flag). |
| 50 | + riscv_cpu = _defaults.riscv_cpu |
| 51 | + |
| 52 | + # RISCV tuning (value for -mtune flag). |
| 53 | + riscv_tune = _defaults.riscv_tune |
| 54 | + |
| 55 | + # RISCV FPU (value for -mfpu flag). |
| 56 | + riscv_fpu = _defaults.riscv_fpu |
| 57 | + |
| 58 | + # RISCV float ABI (value for -mfloat-abi flag). |
| 59 | + riscv_float_abi = _defaults.riscv_float_abi |
| 60 | + |
| 61 | + # RISCV ABI (value for -mabi flag). |
| 62 | + riscv_abi = _defaults.riscv_abi |
| 63 | + } |
| 64 | +} |
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