Apply TBI to virtual addresses on aarch64.

In tag-based KASAN modes, TCR_EL1.TBI1 is enabled, which causes the
top 8 bits of virtual addresses to be ignored for address translation
purposes. Do the same in the page table iterator. There is no harm in
doing so unconditionally, as the architecture does not support >56 bit
VA sizes.

libdrgn/arch_aarch64.c

@@ -392,6 +392,13 @@ static void linux_kernel_pgtable_iterator_init_aarch64(struct drgn_program *prog
 {
 	struct pgtable_iterator_aarch64 *it =
 		container_of(_it, struct pgtable_iterator_aarch64, it);
+
+	/* Apply TBI. */
+	if (it->it.virt_addr & (1ULL << 55))
+		it->it.virt_addr |= 0xFFULL << 56;
+	else
+		it->it.virt_addr &= ~(0xFFULL << 56);
+
 	if (it->it.pgtable == prog->vmcoreinfo.swapper_pg_dir) {
 		it->va_range_min = UINT64_MAX << prog->vmcoreinfo.va_bits;
 		it->va_range_max = UINT64_MAX;