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nand2marionand2mario
committed
works with bl616 firmware
1 parent 6dccc60 commit d9aaf51

14 files changed

+487
-163
lines changed

‎build.tcl

+9-4
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,17 @@
11
if {$argc == 0} {
2-
puts "Usage: $argv0 <device> <mcu>"
2+
puts "Usage: $argv0 <device> [<mcu>]"
33
puts " device: mega60k, mega138k, mega138kpro, console60k"
44
puts " mcu: bl616, picorv32"
55
exit 1
66
}
77

88
set dev [lindex $argv 0]
9-
set mcu [lindex $argv 1]
9+
10+
if {$argc >= 2} {
11+
set mcu [lindex $argv 1]
12+
} else {
13+
set mcu "bl616"
14+
}
1015

1116
if {$dev eq "mega60k"} {
1217
set_device GW5AT-LV60PG484AC1/I0 -device_version B
@@ -56,7 +61,7 @@ if {$dev eq "mega60k"} {
5661

5762
if {$mcu eq "bl616"} {
5863
add_file -type verilog "src/iosys/iosys_bl616.v"
59-
add_file -type verilog "src/iosys/uart_fractional.v"
64+
add_file -type verilog "src/iosys/uart_fixed.v"
6065
} elseif {$mcu eq "picorv32"} {
6166
add_file -type verilog "src/iosys/iosys_picorv32.v"
6267
add_file -type verilog "src/iosys/picorv32.v"
@@ -139,6 +144,6 @@ set_option -use_mspi_as_gpio 1
139144
set_option -use_cpu_as_gpio 1
140145

141146
# use the slower but timing-optimized place algorithm
142-
set_option -place_option 2
147+
set_option -place_option 3
143148

144149
run all

‎buildall.bat

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11

2+
@REM 'x REG unPlaced' problem:
3+
@REM 1.9.11 placement algo 3 works
24

3-
set GWSH=..\..\Gowin_V1.9.10.03_x64\IDE\bin\gw_sh
5+
set GWSH=\Gowin\Gowin_V1.9.10.03_x64\IDE\bin\gw_sh
46

57
echo
68
echo "============ Building console60k ==============="

‎gbatang_console60k_bl616.gprj

+2-2
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55
<Version>5</Version>
66
<Device name="GW5AT-60B" pn="GW5AT-LV60PG484AC1/I0">gw5at60b-002</Device>
77
<FileList>
8+
<File path="src/iosys/iosys_bl616.v" type="file.verilog" enable="1"/>
89
<File path="src/common/dpram32_block.v" type="file.verilog" enable="1"/>
910
<File path="src/common/dpram_block.v" type="file.verilog" enable="1"/>
1011
<File path="src/common/dual_clk_fifo.v" type="file.verilog" enable="1"/>
1112
<File path="src/common/eprocreg_gba.sv" type="file.verilog" enable="1"/>
12-
<File path="src/iosys/iosys_bl616.v" type="file.verilog" enable="1"/>
1313
<File path="src/cpu/gba_cpu.v" type="file.verilog" enable="1"/>
1414
<File path="src/cpu/gba_cpu_thumbdecoder.v" type="file.verilog" enable="1"/>
1515
<File path="src/cpu/gba_interrupts.v" type="file.verilog" enable="1"/>
@@ -41,7 +41,7 @@
4141
<File path="src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
4242
<File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/>
4343
<File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/>
44-
<File path="src/iosys/uart_fractional.v" type="file.verilog" enable="1"/>
44+
<File path="src/iosys/uart_fixed.v" type="file.verilog" enable="1"/>
4545
<File path="src/m138k/fb.v" type="file.verilog" enable="1"/>
4646
<File path="src/m60k/pll_27.v" type="file.verilog" enable="1"/>
4747
<File path="src/m60k/pll_33.v" type="file.verilog" enable="1"/>

‎gbatang_console60k_picorv32.gprj

+78
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
<?xml version="1" encoding="UTF-8"?>
2+
<!DOCTYPE gowin-fpga-project>
3+
<Project>
4+
<Template>FPGA</Template>
5+
<Version>5</Version>
6+
<Device name="GW5AT-60B" pn="GW5AT-LV60PG484AC1/I0">gw5at60b-002</Device>
7+
<FileList>
8+
<File path="src/common/dpram32_block.v" type="file.verilog" enable="1"/>
9+
<File path="src/common/dpram_block.v" type="file.verilog" enable="1"/>
10+
<File path="src/common/dual_clk_fifo.v" type="file.verilog" enable="1"/>
11+
<File path="src/common/eprocreg_gba.sv" type="file.verilog" enable="1"/>
12+
<File path="src/iosys/iosys_picorv32.v" type="file.verilog" enable="1"/>
13+
14+
<File path="src/cpu/gba_cpu.v" type="file.verilog" enable="1"/>
15+
<File path="src/cpu/gba_cpu_thumbdecoder.v" type="file.verilog" enable="1"/>
16+
<File path="src/cpu/gba_interrupts.v" type="file.verilog" enable="1"/>
17+
<File path="src/gba2hdmi.sv" type="file.verilog" enable="1"/>
18+
<File path="src/gbatang_top.sv" type="file.verilog" enable="1"/>
19+
<File path="src/gpu/gba_drawer_merge.v" type="file.verilog" enable="1"/>
20+
<File path="src/gpu/gba_drawer_mode0.v" type="file.verilog" enable="1"/>
21+
<File path="src/gpu/gba_drawer_mode2.v" type="file.verilog" enable="1"/>
22+
<File path="src/gpu/gba_drawer_mode345.v" type="file.verilog" enable="1"/>
23+
<File path="src/gpu/gba_drawer_obj.sv" type="file.verilog" enable="1"/>
24+
<File path="src/gpu/gba_gpu.v" type="file.verilog" enable="1"/>
25+
<File path="src/gpu/gba_gpu_colorshade.sv" type="file.verilog" enable="1"/>
26+
<File path="src/gpu/gba_gpu_drawer.v" type="file.verilog" enable="1"/>
27+
<File path="src/gpu/gba_gpu_timing.v" type="file.verilog" enable="1"/>
28+
<File path="src/gpu/gba_timer.v" type="file.verilog" enable="1"/>
29+
<File path="src/gpu/gba_timer_module.v" type="file.verilog" enable="1"/>
30+
<File path="src/gpu/linebuffer.v" type="file.verilog" enable="1"/>
31+
<File path="src/gpu/vram_hi.v" type="file.verilog" enable="1"/>
32+
<File path="src/gpu/vram_lo.v" type="file.verilog" enable="1"/>
33+
<File path="src/hdmi/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
34+
<File path="src/hdmi/audio_info_frame.sv" type="file.verilog" enable="1"/>
35+
<File path="src/hdmi/audio_sample_packet.sv" type="file.verilog" enable="1"/>
36+
<File path="src/hdmi/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
37+
<File path="src/hdmi/hdmi.sv" type="file.verilog" enable="1"/>
38+
<File path="src/hdmi/packet_assembler.sv" type="file.verilog" enable="1"/>
39+
<File path="src/hdmi/packet_picker.sv" type="file.verilog" enable="1"/>
40+
<File path="src/hdmi/serializer.sv" type="file.verilog" enable="1"/>
41+
<File path="src/hdmi/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
42+
<File path="src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
43+
<File path="src/iosys/gowin_dpb_menu.v" type="file.verilog" enable="1"/>
44+
<File path="src/iosys/picorv32.v" type="file.verilog" enable="1"/>
45+
<File path="src/iosys/simplespimaster.v" type="file.verilog" enable="1"/>
46+
<File path="src/iosys/simpleuart.v" type="file.verilog" enable="1"/>
47+
<File path="src/iosys/spi_master.v" type="file.verilog" enable="1"/>
48+
<File path="src/iosys/spiflash.v" type="file.verilog" enable="1"/>
49+
<File path="src/iosys/textdisp.v" type="file.verilog" enable="1"/>
50+
<File path="src/m138k/fb.v" type="file.verilog" enable="1"/>
51+
<File path="src/m60k/pll_27.v" type="file.verilog" enable="1"/>
52+
<File path="src/m60k/pll_33.v" type="file.verilog" enable="1"/>
53+
<File path="src/m60k/pll_74.v" type="file.verilog" enable="1"/>
54+
<File path="src/memory/gba_dma.v" type="file.verilog" enable="1"/>
55+
<File path="src/memory/gba_dma_module.sv" type="file.verilog" enable="1"/>
56+
<File path="src/memory/gba_eeprom.sv" type="file.verilog" enable="1"/>
57+
<File path="src/memory/gba_flash_sram.sv" type="file.verilog" enable="1"/>
58+
<File path="src/memory/gba_memory.sv" type="file.verilog" enable="1"/>
59+
<File path="src/memory/mem_eeprom.v" type="file.verilog" enable="1"/>
60+
<File path="src/memory/mem_iwram.v" type="file.verilog" enable="1"/>
61+
<File path="src/memory/rv_sdram_adapter.v" type="file.verilog" enable="1"/>
62+
<File path="src/memory/sdram_gba.v" type="file.verilog" enable="1"/>
63+
<File path="src/peripherals/controller_ds2.sv" type="file.verilog" enable="1"/>
64+
<File path="src/peripherals/dualshock_controller.v" type="file.verilog" enable="1"/>
65+
<File path="src/peripherals/gba_joypad.v" type="file.verilog" enable="1"/>
66+
<File path="src/sound/gba_sound.v" type="file.verilog" enable="1"/>
67+
<File path="src/sound/gba_sound_ch1.v" type="file.verilog" enable="1"/>
68+
<File path="src/sound/gba_sound_ch3.v" type="file.verilog" enable="1"/>
69+
<File path="src/sound/gba_sound_ch4.v" type="file.verilog" enable="1"/>
70+
<File path="src/sound/gba_sound_dma.v" type="file.verilog" enable="1"/>
71+
<File path="src/console60k/gbatang.cst" type="file.cst" enable="1"/>
72+
<File path="src/gbatang.sdc" type="file.sdc" enable="1"/>
73+
<File path="src/eeprom.gao" type="file.gao" enable="0"/>
74+
<File path="src/gbatang.gao" type="file.gao" enable="0"/>
75+
<File path="src/gpu.gao" type="file.gao" enable="0"/>
76+
<File path="src/iosys.gao" type="file.gao" enable="0"/>
77+
</FileList>
78+
</Project>

‎gbatang_m60k.gprj.user

+27
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
<?xml version="1" encoding="UTF-8"?>
2+
<!DOCTYPE ProjectUserData>
3+
<UserConfig>
4+
<Version>1.0</Version>
5+
<FlowState>
6+
<Process ID="Synthesis" State="2"/>
7+
<Process ID="Pnr" State="2"/>
8+
<Process ID="Gao" State="2"/>
9+
<Process ID="Rtl_Gao" State="2"/>
10+
<Process ID="Gvio" State="0"/>
11+
<Process ID="Place" State="2"/>
12+
</FlowState>
13+
<ResultFileList>
14+
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/gbatang.vg"/>
15+
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/gbatang.fs"/>
16+
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/gbatang.pin.html"/>
17+
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/gbatang.db"/>
18+
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/gbatang.power.html"/>
19+
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/gbatang.rpt.html"/>
20+
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/gbatang.timing_paths"/>
21+
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/gbatang.tr.html"/>
22+
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/gbatang_syn.rpt.html"/>
23+
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/gbatang_syn_rsc.xml"/>
24+
</ResultFileList>
25+
<Ui>000000ff00000001fd00000002000000000000031d00000586fc0200000001fc0000004b000005860000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000c8000000145fc0100000001fc0000000000000c80000000f400fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000f400ffffff0000095b0000058600000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000275ffffffff0000000000000000</Ui>
26+
<FpUi></FpUi>
27+
</UserConfig>

‎impl/gbatang_console60k_bl616_process_config.json

+2-2
Original file line numberDiff line numberDiff line change
@@ -50,14 +50,14 @@
5050
"MULTIJUMP_MODE" : "Normal",
5151
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
5252
"Multi_Boot" : false,
53-
"OUTPUT_BASE_NAME" : "gbatang_console60k",
53+
"OUTPUT_BASE_NAME" : "gbatang_console60k_bl616",
5454
"POWER_ON_RESET_MONITOR" : true,
5555
"PRINT_BSRAM_VALUE" : true,
5656
"PROGRAM_DONE_BYPASS" : false,
5757
"PlaceInRegToIob" : true,
5858
"PlaceIoRegToIob" : true,
5959
"PlaceOutRegToIob" : true,
60-
"Place_Option" : "2",
60+
"Place_Option" : "3",
6161
"Process_Configuration_Verion" : "1.0",
6262
"Promote_Physical_Constraint_Warning_to_Error" : true,
6363
"READY" : false,

‎src/gbatang_top.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -468,7 +468,7 @@ gba2hdmi video (
468468

469469
`ifdef MCU_BL616
470470

471-
iosys_bl616 #(.CORE_ID(3), .COLOR_LOGO(15'b01111_01100_10101)) iosys (
471+
iosys_bl616 #(.CORE_ID(3), .COLOR_LOGO(15'b01111_01100_10101), .FREQ(16_650_000)) iosys (
472472
.clk(clk16), .hclk(hclk), .resetn(resetn),
473473

474474
.overlay(overlay), .overlay_x(overlay_x), .overlay_y(overlay_y), .overlay_color(overlay_color),

‎src/iosys/iosys_bl616.v

+54-25
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ localparam [8*STR_LEN-1:0] CONF_STR = "Tangcores;-;O12,OSD key,Right+Select,Sele
4343

4444
// Remove SPI parameters and add UART parameters
4545
localparam CLK_FREQ = FREQ;
46-
localparam BAUD_RATE = 1_000_000;
46+
localparam BAUD_RATE = 2_000_000;
4747

4848
reg overlay_reg = 1;
4949
assign overlay = overlay_reg;
@@ -57,29 +57,58 @@ reg [7:0] tx_data;
5757
reg tx_valid;
5858
wire tx_ready;
5959

60+
// synchronize uart_rx to clk
61+
reg uart_rx_r = 1, uart_rx_rr = 1;
62+
always @(posedge clk) begin
63+
uart_rx_r <= uart_rx;
64+
uart_rx_rr <= uart_rx_r;
65+
end
66+
6067
// Instantiate UART modules
61-
uart_rx_fractional #(
62-
.DIV_NUM(CLK_FREQ/1000),
63-
.DIV_DEN(BAUD_RATE/1000)
68+
async_receiver #(
69+
.ClkFrequency(CLK_FREQ),
70+
.Baud(BAUD_RATE)
6471
) uart_receiver (
6572
.clk(clk),
66-
.resetn(resetn),
67-
.rx(uart_rx),
68-
.data(rx_data),
69-
.valid(rx_valid)
73+
.RxD(uart_rx_rr),
74+
.RxD_data(rx_data),
75+
.RxD_data_ready(rx_valid)
7076
);
7177

72-
uart_tx_fractional #(
73-
.DIV_NUM(CLK_FREQ/1000),
74-
.DIV_DEN(BAUD_RATE/1000)
78+
async_transmitter #(
79+
.ClkFrequency(CLK_FREQ),
80+
.Baud(BAUD_RATE)
7581
) uart_transmitter (
7682
.clk(clk),
77-
.resetn(resetn),
78-
.tx(uart_tx),
79-
.data(tx_data),
80-
.valid(tx_valid),
81-
.ready(tx_ready)
83+
.TxD(uart_tx),
84+
.TxD_data(tx_data),
85+
.TxD_start(tx_valid),
86+
.TxD_busy(tx_busy)
8287
);
88+
assign tx_ready = ~tx_busy;
89+
90+
// uart_rx_fractional #(
91+
// .DIV_NUM(CLK_FREQ/1000),
92+
// .DIV_DEN(BAUD_RATE/1000)
93+
// ) uart_receiver (
94+
// .clk(clk),
95+
// .resetn(resetn),
96+
// .rx(uart_rx),
97+
// .data(rx_data),
98+
// .valid(rx_valid)
99+
// );
100+
101+
// uart_tx_fractional #(
102+
// .DIV_NUM(CLK_FREQ/1000),
103+
// .DIV_DEN(BAUD_RATE/1000)
104+
// ) uart_transmitter (
105+
// .clk(clk),
106+
// .resetn(resetn),
107+
// .tx(uart_tx),
108+
// .data(tx_data),
109+
// .valid(tx_valid),
110+
// .ready(tx_ready)
111+
// );
83112

84113
// Command processing state machine
85114
localparam RECV_IDLE = 0; // waiting for command
@@ -150,7 +179,7 @@ always @(posedge clk) begin
150179
cmd_reg <= rx_data;
151180
if (rx_data == 1 || rx_data == 2)
152181
recv_state <= RECV_RESPONSE_REQ;
153-
else
182+
else if (rx_data <= 8)
154183
recv_state <= RECV_PARAM;
155184
data_cnt <= 0;
156185
end
@@ -194,6 +223,8 @@ always @(posedge clk) begin
194223
7: begin
195224
if (data_cnt < 3) begin
196225
rom_remain <= {rom_remain[15:0], rx_data};
226+
if (data_cnt == 2 && {rom_remain[15:0], rx_data} == 0) // shortcut return
227+
recv_state <= RECV_IDLE;
197228
end else begin
198229
rom_do <= rx_data;
199230
rom_do_valid <= 1; // pulse data valid
@@ -242,7 +273,7 @@ localparam SEND_JOYPAD = 4;
242273
reg [2:0] send_state;
243274
reg [$clog2(STR_LEN+1)-1:0] send_idx;
244275
localparam JOY_UPDATE_INTERVAL = 50_000_000 / 50; // 20ms interval for 50Hz
245-
reg [31:0] joy_timer;
276+
reg [$clog2(JOY_UPDATE_INTERVAL+1)-1:0] joy_timer;
246277
reg [15:0] joy1_reg;
247278
reg [15:0] joy2_reg;
248279

@@ -255,17 +286,15 @@ always @(posedge clk) begin
255286
tx_valid <= 0;
256287

257288
// Joypad state transmission logic
258-
joy_timer <= joy_timer + 1;
259-
if (joy_timer >= JOY_UPDATE_INTERVAL) begin
260-
joy_timer <= 0;
261-
joy1_reg <= joy1;
262-
joy2_reg <= joy2;
263-
end
289+
joy_timer <= joy_timer == 0 ? 0 : joy_timer - 1;
264290

265291
// UART transmission state machine
266292
case (send_state)
267293
SEND_IDLE: begin
268-
if (joy_timer >= JOY_UPDATE_INTERVAL) begin
294+
if (joy_timer == 0 && (joy1 != joy1_reg || joy2 != joy2_reg)) begin
295+
joy_timer <= JOY_UPDATE_INTERVAL;
296+
joy1_reg <= joy1;
297+
joy2_reg <= joy2;
269298
send_state <= SEND_JOYPAD;
270299
send_idx <= 0;
271300
end else if (response_req != response_ack) begin

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