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notro edited this page Sep 13, 2013 · 15 revisions

This is a fork of the DMA capable SPI master driver by Martin Sperl.

In addition to adding DMA it also silences this message

bcm2708_spi bcm2708_spi.0: master is unqueued, this is deprecated

Module arguments

  • mode
    2 - dma (default)
    1 - interrupt
    0 - polled
  • realtime
    Run with realtime priority

FIFO size

Excerpt from BCM2835 ARM Peripherals datasheet

10.6.2 Interrupt 
e) Set INTR and INTD. These can be left set over multiple operations. 
f) Set CS, CPOL, CPHA as required and set TA = 1. This will immediately trigger a 
first interrupt with DONE == 1. 
g) On interrupt: 
h) If DONE is set and data to write (this means it is the first interrupt), write up to 16 
bytes to SPI_FIFO. If DONE is set and no more data, set TA = 0. Read trailing data 
from SPI_FIFO until RXD is 0. 
i) If RXR is set read 12 bytes data from SPI_FIFO and if more data to write, write up to 
12 bytes to SPIFIFO.

The vanilla driver follows this to the letter. Martin Sperl in his version fills the FIFO until it is full.
I added printk statements to bcm2708_transfer_one_message_irqdriven() and bcm2708_transfer_one_message_irqdriven_irqhandler() printing out how many bytes was written to the FIFO. This showed that the buffer can be filled with 110-120 bytes. This gives a tenth the number of interrupts per transfer. This minimizes latency and decreases the total transfer time.

References

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