52
52
#define MMU_IO_BASE (0x00000000ul)
53
53
#define MMU_IO_SIZE (0x40000000ul)
54
54
55
- //// TODO: #define MMU_INT_BASE (0xe0000000ul )
56
- //// TODO: #define MMU_INT_SIZE (0x10000000ul)
55
+ #define MMU_INT_BASE (0x70000000ul )
56
+ #define MMU_INT_SIZE (0x10000000ul)
57
57
58
58
/* Physical and virtual addresses to page tables (vaddr = paddr mapping) */
59
59
60
60
#define PGT_L1_PBASE (uintptr_t)&m_l1_pgtable
61
61
#define PGT_L2_PBASE (uintptr_t)&m_l2_pgtable
62
- //// TODO: #define PGT_L2_INT_PBASE (uintptr_t)&m_l2_int_pgtable
62
+ #define PGT_L2_INT_PBASE (uintptr_t)&m_l2_int_pgtable
63
63
#define PGT_L3_PBASE (uintptr_t)&m_l3_pgtable
64
64
#define PGT_L1_VBASE PGT_L1_PBASE
65
65
#define PGT_L2_VBASE PGT_L2_PBASE
66
- //// TODO: #define PGT_L2_INT_VBASE PGT_L2_INT_PBASE
66
+ #define PGT_L2_INT_VBASE PGT_L2_INT_PBASE
67
67
#define PGT_L3_VBASE PGT_L3_PBASE
68
68
69
69
#define PGT_L1_SIZE (512) /* Enough to map 512 GiB */
70
70
#define PGT_L2_SIZE (512) /* Enough to map 1 GiB */
71
- //// TODO: #define PGT_L2_INT_SIZE (512) /* Enough to map 1 GiB */
71
+ #define PGT_L2_INT_SIZE (512) /* Enough to map 1 GiB */
72
72
#define PGT_L3_SIZE (1024) /* Enough to map 4 MiB (2MiB x 2) */
73
73
74
74
#define SLAB_COUNT (sizeof(m_l3_pgtable) / RV_MMU_PAGE_SIZE)
@@ -98,7 +98,7 @@ typedef struct pgalloc_slab_s pgalloc_slab_t;
98
98
99
99
static size_t m_l1_pgtable [PGT_L1_SIZE ] locate_data (".pgtables" );
100
100
static size_t m_l2_pgtable [PGT_L2_SIZE ] locate_data (".pgtables" );
101
- //// TODO: static size_t m_l2_int_pgtable[PGT_L2_INT_SIZE] locate_data(".pgtables");
101
+ static size_t m_l2_int_pgtable [PGT_L2_INT_SIZE ] locate_data (".pgtables" );
102
102
static size_t m_l3_pgtable [PGT_L3_SIZE ] locate_data (".pgtables" );
103
103
104
104
/* Kernel mappings (L1 base) */
@@ -244,7 +244,6 @@ void bl808_kernel_mappings(void)
244
244
mmu_ln_map_region (1 , PGT_L1_VBASE , MMU_IO_BASE , MMU_IO_BASE ,
245
245
MMU_IO_SIZE , MMU_THEAD_IO_FLAGS );
246
246
247
- #ifdef TODO ////
248
247
/* Map the PLIC with L2 page table */
249
248
250
249
binfo ("map PLIC with L2 page table\n" );
@@ -255,7 +254,6 @@ void bl808_kernel_mappings(void)
255
254
256
255
binfo ("connect the L1 and PLIC L2 page tables\n" );
257
256
mmu_ln_setentry (1 , PGT_L1_VBASE , PGT_L2_INT_PBASE , MMU_INT_BASE , PTE_G );
258
- #endif //// TODO
259
257
260
258
/* Map the kernel text and data for L2/L3 */
261
259
0 commit comments