EalrGrey Questa support?

[muntenau]

Hello!

I am new to Open Titan and RISC-V in general. I really like that way this project is organised!

Using Verilator I can simulate EarlGrey. The whole flow works smooth... I get the messages on the terminal, I see waveforms etc.

However, I am facing difficulties trying to simulate EarGray with Questa

This is the command I use:
fusesoc --cores-root . run --flag=fileset_top --target=sim --tool=modelsim --setup --build lowrisc:systems:top_earlgrey_verilator

It generates a build script that is missing the C sources:
build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-modelsim/edalize_build_rtl.tcl
I tried to add them by hand, but without much success so far.

I am wondering if anybody was successful in simulating EarlGrey with Questa? This tool does not appear to be supported.

What about VCS? Is it fully supported to simulate Earl Grey?

Thank you,
Mihai

[imphil]

Thanks for trying out OpenTitan.

We don't use Questa regularly, most of us don't even have access to it. Almost all verification is done using VCS and it is generally best supported.

What are you trying to achieve? If you're trying to run a chip-level simulation you have to go through dvsim, not through fusesoc. You can find more information at https://docs.opentitan.org/doc/ug/getting_started_dv/.

We are of course happy to accept pull requests to improve Questa support, but it's not something we can work on ourselves, unfortunately.

Please let us know by re-opening this issue if you have further issues with this. Or open another issue if you have a different question.