[aes, dv] Extend tests to hit missing functional coverpoints

[vogelpi]

Description

IIUC, the scoreboard isn't enabled during automated CSR tests which is why the following functional coverpoints are currently not hit:

• aes_aux_regwen_cg: Extend aes_init() to randomly lock the register and if locking, modifying the ctrl_aux_shadowed register.
• aes_alert_cg: Extend aes_alert_reset_vseq.sv to also write the alert test register.
• aes_status_cg: Extend setup_dut() to randomly inject control update errors with low probability and verify that the status register indicates the error.
• aes_ctrl_cg: Enable configuration errors with sideload, currently we have

  constraint config_error_type_c {
      solve has_config_error before cfg_error_type;
      solve sideload_en before cfg_error_type;
      if (has_config_error & !sideload_en) {
        cfg_error_type inside {[1:7]};
        config_error_type_en[0] -> cfg_error_type[0] == 0;
        config_error_type_en[1] -> cfg_error_type[1] == 0;
        config_error_type_en[2] -> cfg_error_type[2] == 0;
      } else {
        cfg_error_type == 3'b000;
      }
    }

  i.e. whenever sideload is enabled, no configuration error is inserted. This is observable from aes_ctrl_cg.

I am labeling this as V3 as nothing of this is really critical. The only thing that is really relevant for M2.5 and where there is a slight risk that something could go wrong (because probably not covered by automated CSR tests) is the aes_aux_regwen_cg. However, this feature is actually tested using a TLT which disables masking. This is sufficient for M2.5.

[vogelpi]

FYI, I have a branch that addresses all these things and will push a PR once the quiet period is over. With these changes I get the same pass rates as on master with function coverage increasing to roughly 98% from previously 92% (masked) and 91% (unmasked).