[aes] aes_core simulation using ModelSim

[Adam11072000]

Description

Hello,

we're trying to simulate aes_core module using ModelSim simulator with Vivado IDE and we're getting this error:

** Error: ../../../../hw/ip/prim/rtl/prim_lfsr.sv(467): (vlog-2980) Error: The 'slice_size' portion of the streaming concatenation operator must

be a simple data type or a constant expression.

the error refers to:
{<<LfsrIdxDw{col}};
which is a correct syntax byt is failing with ModelSim

we've tried verilator too but we cannot seem to find a way to generate waveforms for aes module.
can you help?

thanks

[vogelpi]

Hi @Adam11072000 ,
at the moment we use primarily VCS and Xcelium for OpenTitan. Other simulators like Questa/ModelSim might work or not. As I don't have access to this tool, I cannot really assist here.

Regarding Verilator, I see two options to get traces:

1. You use the Verilated simulation of the Earlgrey top-level which also instantiates the AES core. You can run e.g. aes_smoketest and enable tracing to get some AES waves. For details, please refer to the documentation of the Verilator setup.
2. I have developed a scratch verification TB in Verilator to develop the AES unit. It's not in the repository but on my personal branch here: https://github.com/vogelpi/opentitan/tree/aes-dev-verilator For details on how to run it, please refer to the README.

[m-temp]

When using verilator, you could also have a look at my branch. Unfortunately, it's very out of date (better not to use it as I don't know it it runs with the current aes core), but my commented aes_tlul_sequence might help to understand the bus communication better and the python script can be used to generate longer stimuli.

[vogelpi]

I am closing this issue as the original question on how to get AES waves using Verilator has been answered and there hasn't been any activity in here for more than 6 months now. Also #19216 now adds a simple Verilator testbench for the AES cipher core on master.