From c7a9b55023bc1910e1d2e0383dfab0314f525213 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 18:49:38 +0800 Subject: [PATCH 01/25] Update RISCVSystemOperands.td --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index d85b4a9cf77b3..faec8d0b5bc00 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -276,6 +276,14 @@ foreach i = 0...15 in { foreach i = 0...63 in def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; +//===----------------------------------------------------------------------===// +// Machine Non-Maskable Interrupt Handling +//===----------------------------------------------------------------------===// +def:SysReg<"mnscratch",0x740>; +def:SysReg<"mnepc",0x741>; +def:SysReg<"mncause",0x742>; +def:SysReg<"mnstatus",0x744>; + //===----------------------------------------------------------------------===// // Machine Counter and Timers //===----------------------------------------------------------------------===// From 91125a155eed67cbe4546fb22084d83fdab61a8e Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 18:52:00 +0800 Subject: [PATCH 02/25] Update machine-csr-names.s --- llvm/test/MC/RISCV/machine-csr-names.s | 60 ++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index ae1af1fc8abc3..1e13d5c60b8a4 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero csrrs t2, 0xB1F, zero +###################################### +# Machine Counter Setup +###################################### +# mnscratch +# name +# CHECK-INST: csrrs t1, mnscratch, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74] +# CHECK-INST-ALIAS: csrr t1, mnscratch +# uimm12 +# CHECK-INST: csrrs t2, mnscratch, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74] +# CHECK-INST-ALIAS: csrr t2, mnscratch +# name +csrrs t1, mnscratch, zero +# uimm12 +csrrs t2, 0x740, zero + +# mnepc +# name +# CHECK-INST: csrrs t1, mnepc, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74] +# CHECK-INST-ALIAS: csrr t1, mnepc +# uimm12 +# CHECK-INST: csrrs t2, mnepc, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74] +# CHECK-INST-ALIAS: csrr t2, mnepc +# name +csrrs t1, mnepc, zero +# uimm12 +csrrs t2, 0x741, zero + +# mncause +# name +# CHECK-INST: csrrs t1, mncause, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74] +# CHECK-INST-ALIAS: csrr t1, mncause +# uimm12 +# CHECK-INST: csrrs t2, mncause, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74] +# CHECK-INST-ALIAS: csrr t2, mncause +# name +csrrs t1, mncause, zero +# uimm12 +csrrs t2, 0x742, zero + +# mnstatus +# name +# CHECK-INST: csrrs t1, mnstatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74] +# CHECK-INST-ALIAS: csrr t1, mnstatus +# uimm12 +# CHECK-INST: csrrs t2, mnstatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74] +# CHECK-INST-ALIAS: csrr t2, mnstatus +# name +csrrs t1, mnstatus, zero +# uimm12 +csrrs t2, 0x744, zero + + ###################################### # Machine Counter Setup ###################################### From 6014139b67ae601ae33aa13919a4dd29b2e18313 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 18:53:54 +0800 Subject: [PATCH 03/25] Update riscv-target-features.c --- clang/test/Preprocessor/riscv-target-features.c | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 05a8534ba13da..5a595742939ff 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -30,6 +30,7 @@ // CHECK-NOT: __riscv_smcdeleg {{.*$}} // CHECK-NOT: __riscv_smcsrind {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} +// CHECK-NOT: __riscv_smrnmi {{.*$}} // CHECK-NOT: __riscv_smstateen {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} // CHECK-NOT: __riscv_ssccfg {{.*$}} From 8706286d0d39eb72687b45a35dfd0a064edd1484 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 18:55:07 +0800 Subject: [PATCH 04/25] Update RISCVUsage.rst --- llvm/docs/RISCVUsage.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 5736f3807f131..a7ea36191283a 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -129,6 +129,7 @@ on support follow. ``Smcdeleg`` Supported ``Smcsrind`` Supported ``Smepmp`` Supported + ``Smrnmi`` Supported ``Smstateen`` Assembly Support ``Ssaia`` Supported ``Ssccfg`` Supported From 68447548c1c4988e4d4cc134e716e769ec26a770 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 18:58:29 +0800 Subject: [PATCH 05/25] Update RISCVFeatures.td --- llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3d0e1dae801d3..10b18e33f2abb 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -931,6 +931,10 @@ def FeatureStdExtSmepmp : RISCVExtension<"smepmp", 1, 0, "'Smepmp' (Enhanced Physical Memory Protection)">; +def FeatureStdExtSmrnmi + : RISCVExtension<"smrnmi", 1, 0, + "'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">; + def FeatureStdExtSmcdeleg : RISCVExtension<"smcdeleg", 1, 0, "'Smcdeleg' (Counter Delegation Machine Level)">; From 7922fbb048021ca4cc6dea5dfe9c1f184dc951a9 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 18:59:50 +0800 Subject: [PATCH 06/25] Update attributes.ll --- llvm/test/CodeGen/RISCV/attributes.ll | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 86ce368bc1db6..ca213f3733978 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -118,6 +118,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s +; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s From c8fccb5a116b7a510266daf1f2020ae8b658448a Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:05:08 +0800 Subject: [PATCH 07/25] Update attributes.ll --- llvm/test/CodeGen/RISCV/attributes.ll | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index ca213f3733978..aa27d63bfa626 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -262,6 +262,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s +; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s @@ -411,6 +412,7 @@ ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" +; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" @@ -552,6 +554,7 @@ ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" +; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" From 3d6f0fe593a22fdb565af3849e18795ec06ce062 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:06:24 +0800 Subject: [PATCH 08/25] Update attribute-arch.s --- llvm/test/MC/RISCV/attribute-arch.s | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 1c0b2a59d0693..078a58f013907 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -327,6 +327,9 @@ .attribute arch, "rv32i_smepmp1p0" # CHECK: attribute 5, "rv32i2p1_smepmp1p0" +.attribute arch, "rv32i_smrnmi1p0" +# CHECK: attribute 5, "rv32i2p1_smrnmid1p0" + .attribute arch, "rv32i_ssccfg1p0" # CHECK: attribute 5, "rv32i2p1_ssccfg1p0" From 805fd8aa16dbc8b3e7839d00f63121c44f269595 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:07:18 +0800 Subject: [PATCH 09/25] Update RISCVISAInfoTest.cpp --- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 33944b64dc157..ded43a4ff7875 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1065,6 +1065,7 @@ R"(All available -march extensions for RISC-V smcdeleg 1.0 smcsrind 1.0 smepmp 1.0 + smrnmi 1.0 smstateen 1.0 ssaia 1.0 ssccfg 1.0 From 35588a36e35e6d71b37b5db063ca2798faef7b71 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:12:20 +0800 Subject: [PATCH 10/25] Update riscv-target-features.c --- clang/test/Preprocessor/riscv-target-features.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 5a595742939ff..6cd011533362f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1450,6 +1450,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32ismrnmi1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64ismrnmi1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s +// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izfa -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s From f49795058fb4d430df87f5effe15ca117db27bdc Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:15:36 +0800 Subject: [PATCH 11/25] Update riscv-target-features.c --- clang/test/Preprocessor/riscv-target-features.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 6cd011533362f..9e986f0143aef 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1450,13 +1450,13 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s // CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}} -// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: %clang --target=riscv32 \ // RUN: -march=rv32ismrnmi1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s -// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: %clang --target=riscv64 \ // RUN: -march=rv64ismrnmi1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s -// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}} +// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}} // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izfa -E -dM %s \ From 7db01e77a65c6f86d37cd08ee7d38cfb61ceb521 Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:18:46 +0800 Subject: [PATCH 12/25] Update RISCVInstrInfo.td --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 5d329dceac651..485fe386187c5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -66,6 +66,8 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; +def riscv_mnret_glue : SDNode<"RISCVISD::MNRET_GLUE", SDTNone, + [SDNPHasChain, SDNPOptInGlue]>; def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>; def riscv_brcc : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC, [SDNPHasChain]>; @@ -813,6 +815,12 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> { let rs1 = 0; let rs2 = 0b00010; } + +def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> { + let rd = 0; + let rs1 = 0; + let rs2 = 0b00010; +} } // isBarrier = 1, isReturn = 1, isTerminator = 1 def WFI : Priv<"wfi", 0b0001000>, Sched<[]> { @@ -1581,6 +1589,7 @@ def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; def : Pat<(riscv_sret_glue), (SRET)>; def : Pat<(riscv_mret_glue), (MRET)>; +def : Pat<(riscv_mnret_glue), (MNRET)>; let isCall = 1, Defs = [X1] in { let Predicates = [NoStdExtZicfilp] in From 29eaa52c269f0bd5fe834a8195da85091998d4ae Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:19:32 +0800 Subject: [PATCH 13/25] Update priv-valid.s --- llvm/test/MC/RISCV/priv-valid.s | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s index 561c76bf4fa29..75dc8c6b98cc5 100644 --- a/llvm/test/MC/RISCV/priv-valid.s +++ b/llvm/test/MC/RISCV/priv-valid.s @@ -17,6 +17,10 @@ sret # CHECK: encoding: [0x73,0x00,0x20,0x30] mret +# CHECK-INST: mnret +# CHECK: encoding: [0x73,0x00,0x20,0x70] +mnret + # CHECK-INST: wfi # CHECK: encoding: [0x73,0x00,0x50,0x10] wfi From 3c5f6d1b37c64f56f93d6bc88ba17703020231cc Mon Sep 17 00:00:00 2001 From: dong-miao <65881865+dong-miao@users.noreply.github.com> Date: Wed, 9 Oct 2024 19:20:05 +0800 Subject: [PATCH 14/25] Update priv-invalid.s --- llvm/test/MC/RISCV/priv-invalid.s | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s index d0446dbd1f865..e9ed3c3d0d0ab 100644 --- a/llvm/test/MC/RISCV/priv-invalid.s +++ b/llvm/test/MC/RISCV/priv-invalid.s @@ -2,6 +2,8 @@ mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction +mnret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction + sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction From 1858bed89b11158131ce43ac3bf5a73282f99049 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 16:44:40 +0800 Subject: [PATCH 15/25] Update RISCVFeatures.td --- llvm/lib/Target/RISCV/RISCVFeatures.td | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 10b18e33f2abb..95374f2f6870a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -934,6 +934,9 @@ def FeatureStdExtSmepmp def FeatureStdExtSmrnmi : RISCVExtension<"smrnmi", 1, 0, "'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">; +def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">, + AssemblerPredicate<(all_of FeatureStdExtSmrnmi), + "'Smrnmi' (Resumable Non-Maskable Interrupts)">; def FeatureStdExtSmcdeleg : RISCVExtension<"smcdeleg", 1, 0, From dedaf014b5cd15804187dffd31f6071320c0205f Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 16:46:06 +0800 Subject: [PATCH 16/25] Update RISCVFeatures.td --- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 95374f2f6870a..7ccce2e1c70b2 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -933,7 +933,7 @@ def FeatureStdExtSmepmp def FeatureStdExtSmrnmi : RISCVExtension<"smrnmi", 1, 0, - "'Smrnmi' (Extension for Resumable Non-Maskable Interrupts)">; + "'Smrnmi' (Resumable Non-Maskable Interrupts)">; def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">, AssemblerPredicate<(all_of FeatureStdExtSmrnmi), "'Smrnmi' (Resumable Non-Maskable Interrupts)">; From 3086afc03bd17f0f80f5a3a6ad1e7671c37a80a1 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 16:49:14 +0800 Subject: [PATCH 17/25] Update RISCVInstrInfo.td --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 485fe386187c5..86cc638fd04ac 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -66,8 +66,6 @@ def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; -def riscv_mnret_glue : SDNode<"RISCVISD::MNRET_GLUE", SDTNone, - [SDNPHasChain, SDNPOptInGlue]>; def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>; def riscv_brcc : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC, [SDNPHasChain]>; @@ -815,13 +813,15 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> { let rs1 = 0; let rs2 = 0b00010; } +} // isBarrier = 1, isReturn = 1, isTerminator = 1 +let Predicates = [HasStdExtSmrnmi] in { def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> { let rd = 0; let rs1 = 0; let rs2 = 0b00010; } -} // isBarrier = 1, isReturn = 1, isTerminator = 1 +}// Predicates = [HasStdExtSmrnmi] def WFI : Priv<"wfi", 0b0001000>, Sched<[]> { let rd = 0; @@ -1589,7 +1589,6 @@ def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; def : Pat<(riscv_sret_glue), (SRET)>; def : Pat<(riscv_mret_glue), (MRET)>; -def : Pat<(riscv_mnret_glue), (MNRET)>; let isCall = 1, Defs = [X1] in { let Predicates = [NoStdExtZicfilp] in From 95567b396346be23581b6296c99891711d8509ec Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 16:52:19 +0800 Subject: [PATCH 18/25] Update RISCVSystemOperands.td --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 8 -------- 1 file changed, 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index faec8d0b5bc00..d85b4a9cf77b3 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -276,14 +276,6 @@ foreach i = 0...15 in { foreach i = 0...63 in def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; -//===----------------------------------------------------------------------===// -// Machine Non-Maskable Interrupt Handling -//===----------------------------------------------------------------------===// -def:SysReg<"mnscratch",0x740>; -def:SysReg<"mnepc",0x741>; -def:SysReg<"mncause",0x742>; -def:SysReg<"mnstatus",0x744>; - //===----------------------------------------------------------------------===// // Machine Counter and Timers //===----------------------------------------------------------------------===// From 88dfe2be1c66e374d7074be1e76630a8a707f6fd Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 16:52:47 +0800 Subject: [PATCH 19/25] Update priv-invalid.s --- llvm/test/MC/RISCV/priv-invalid.s | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s index e9ed3c3d0d0ab..d0446dbd1f865 100644 --- a/llvm/test/MC/RISCV/priv-invalid.s +++ b/llvm/test/MC/RISCV/priv-invalid.s @@ -2,8 +2,6 @@ mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction -mnret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction - sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction From 1350674abac35c0f215c779b9ade4e206fde93e1 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 16:53:17 +0800 Subject: [PATCH 20/25] Update priv-valid.s --- llvm/test/MC/RISCV/priv-valid.s | 4 ---- 1 file changed, 4 deletions(-) diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s index 75dc8c6b98cc5..561c76bf4fa29 100644 --- a/llvm/test/MC/RISCV/priv-valid.s +++ b/llvm/test/MC/RISCV/priv-valid.s @@ -17,10 +17,6 @@ sret # CHECK: encoding: [0x73,0x00,0x20,0x30] mret -# CHECK-INST: mnret -# CHECK: encoding: [0x73,0x00,0x20,0x70] -mnret - # CHECK-INST: wfi # CHECK: encoding: [0x73,0x00,0x50,0x10] wfi From 116aa081d897677f92fa0d822a399fbef5835ba9 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 17:01:01 +0800 Subject: [PATCH 21/25] Create smrnmi-invalid.s --- llvm/test/MC/RISCV/smrnmi-invalid.s | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 llvm/test/MC/RISCV/smrnmi-invalid.s diff --git a/llvm/test/MC/RISCV/smrnmi-invalid.s b/llvm/test/MC/RISCV/smrnmi-invalid.s new file mode 100644 index 0000000000000..1a5e692148b37 --- /dev/null +++ b/llvm/test/MC/RISCV/smrnmi-invalid.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+smrnmi < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+smrnmi < %s 2>&1 | FileCheck %s + +mnret 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction From e07753685b7539fe031c358200863dfe5862dd6e Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Mon, 21 Oct 2024 17:01:51 +0800 Subject: [PATCH 22/25] Create smrnmi-valid.s --- llvm/test/MC/RISCV/smrnmi-valid.s | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 llvm/test/MC/RISCV/smrnmi-valid.s diff --git a/llvm/test/MC/RISCV/smrnmi-valid.s b/llvm/test/MC/RISCV/smrnmi-valid.s new file mode 100644 index 0000000000000..d330ecefa6053 --- /dev/null +++ b/llvm/test/MC/RISCV/smrnmi-valid.s @@ -0,0 +1,14 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+smrnmi -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+smrnmi -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+smrnmi < %s \ +# RUN: | llvm-objdump --mattr=+smrnmi -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+smrnmi < %s \ +# RUN: | llvm-objdump --mattr=+smrnmi -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: mnret +# CHECK: encoding: [0x73,0x00,0x20,0x70] +mnret From 6249ffb8c526c73d516c0c9d3b346666d9bdfdd4 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Tue, 22 Oct 2024 16:07:53 +0800 Subject: [PATCH 23/25] Update llvm/docs/RISCVUsage.rst Co-authored-by: Sam Elliott --- llvm/docs/RISCVUsage.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index a7ea36191283a..2135ed3b11141 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -129,7 +129,7 @@ on support follow. ``Smcdeleg`` Supported ``Smcsrind`` Supported ``Smepmp`` Supported - ``Smrnmi`` Supported + ``Smrnmi`` Assembly Support ``Smstateen`` Assembly Support ``Ssaia`` Supported ``Ssccfg`` Supported From 5a5884448708c9cc8ca4a16796f3eafe7226a180 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Thu, 24 Oct 2024 13:34:01 +0800 Subject: [PATCH 24/25] Update attribute-arch.s --- llvm/test/MC/RISCV/attribute-arch.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 078a58f013907..2332bcacc99d0 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -328,7 +328,7 @@ # CHECK: attribute 5, "rv32i2p1_smepmp1p0" .attribute arch, "rv32i_smrnmi1p0" -# CHECK: attribute 5, "rv32i2p1_smrnmid1p0" +# CHECK: attribute 5, "rv32i2p1_smrnmi1p0" .attribute arch, "rv32i_ssccfg1p0" # CHECK: attribute 5, "rv32i2p1_ssccfg1p0" From 769d3955a246acb0a85b4ac52c1fe17493c758e7 Mon Sep 17 00:00:00 2001 From: dong-miao <601183878@qq.com> Date: Thu, 24 Oct 2024 14:56:56 +0800 Subject: [PATCH 25/25] Update print-supported-extensions-riscv.c --- clang/test/Driver/print-supported-extensions-riscv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index a39c1ab36b1db..65375b79cb680 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -120,6 +120,7 @@ // CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level) // CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level) // CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection) +// CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts) // CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension) // CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level) // CHECK-NEXT: ssccfg 1.0 'Ssccfg' (Counter Configuration Supervisor Level)