[AArch64][SVE] can improve vector constant generation with SVE's INDEX instruction

[k-arrows]

GCC has implemented this in a recent patch. Consider the following example.
https://godbolt.org/z/szzTesvKz

#include <arm_sve.h>

typedef int v4si __attribute__ ((vector_size (16)));
v4si
f_v4si (void)
{
  return (v4si){ 0, 1, 2, 3 };
}

GCC:

f_v4si():
        index   z0.s, #0, #1
        ret

Clang:

.LCPI0_0:
        .word   0
        .word   1
        .word   2
        .word   3
f_v4si():
        adrp    x8, .LCPI0_0
        ldr     q0, [x8, :lo12:.LCPI0_0]
        ret

I referred to the following GCC patch.
INDEX

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: None (k-arrows)

GCC has implemented this in a recent patch. Consider the following example. https://godbolt.org/z/szzTesvKz ```cpp #include <arm_sve.h>

typedef int v4si attribute ((vector_size (16)));
v4si
f_v4si (void)
{
return (v4si){ 0, 1, 2, 3 };
}

GCC:
```asm
f_v4si():
        index   z0.s, #<!-- -->0, #<!-- -->1
        ret

Clang:

.LCPI0_0:
        .word   0
        .word   1
        .word   2
        .word   3
f_v4si():
        adrp    x8, .LCPI0_0
        ldr     q0, [x8, :lo12:.LCPI0_0]
        ret

I referred to the following GCC patch.
INDEX