From aa24da5a5ff4e4e05e40333f10149fada5e67042 Mon Sep 17 00:00:00 2001 From: Ronan Keryell Date: Wed, 6 Mar 2024 16:02:28 -0800 Subject: [PATCH] Mention other projects and manuals about AIE1 & AIE2 CGRA --- README.rst | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/README.rst b/README.rst index f266f320..5567ff2c 100644 --- a/README.rst +++ b/README.rst @@ -139,6 +139,36 @@ as the Ryzen 9 7940HS has an AIE-ML/AIE2 as the XDNA/NPU/IPU. ``_ and the compiler for device support is https://github.com/triSYCL/sycl +Other open-source projects related to AIE which are interesting to program AIE: + +- https://riallto.ai + +- https://github.com/Xilinx/mlir-aie + +- https://github.com/Xilinx/mlir-air + +- https://github.com/nod-ai/iree-amd-aie + +Some documentation about AMD AIE CGRA: +- AIE aka AIE1 + + - Versal Adaptive SoC AI Engine Architecture Manual + https://docs.xilinx.com/r/en-US/am009-versal-ai-engine/Overview + + - Versal Adaptive SoC Technical Reference Manual + https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Introduction + + - AIE/AIE1 C++ API + https://www.xilinx.com/htmldocs/xilinx2023_2/aiengine_api/aie_api/doc/index.html + +- AIE-ML aka AIE2 + + - AIE2/AIE-ML architecture + https://docs.xilinx.com/r/en-US/am020-versal-aie-ml/Overview + + - AIE2/AIE-ML C++ API + https://www.xilinx.com/htmldocs/xilinx2023_2/aiengine_ml_intrinsics/intrinsics/ + Documentation -------------