From 6d57ffc6278b58e8b1902eb2e127c39441bb7966 Mon Sep 17 00:00:00 2001 From: Ronan Keryell Date: Mon, 21 Oct 2024 11:50:57 -0700 Subject: [PATCH] Fix semantics bug detected by clang++-20 Also removed redundant template. --- include/triSYCL/vendor/Xilinx/acap/aie/hardware.hpp | 4 ++-- tests/acap/cascade_pipeliner.cpp | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/include/triSYCL/vendor/Xilinx/acap/aie/hardware.hpp b/include/triSYCL/vendor/Xilinx/acap/aie/hardware.hpp index dd22ae76..b5701859 100644 --- a/include/triSYCL/vendor/Xilinx/acap/aie/hardware.hpp +++ b/include/triSYCL/vendor/Xilinx/acap/aie/hardware.hpp @@ -307,9 +307,9 @@ struct dev_ptr { dev_ptr operator-(std::ptrdiff_t off) { return {add(ptr, -off)}; } std::ptrdiff_t operator-(dev_ptr other) { return ptr - other.ptr; } dev_ptr& operator++() { ptr = add(ptr, 1); return *this; } - dev_ptr operator++(int) { dev_ptr old = *this; *this++; return old; } + dev_ptr operator++(int) { dev_ptr old = *this; (*this)++; return old; } dev_ptr& operator--() { ptr = add(ptr, -1); return *this; } - dev_ptr operator--(int) { dev_ptr old = *this; *this--; return old; } + dev_ptr operator--(int) { dev_ptr old = *this; (*this)--; return old; } /// Pointer comparaison bool operator==(dev_ptr other) const { return ptr == other.ptr; } diff --git a/tests/acap/cascade_pipeliner.cpp b/tests/acap/cascade_pipeliner.cpp index a6a1c167..469eb091 100644 --- a/tests/acap/cascade_pipeliner.cpp +++ b/tests/acap/cascade_pipeliner.cpp @@ -7,8 +7,6 @@ #include #include -#include -#include #include #include @@ -99,11 +97,11 @@ struct cascade_executor { auto get_executor() { // AIE NoC connection between shim and input of the pipeline - d.template connect(port::shim { 0, 0 }, port::tile { 0, 0, 0 }); + d.connect(port::shim { 0, 0 }, port::tile { 0, 0, 0 }); // AIE NoC connection between output of the pipeline and the shim auto last_x = decltype(d)::geo::cascade_linear_x(last_stage); auto last_y = decltype(d)::geo::cascade_linear_y(last_stage); - d.template connect(port::tile { last_x, last_y, 0 }, + d.connect(port::tile { last_x, last_y, 0 }, port::shim { 1, 0 }); return [&] (FirstT input) { d.shim(0).bli_out(0) << input;