diff --git a/CHANGELOG.md b/CHANGELOG.md index e21b5cf..4f55ab2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -9,6 +9,9 @@ All notable changes to this project will be documented in this file. - **BREAKING** Remove typenum dependency, and use const generics. Requires at least Rust 1.51. +- **BREAKING** the GPIO `Pin` trait is now generic over the GPIO module. + A const generic replaces the associated type `Module`. + - **BREAKING** rename feature flags and module: `"imxrt106x" => "imxrt1060"` For rational on this change, see @@ -25,8 +28,10 @@ All notable changes to this project will be documented in this file. - etc. - **BREAKING** in the ADC module, we remove the `ADC` trait. Users should - replace usages of `adc::ADC` with `consts::Unsigned`. The `Adc1` and `Adc2` - types are now aliases for `U1` and `U2`. + replace usages of `adc::ADC` with constants that indicate ADC1, ADC2, etc. + + `gpio::Pin` is no longer a trait bound for the `adc::Pin` trait. Users who + relied on this guarantee should explicitly require the bound. `adc::Pin::INPUT` is now an associated `u32` constant, not a type. Cast the `u32` as needed for your implementation. See the before and after below for @@ -61,6 +66,18 @@ All notable changes to this project will be documented in this file. - Add uSDHC pin traits. - Add select uSDHC pins for the i.MX RT 1060. +- Basic i.MX RT 1170 support with the `"imxrt1170"` feature. Includes minimal + pad implementations for + + - LPI2C + - LPSPI + - LPUART + - FlexPWM + + that are sufficient for evaluating the 1170EVK. + +- Add CCM clock output pin trait with 1010, 1170 implementations. + ## [0.1.5] - 2022-01-01 ### Added diff --git a/Cargo.toml b/Cargo.toml index 38c3c7a..1bf0555 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,6 +13,7 @@ keywords = ["imxrt", "nxp", "embedded", "no_std"] categories = ["embedded", "no-std"] [features] +imxrt1170 = [] imxrt1060 = [] imxrt1010 = [] diff --git a/daisy.py b/daisy.py index 674b487..450dc5c 100755 --- a/daisy.py +++ b/daisy.py @@ -13,10 +13,7 @@ import xml.etree.ElementTree as ET -def daisy_constant(path): - tree = ET.parse(path) - root = tree.getroot() - iomuxc = root.find("./peripherals/peripheral[name='IOMUXC']") +def daisy_constant(iomuxc): base_address = int(iomuxc.find("./baseAddress").text, 16) for register in iomuxc.findall("./registers/register"): @@ -35,7 +32,18 @@ def daisy_constant(path): print(constant) +def search_iomuxces(path): + tree = ET.parse(path) + root = tree.getroot() + iomuxc = root.find("./peripherals/peripheral[name='IOMUXC']") + iomuxc_lpsr = root.find("./peripherals/peripheral[name='IOMUXC_LPSR']") + + if iomuxc: + daisy_constant(iomuxc) + if iomuxc_lpsr: + daisy_constant(iomuxc_lpsr) + if __name__ == "__main__": import sys - daisy_constant(sys.argv[1]) + search_iomuxces(sys.argv[1]) diff --git a/iomuxc.py b/iomuxc.py index ff403f2..0dcc743 100755 --- a/iomuxc.py +++ b/iomuxc.py @@ -33,10 +33,23 @@ /// /// See `ErasedPads` for more information.""" -def iomuxc(path): - tree = ET.parse(path) - root = tree.getroot() - iomuxc = root.find("./peripherals/peripheral[name='IOMUXC']") + +class GpioImpl: + """A pad's GPIO implementation.""" + + __slots__ = [ + "alt", + "module", + "offset", + ] + + def __init__(self, alt, module, offset): + self.alt = alt + self.module = module + self.offset = offset + + +def extract_pads(iomuxc): base_address = int(iomuxc.find("./baseAddress").text, 16) # Collect MUX and PAD absolute register addresses. @@ -69,13 +82,21 @@ def iomuxc(path): [gpio_offset] = re.findall("\d+", gpio_text) gpio_module = 1 gpio_offset = int(gpio_offset) + # But wait! The 1176 SVD has a third form, "GPIO_MUXx_IOyz", + # which is mixed with the first form... + elif gpio_match := re.search("GPIO_MUX\d_IO\d", desc): + gpio_text = gpio_match.group(0) + [gpio_module, gpio_offset] = re.findall("\d+", gpio_text) + gpio_module = int(gpio_module) + gpio_offset = int(gpio_offset) else: # There's no (expected) GPIO alt. This path is handled # later during code generation. continue - pads[name]["GPIO_ALT"] = alt_value = int(alt.find("./value").text, 16) - pads[name]["GPIO_MODULE"] = gpio_module - pads[name]["GPIO_OFFSET"] = gpio_offset + alt_value = int(alt.find("./value").text, 16) + gpio_impls = pads[name].get("GPIO", []) + gpio_impls.append(GpioImpl(alt_value, gpio_module, gpio_offset)) + pads[name]["GPIO"] = gpio_impls elif "SW_PAD_CTL_PAD_" in name: name = name.replace("SW_PAD_CTL_PAD_", "") @@ -84,12 +105,25 @@ def iomuxc(path): # Sanity check. for name, registers in pads.items(): - assert("PAD" in registers and "MUX" in registers) + assert "PAD" in registers and "MUX" in registers + + return pads + + +def iomuxc(path): + tree = ET.parse(path) + root = tree.getroot() + iomuxc = root.find("./peripherals/peripheral[name='IOMUXC']") + iomuxc_lpsr = root.find("./peripherals/peripheral[name='IOMUXC_LPSR']") + + pads = extract_pads(iomuxc) + if iomuxc_lpsr: + pads |= extract_pads(iomuxc_lpsr) # Create pad groups. groups = defaultdict(list) for name in pads.keys(): - group = name[:-len("_01")] + group = name[: -len("_01")] groups[group].append(name) # Generate Rust modules @@ -115,22 +149,21 @@ def iomuxc(path): print(f"pub type {pad_name} = crate::Pad<{mux_reg_name}, {pad_reg_name}>;") # impl gpio::Pin - if "GPIO_ALT" in registers: + for gpio_impl in registers.get("GPIO", []): print() - print(f"impl crate::gpio::Pin for {pad_name} {{") - print(f"const ALT: u32 = {registers['GPIO_ALT']};") - print(f"type Module = crate::consts::U{registers['GPIO_MODULE']};") - print(f"type Offset = crate::consts::U{registers['GPIO_OFFSET']};") + print(f"impl crate::gpio::Pin<{gpio_impl.module}> for {pad_name} {{") + print(f"const ALT: u32 = {gpio_impl.alt};") + print(f"const OFFSET: u32 = {gpio_impl.offset};") print("}") - else: - print(f"// {pad_name} does not have a GPIO alternate.") + if registers.get("GPIO") is None: + print(f"// {pad_name} does not have any GPIO alternates.") print() # Pads struct print(f"/// All pads with prefix {group}.") print("pub struct Pads {") for pad_name in pad_names: - pad_number = pad_name[-len("01"):] + pad_number = pad_name[-len("01") :] print(f"pub p{pad_number}: {pad_name},") print("}") @@ -146,14 +179,14 @@ def iomuxc(path): print(NEW_DOCSTRING) print("#[inline] pub const unsafe fn new() -> Self { Self {") for pad_name in pad_names: - pad_number = pad_name[-len("01"):] + pad_number = pad_name[-len("01") :] print(f"p{pad_number}: {pad_name}::new(),") print("} }") print(ERASE_DOCSTRING) print("#[inline] pub const fn erase(self) -> ErasedPads { [") for pad_name in sorted(pad_names): - pad_number = pad_name[-len("01"):] + pad_number = pad_name[-len("01") :] print(f"self.p{pad_number}.erase(),") print("] }") print("}") @@ -167,6 +200,7 @@ def iomuxc(path): for group in groups.keys(): print(f"pub {group.lower()}: {group.lower()}::Pads,") print("}") + print() print("impl Pads {") print(NEW_DOCSTRING) @@ -180,6 +214,7 @@ def iomuxc(path): print(f"{group.lower()}: self.{group.lower()}.erase(),") print("} }") print("}") + print() # Generate top-level ErasedPads struct print("/// All erased pads.") @@ -188,5 +223,6 @@ def iomuxc(path): print(f"pub {group.lower()}: {group.lower()}::ErasedPads,") print("}") + if __name__ == "__main__": iomuxc(sys.argv[1]) diff --git a/src/adc.rs b/src/adc.rs index 5dfd9d2..df34c09 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,18 +1,13 @@ //! ADC pad configuration -use crate::consts::Unsigned; - -/// Type number for ADC1 -pub type Adc1 = crate::consts::U1; -/// Type number for ADC2 -pub type Adc2 = crate::consts::U2; +pub const ADC1: u8 = 1; +pub const ADC2: u8 = 2; /// Describes an ADC input pin /// -/// ADC pins are specialized GPIO pins. Some pads may be used in both `Adc1` -/// and `Adc2`, so implementations will indicate their compatibility by -/// supplying an identifier in place of `ADCx`. -pub trait Pin: super::gpio::Pin { +/// Some pads may be used in both `ADC1` and `ADC2`, so implementations +/// indicate their compatibility by supplying a constant `N`. +pub trait Pin: super::Iomuxc { /// The input pin identifier /// /// Starts at `0`, and increments up. @@ -23,18 +18,21 @@ pub trait Pin: super::gpio::Pin { /// /// Due to a requirement in the ADC module, `prepare` will disable the pull/keeper /// on the pin. The configuration change will not affect any other settings. -pub fn prepare>(pin: &mut P) { +pub fn prepare, const N: u8>(pin: &mut P) { // See the note in the ADC section of the reference manual // (using iMXRT1060, rev 2). ADC input signals connect to // GPIO, and we need to disable the keeper to prevent signal // jumps. - super::alternate(pin,

::ALT); super::configure(pin, super::Config::modify().set_pull_keeper(None)); + // Not putting the ADC into the GPIO alternate. Reference + // manuals indicate that the alt (mode) doesn't matter. We're + // expecting that the GPIO input path is implicit, regardless + // of the alt. } #[allow(unused)] // Used in chip-specific modules... macro_rules! adc { - (module: $module:ty, pad: $pad:ty, input: $input:expr) => { + (module: $module:expr, pad: $pad:ty, input: $input:expr) => { impl Pin<$module> for $pad { const INPUT: u32 = $input; } diff --git a/src/imxrt1010/mod.rs b/src/imxrt1010/mod.rs index cf144e5..13a7bc1 100644 --- a/src/imxrt1010/mod.rs +++ b/src/imxrt1010/mod.rs @@ -95,3 +95,16 @@ mod lpuart; mod pads; pub use pads::*; + +mod ccm { + pub use crate::ccm::{Function, Observable, Pin}; + + impl Pin for super::pads::gpio_sd::GPIO_SD_02 { + const ALT: u32 = 3; + type Function = Observable<1>; + } + impl Pin for super::pads::gpio_sd::GPIO_SD_01 { + const ALT: u32 = 3; + type Function = Observable<2>; + } +} diff --git a/src/imxrt1010/pads.rs b/src/imxrt1010/pads.rs index c5153bd..44bc84f 100644 --- a/src/imxrt1010/pads.rs +++ b/src/imxrt1010/pads.rs @@ -8,150 +8,135 @@ pub mod gpio_ad { const GPIO_AD_14_PAD_ADDR: u32 = 0x401f80c0; pub type GPIO_AD_14 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_14 { + impl crate::gpio::Pin<1> for GPIO_AD_14 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U28; + const OFFSET: u32 = 28; } const GPIO_AD_13_MUX_ADDR: u32 = 0x401f8014; const GPIO_AD_13_PAD_ADDR: u32 = 0x401f80c4; pub type GPIO_AD_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_13 { + impl crate::gpio::Pin<1> for GPIO_AD_13 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U27; + const OFFSET: u32 = 27; } const GPIO_AD_12_MUX_ADDR: u32 = 0x401f8018; const GPIO_AD_12_PAD_ADDR: u32 = 0x401f80c8; pub type GPIO_AD_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_12 { + impl crate::gpio::Pin<1> for GPIO_AD_12 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U26; + const OFFSET: u32 = 26; } const GPIO_AD_11_MUX_ADDR: u32 = 0x401f801c; const GPIO_AD_11_PAD_ADDR: u32 = 0x401f80cc; pub type GPIO_AD_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_11 { + impl crate::gpio::Pin<1> for GPIO_AD_11 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U25; + const OFFSET: u32 = 25; } const GPIO_AD_10_MUX_ADDR: u32 = 0x401f8020; const GPIO_AD_10_PAD_ADDR: u32 = 0x401f80d0; pub type GPIO_AD_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_10 { + impl crate::gpio::Pin<1> for GPIO_AD_10 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U24; + const OFFSET: u32 = 24; } const GPIO_AD_09_MUX_ADDR: u32 = 0x401f8024; const GPIO_AD_09_PAD_ADDR: u32 = 0x401f80d4; pub type GPIO_AD_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_09 { + impl crate::gpio::Pin<1> for GPIO_AD_09 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U23; + const OFFSET: u32 = 23; } const GPIO_AD_08_MUX_ADDR: u32 = 0x401f8028; const GPIO_AD_08_PAD_ADDR: u32 = 0x401f80d8; pub type GPIO_AD_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_08 { + impl crate::gpio::Pin<1> for GPIO_AD_08 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U22; + const OFFSET: u32 = 22; } const GPIO_AD_07_MUX_ADDR: u32 = 0x401f802c; const GPIO_AD_07_PAD_ADDR: u32 = 0x401f80dc; pub type GPIO_AD_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_07 { + impl crate::gpio::Pin<1> for GPIO_AD_07 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U21; + const OFFSET: u32 = 21; } const GPIO_AD_06_MUX_ADDR: u32 = 0x401f8030; const GPIO_AD_06_PAD_ADDR: u32 = 0x401f80e0; pub type GPIO_AD_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_06 { + impl crate::gpio::Pin<1> for GPIO_AD_06 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U20; + const OFFSET: u32 = 20; } const GPIO_AD_05_MUX_ADDR: u32 = 0x401f8034; const GPIO_AD_05_PAD_ADDR: u32 = 0x401f80e4; pub type GPIO_AD_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_05 { + impl crate::gpio::Pin<1> for GPIO_AD_05 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U19; + const OFFSET: u32 = 19; } const GPIO_AD_04_MUX_ADDR: u32 = 0x401f8038; const GPIO_AD_04_PAD_ADDR: u32 = 0x401f80e8; pub type GPIO_AD_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_04 { + impl crate::gpio::Pin<1> for GPIO_AD_04 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U18; + const OFFSET: u32 = 18; } const GPIO_AD_03_MUX_ADDR: u32 = 0x401f803c; const GPIO_AD_03_PAD_ADDR: u32 = 0x401f80ec; pub type GPIO_AD_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_03 { + impl crate::gpio::Pin<1> for GPIO_AD_03 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U17; + const OFFSET: u32 = 17; } const GPIO_AD_02_MUX_ADDR: u32 = 0x401f8040; const GPIO_AD_02_PAD_ADDR: u32 = 0x401f80f0; pub type GPIO_AD_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_02 { + impl crate::gpio::Pin<1> for GPIO_AD_02 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U16; + const OFFSET: u32 = 16; } const GPIO_AD_01_MUX_ADDR: u32 = 0x401f8044; const GPIO_AD_01_PAD_ADDR: u32 = 0x401f80f4; pub type GPIO_AD_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_01 { + impl crate::gpio::Pin<1> for GPIO_AD_01 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U15; + const OFFSET: u32 = 15; } const GPIO_AD_00_MUX_ADDR: u32 = 0x401f8048; const GPIO_AD_00_PAD_ADDR: u32 = 0x401f80f8; pub type GPIO_AD_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_00 { + impl crate::gpio::Pin<1> for GPIO_AD_00 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U14; + const OFFSET: u32 = 14; } /// All pads with prefix GPIO_AD. @@ -241,146 +226,132 @@ pub mod gpio_sd { const GPIO_SD_14_MUX_ADDR: u32 = 0x401f804c; const GPIO_SD_14_PAD_ADDR: u32 = 0x401f80fc; pub type GPIO_SD_14 = crate::Pad; - // GPIO_SD_14 does not have a GPIO alternate. + // GPIO_SD_14 does not have any GPIO alternates. const GPIO_SD_13_MUX_ADDR: u32 = 0x401f8050; const GPIO_SD_13_PAD_ADDR: u32 = 0x401f8100; pub type GPIO_SD_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_13 { + impl crate::gpio::Pin<2> for GPIO_SD_13 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U13; + const OFFSET: u32 = 13; } const GPIO_SD_12_MUX_ADDR: u32 = 0x401f8054; const GPIO_SD_12_PAD_ADDR: u32 = 0x401f8104; pub type GPIO_SD_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_12 { + impl crate::gpio::Pin<2> for GPIO_SD_12 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U12; + const OFFSET: u32 = 12; } const GPIO_SD_11_MUX_ADDR: u32 = 0x401f8058; const GPIO_SD_11_PAD_ADDR: u32 = 0x401f8108; pub type GPIO_SD_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_11 { + impl crate::gpio::Pin<2> for GPIO_SD_11 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U11; + const OFFSET: u32 = 11; } const GPIO_SD_10_MUX_ADDR: u32 = 0x401f805c; const GPIO_SD_10_PAD_ADDR: u32 = 0x401f810c; pub type GPIO_SD_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_10 { + impl crate::gpio::Pin<2> for GPIO_SD_10 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U10; + const OFFSET: u32 = 10; } const GPIO_SD_09_MUX_ADDR: u32 = 0x401f8060; const GPIO_SD_09_PAD_ADDR: u32 = 0x401f8110; pub type GPIO_SD_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_09 { + impl crate::gpio::Pin<2> for GPIO_SD_09 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U9; + const OFFSET: u32 = 9; } const GPIO_SD_08_MUX_ADDR: u32 = 0x401f8064; const GPIO_SD_08_PAD_ADDR: u32 = 0x401f8114; pub type GPIO_SD_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_08 { + impl crate::gpio::Pin<2> for GPIO_SD_08 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U8; + const OFFSET: u32 = 8; } const GPIO_SD_07_MUX_ADDR: u32 = 0x401f8068; const GPIO_SD_07_PAD_ADDR: u32 = 0x401f8118; pub type GPIO_SD_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_07 { + impl crate::gpio::Pin<2> for GPIO_SD_07 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U7; + const OFFSET: u32 = 7; } const GPIO_SD_06_MUX_ADDR: u32 = 0x401f806c; const GPIO_SD_06_PAD_ADDR: u32 = 0x401f811c; pub type GPIO_SD_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_06 { + impl crate::gpio::Pin<2> for GPIO_SD_06 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U6; + const OFFSET: u32 = 6; } const GPIO_SD_05_MUX_ADDR: u32 = 0x401f8070; const GPIO_SD_05_PAD_ADDR: u32 = 0x401f8120; pub type GPIO_SD_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_05 { + impl crate::gpio::Pin<2> for GPIO_SD_05 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U5; + const OFFSET: u32 = 5; } const GPIO_SD_04_MUX_ADDR: u32 = 0x401f8074; const GPIO_SD_04_PAD_ADDR: u32 = 0x401f8124; pub type GPIO_SD_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_04 { + impl crate::gpio::Pin<2> for GPIO_SD_04 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U4; + const OFFSET: u32 = 4; } const GPIO_SD_03_MUX_ADDR: u32 = 0x401f8078; const GPIO_SD_03_PAD_ADDR: u32 = 0x401f8128; pub type GPIO_SD_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_03 { + impl crate::gpio::Pin<2> for GPIO_SD_03 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U3; + const OFFSET: u32 = 3; } const GPIO_SD_02_MUX_ADDR: u32 = 0x401f807c; const GPIO_SD_02_PAD_ADDR: u32 = 0x401f812c; pub type GPIO_SD_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_02 { + impl crate::gpio::Pin<2> for GPIO_SD_02 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U2; + const OFFSET: u32 = 2; } const GPIO_SD_01_MUX_ADDR: u32 = 0x401f8080; const GPIO_SD_01_PAD_ADDR: u32 = 0x401f8130; pub type GPIO_SD_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_01 { + impl crate::gpio::Pin<2> for GPIO_SD_01 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U1; + const OFFSET: u32 = 1; } const GPIO_SD_00_MUX_ADDR: u32 = 0x401f8084; const GPIO_SD_00_PAD_ADDR: u32 = 0x401f8134; pub type GPIO_SD_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_00 { + impl crate::gpio::Pin<2> for GPIO_SD_00 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U0; + const OFFSET: u32 = 0; } /// All pads with prefix GPIO_SD. @@ -471,140 +442,126 @@ pub mod gpio { const GPIO_13_PAD_ADDR: u32 = 0x401f8138; pub type GPIO_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_13 { + impl crate::gpio::Pin<1> for GPIO_13 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U13; + const OFFSET: u32 = 13; } const GPIO_12_MUX_ADDR: u32 = 0x401f808c; const GPIO_12_PAD_ADDR: u32 = 0x401f813c; pub type GPIO_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_12 { + impl crate::gpio::Pin<1> for GPIO_12 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U12; + const OFFSET: u32 = 12; } const GPIO_11_MUX_ADDR: u32 = 0x401f8090; const GPIO_11_PAD_ADDR: u32 = 0x401f8140; pub type GPIO_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_11 { + impl crate::gpio::Pin<1> for GPIO_11 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U11; + const OFFSET: u32 = 11; } const GPIO_10_MUX_ADDR: u32 = 0x401f8094; const GPIO_10_PAD_ADDR: u32 = 0x401f8144; pub type GPIO_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_10 { + impl crate::gpio::Pin<1> for GPIO_10 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U10; + const OFFSET: u32 = 10; } const GPIO_09_MUX_ADDR: u32 = 0x401f8098; const GPIO_09_PAD_ADDR: u32 = 0x401f8148; pub type GPIO_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_09 { + impl crate::gpio::Pin<1> for GPIO_09 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U9; + const OFFSET: u32 = 9; } const GPIO_08_MUX_ADDR: u32 = 0x401f809c; const GPIO_08_PAD_ADDR: u32 = 0x401f814c; pub type GPIO_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_08 { + impl crate::gpio::Pin<1> for GPIO_08 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U8; + const OFFSET: u32 = 8; } const GPIO_07_MUX_ADDR: u32 = 0x401f80a0; const GPIO_07_PAD_ADDR: u32 = 0x401f8150; pub type GPIO_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_07 { + impl crate::gpio::Pin<1> for GPIO_07 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U7; + const OFFSET: u32 = 7; } const GPIO_06_MUX_ADDR: u32 = 0x401f80a4; const GPIO_06_PAD_ADDR: u32 = 0x401f8154; pub type GPIO_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_06 { + impl crate::gpio::Pin<1> for GPIO_06 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U6; + const OFFSET: u32 = 6; } const GPIO_05_MUX_ADDR: u32 = 0x401f80a8; const GPIO_05_PAD_ADDR: u32 = 0x401f8158; pub type GPIO_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_05 { + impl crate::gpio::Pin<1> for GPIO_05 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U5; + const OFFSET: u32 = 5; } const GPIO_04_MUX_ADDR: u32 = 0x401f80ac; const GPIO_04_PAD_ADDR: u32 = 0x401f815c; pub type GPIO_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_04 { + impl crate::gpio::Pin<1> for GPIO_04 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U4; + const OFFSET: u32 = 4; } const GPIO_03_MUX_ADDR: u32 = 0x401f80b0; const GPIO_03_PAD_ADDR: u32 = 0x401f8160; pub type GPIO_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_03 { + impl crate::gpio::Pin<1> for GPIO_03 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U3; + const OFFSET: u32 = 3; } const GPIO_02_MUX_ADDR: u32 = 0x401f80b4; const GPIO_02_PAD_ADDR: u32 = 0x401f8164; pub type GPIO_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_02 { + impl crate::gpio::Pin<1> for GPIO_02 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U2; + const OFFSET: u32 = 2; } const GPIO_01_MUX_ADDR: u32 = 0x401f80b8; const GPIO_01_PAD_ADDR: u32 = 0x401f8168; pub type GPIO_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_01 { + impl crate::gpio::Pin<1> for GPIO_01 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U1; + const OFFSET: u32 = 1; } const GPIO_00_MUX_ADDR: u32 = 0x401f80bc; const GPIO_00_PAD_ADDR: u32 = 0x401f816c; pub type GPIO_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_00 { + impl crate::gpio::Pin<1> for GPIO_00 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U0; + const OFFSET: u32 = 0; } /// All pads with prefix GPIO. @@ -691,6 +648,7 @@ pub struct Pads { pub gpio_sd: gpio_sd::Pads, pub gpio: gpio::Pads, } + impl Pads { /// Take all pads from this group /// @@ -724,6 +682,7 @@ impl Pads { } } } + /// All erased pads. pub struct ErasedPads { pub gpio_ad: gpio_ad::ErasedPads, diff --git a/src/imxrt1060/adc.rs b/src/imxrt1060/adc.rs index 920b0de..a0ae3c6 100644 --- a/src/imxrt1060/adc.rs +++ b/src/imxrt1060/adc.rs @@ -6,44 +6,44 @@ //! section of the reference manual. use super::{gpio_ad_b0::*, gpio_ad_b1::*}; -use crate::adc::{Adc1, Adc2, Pin}; +use crate::adc::Pin; // // Adc1 // -adc!(module: Adc1, pad: GPIO_AD_B1_11, input: 0); -adc!(module: Adc1, pad: GPIO_AD_B0_12, input: 1); -adc!(module: Adc1, pad: GPIO_AD_B0_13, input: 2); -adc!(module: Adc1, pad: GPIO_AD_B0_14, input: 3); -adc!(module: Adc1, pad: GPIO_AD_B0_15, input: 4); -adc!(module: Adc1, pad: GPIO_AD_B1_00, input: 5); -adc!(module: Adc1, pad: GPIO_AD_B1_01, input: 6); -adc!(module: Adc1, pad: GPIO_AD_B1_02, input: 7); -adc!(module: Adc1, pad: GPIO_AD_B1_03, input: 8); -adc!(module: Adc1, pad: GPIO_AD_B1_04, input: 9); -adc!(module: Adc1, pad: GPIO_AD_B1_05, input: 10); -adc!(module: Adc1, pad: GPIO_AD_B1_06, input: 11); -adc!(module: Adc1, pad: GPIO_AD_B1_07, input: 12); -adc!(module: Adc1, pad: GPIO_AD_B1_08, input: 13); -adc!(module: Adc1, pad: GPIO_AD_B1_09, input: 14); -adc!(module: Adc1, pad: GPIO_AD_B1_10, input: 15); +adc!(module: 1, pad: GPIO_AD_B1_11, input: 0); +adc!(module: 1, pad: GPIO_AD_B0_12, input: 1); +adc!(module: 1, pad: GPIO_AD_B0_13, input: 2); +adc!(module: 1, pad: GPIO_AD_B0_14, input: 3); +adc!(module: 1, pad: GPIO_AD_B0_15, input: 4); +adc!(module: 1, pad: GPIO_AD_B1_00, input: 5); +adc!(module: 1, pad: GPIO_AD_B1_01, input: 6); +adc!(module: 1, pad: GPIO_AD_B1_02, input: 7); +adc!(module: 1, pad: GPIO_AD_B1_03, input: 8); +adc!(module: 1, pad: GPIO_AD_B1_04, input: 9); +adc!(module: 1, pad: GPIO_AD_B1_05, input: 10); +adc!(module: 1, pad: GPIO_AD_B1_06, input: 11); +adc!(module: 1, pad: GPIO_AD_B1_07, input: 12); +adc!(module: 1, pad: GPIO_AD_B1_08, input: 13); +adc!(module: 1, pad: GPIO_AD_B1_09, input: 14); +adc!(module: 1, pad: GPIO_AD_B1_10, input: 15); // // Adc2 // -adc!(module: Adc2, pad: GPIO_AD_B1_11, input: 0); -adc!(module: Adc2, pad: GPIO_AD_B1_12, input: 1); -adc!(module: Adc2, pad: GPIO_AD_B1_13, input: 2); -adc!(module: Adc2, pad: GPIO_AD_B1_14, input: 3); -adc!(module: Adc2, pad: GPIO_AD_B1_15, input: 4); -adc!(module: Adc2, pad: GPIO_AD_B1_00, input: 5); -adc!(module: Adc2, pad: GPIO_AD_B1_01, input: 6); -adc!(module: Adc2, pad: GPIO_AD_B1_02, input: 7); -adc!(module: Adc2, pad: GPIO_AD_B1_03, input: 8); -adc!(module: Adc2, pad: GPIO_AD_B1_04, input: 9); -adc!(module: Adc2, pad: GPIO_AD_B1_05, input: 10); -adc!(module: Adc2, pad: GPIO_AD_B1_06, input: 11); -adc!(module: Adc2, pad: GPIO_AD_B1_07, input: 12); -adc!(module: Adc2, pad: GPIO_AD_B1_08, input: 13); -adc!(module: Adc2, pad: GPIO_AD_B1_09, input: 14); -adc!(module: Adc2, pad: GPIO_AD_B1_10, input: 15); +adc!(module: 2, pad: GPIO_AD_B1_11, input: 0); +adc!(module: 2, pad: GPIO_AD_B1_12, input: 1); +adc!(module: 2, pad: GPIO_AD_B1_13, input: 2); +adc!(module: 2, pad: GPIO_AD_B1_14, input: 3); +adc!(module: 2, pad: GPIO_AD_B1_15, input: 4); +adc!(module: 2, pad: GPIO_AD_B1_00, input: 5); +adc!(module: 2, pad: GPIO_AD_B1_01, input: 6); +adc!(module: 2, pad: GPIO_AD_B1_02, input: 7); +adc!(module: 2, pad: GPIO_AD_B1_03, input: 8); +adc!(module: 2, pad: GPIO_AD_B1_04, input: 9); +adc!(module: 2, pad: GPIO_AD_B1_05, input: 10); +adc!(module: 2, pad: GPIO_AD_B1_06, input: 11); +adc!(module: 2, pad: GPIO_AD_B1_07, input: 12); +adc!(module: 2, pad: GPIO_AD_B1_08, input: 13); +adc!(module: 2, pad: GPIO_AD_B1_09, input: 14); +adc!(module: 2, pad: GPIO_AD_B1_10, input: 15); diff --git a/src/imxrt1060/pads.rs b/src/imxrt1060/pads.rs index d3e8555..667aad3 100644 --- a/src/imxrt1060/pads.rs +++ b/src/imxrt1060/pads.rs @@ -8,420 +8,378 @@ pub mod gpio_emc { const GPIO_EMC_00_PAD_ADDR: u32 = 0x401f8204; pub type GPIO_EMC_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_00 { + impl crate::gpio::Pin<4> for GPIO_EMC_00 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U0; + const OFFSET: u32 = 0; } const GPIO_EMC_01_MUX_ADDR: u32 = 0x401f8018; const GPIO_EMC_01_PAD_ADDR: u32 = 0x401f8208; pub type GPIO_EMC_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_01 { + impl crate::gpio::Pin<4> for GPIO_EMC_01 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U1; + const OFFSET: u32 = 1; } const GPIO_EMC_02_MUX_ADDR: u32 = 0x401f801c; const GPIO_EMC_02_PAD_ADDR: u32 = 0x401f820c; pub type GPIO_EMC_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_02 { + impl crate::gpio::Pin<4> for GPIO_EMC_02 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U2; + const OFFSET: u32 = 2; } const GPIO_EMC_03_MUX_ADDR: u32 = 0x401f8020; const GPIO_EMC_03_PAD_ADDR: u32 = 0x401f8210; pub type GPIO_EMC_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_03 { + impl crate::gpio::Pin<4> for GPIO_EMC_03 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U3; + const OFFSET: u32 = 3; } const GPIO_EMC_04_MUX_ADDR: u32 = 0x401f8024; const GPIO_EMC_04_PAD_ADDR: u32 = 0x401f8214; pub type GPIO_EMC_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_04 { + impl crate::gpio::Pin<4> for GPIO_EMC_04 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U4; + const OFFSET: u32 = 4; } const GPIO_EMC_05_MUX_ADDR: u32 = 0x401f8028; const GPIO_EMC_05_PAD_ADDR: u32 = 0x401f8218; pub type GPIO_EMC_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_05 { + impl crate::gpio::Pin<4> for GPIO_EMC_05 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U5; + const OFFSET: u32 = 5; } const GPIO_EMC_06_MUX_ADDR: u32 = 0x401f802c; const GPIO_EMC_06_PAD_ADDR: u32 = 0x401f821c; pub type GPIO_EMC_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_06 { + impl crate::gpio::Pin<4> for GPIO_EMC_06 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U6; + const OFFSET: u32 = 6; } const GPIO_EMC_07_MUX_ADDR: u32 = 0x401f8030; const GPIO_EMC_07_PAD_ADDR: u32 = 0x401f8220; pub type GPIO_EMC_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_07 { + impl crate::gpio::Pin<4> for GPIO_EMC_07 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U7; + const OFFSET: u32 = 7; } const GPIO_EMC_08_MUX_ADDR: u32 = 0x401f8034; const GPIO_EMC_08_PAD_ADDR: u32 = 0x401f8224; pub type GPIO_EMC_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_08 { + impl crate::gpio::Pin<4> for GPIO_EMC_08 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U8; + const OFFSET: u32 = 8; } const GPIO_EMC_09_MUX_ADDR: u32 = 0x401f8038; const GPIO_EMC_09_PAD_ADDR: u32 = 0x401f8228; pub type GPIO_EMC_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_09 { + impl crate::gpio::Pin<4> for GPIO_EMC_09 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U9; + const OFFSET: u32 = 9; } const GPIO_EMC_10_MUX_ADDR: u32 = 0x401f803c; const GPIO_EMC_10_PAD_ADDR: u32 = 0x401f822c; pub type GPIO_EMC_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_10 { + impl crate::gpio::Pin<4> for GPIO_EMC_10 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U10; + const OFFSET: u32 = 10; } const GPIO_EMC_11_MUX_ADDR: u32 = 0x401f8040; const GPIO_EMC_11_PAD_ADDR: u32 = 0x401f8230; pub type GPIO_EMC_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_11 { + impl crate::gpio::Pin<4> for GPIO_EMC_11 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U11; + const OFFSET: u32 = 11; } const GPIO_EMC_12_MUX_ADDR: u32 = 0x401f8044; const GPIO_EMC_12_PAD_ADDR: u32 = 0x401f8234; pub type GPIO_EMC_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_12 { + impl crate::gpio::Pin<4> for GPIO_EMC_12 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U12; + const OFFSET: u32 = 12; } const GPIO_EMC_13_MUX_ADDR: u32 = 0x401f8048; const GPIO_EMC_13_PAD_ADDR: u32 = 0x401f8238; pub type GPIO_EMC_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_13 { + impl crate::gpio::Pin<4> for GPIO_EMC_13 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U13; + const OFFSET: u32 = 13; } const GPIO_EMC_14_MUX_ADDR: u32 = 0x401f804c; const GPIO_EMC_14_PAD_ADDR: u32 = 0x401f823c; pub type GPIO_EMC_14 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_14 { + impl crate::gpio::Pin<4> for GPIO_EMC_14 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U14; + const OFFSET: u32 = 14; } const GPIO_EMC_15_MUX_ADDR: u32 = 0x401f8050; const GPIO_EMC_15_PAD_ADDR: u32 = 0x401f8240; pub type GPIO_EMC_15 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_15 { + impl crate::gpio::Pin<4> for GPIO_EMC_15 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U15; + const OFFSET: u32 = 15; } const GPIO_EMC_16_MUX_ADDR: u32 = 0x401f8054; const GPIO_EMC_16_PAD_ADDR: u32 = 0x401f8244; pub type GPIO_EMC_16 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_16 { + impl crate::gpio::Pin<4> for GPIO_EMC_16 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U16; + const OFFSET: u32 = 16; } const GPIO_EMC_17_MUX_ADDR: u32 = 0x401f8058; const GPIO_EMC_17_PAD_ADDR: u32 = 0x401f8248; pub type GPIO_EMC_17 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_17 { + impl crate::gpio::Pin<4> for GPIO_EMC_17 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U17; + const OFFSET: u32 = 17; } const GPIO_EMC_18_MUX_ADDR: u32 = 0x401f805c; const GPIO_EMC_18_PAD_ADDR: u32 = 0x401f824c; pub type GPIO_EMC_18 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_18 { + impl crate::gpio::Pin<4> for GPIO_EMC_18 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U18; + const OFFSET: u32 = 18; } const GPIO_EMC_19_MUX_ADDR: u32 = 0x401f8060; const GPIO_EMC_19_PAD_ADDR: u32 = 0x401f8250; pub type GPIO_EMC_19 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_19 { + impl crate::gpio::Pin<4> for GPIO_EMC_19 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U19; + const OFFSET: u32 = 19; } const GPIO_EMC_20_MUX_ADDR: u32 = 0x401f8064; const GPIO_EMC_20_PAD_ADDR: u32 = 0x401f8254; pub type GPIO_EMC_20 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_20 { + impl crate::gpio::Pin<4> for GPIO_EMC_20 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U20; + const OFFSET: u32 = 20; } const GPIO_EMC_21_MUX_ADDR: u32 = 0x401f8068; const GPIO_EMC_21_PAD_ADDR: u32 = 0x401f8258; pub type GPIO_EMC_21 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_21 { + impl crate::gpio::Pin<4> for GPIO_EMC_21 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U21; + const OFFSET: u32 = 21; } const GPIO_EMC_22_MUX_ADDR: u32 = 0x401f806c; const GPIO_EMC_22_PAD_ADDR: u32 = 0x401f825c; pub type GPIO_EMC_22 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_22 { + impl crate::gpio::Pin<4> for GPIO_EMC_22 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U22; + const OFFSET: u32 = 22; } const GPIO_EMC_23_MUX_ADDR: u32 = 0x401f8070; const GPIO_EMC_23_PAD_ADDR: u32 = 0x401f8260; pub type GPIO_EMC_23 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_23 { + impl crate::gpio::Pin<4> for GPIO_EMC_23 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U23; + const OFFSET: u32 = 23; } const GPIO_EMC_24_MUX_ADDR: u32 = 0x401f8074; const GPIO_EMC_24_PAD_ADDR: u32 = 0x401f8264; pub type GPIO_EMC_24 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_24 { + impl crate::gpio::Pin<4> for GPIO_EMC_24 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U24; + const OFFSET: u32 = 24; } const GPIO_EMC_25_MUX_ADDR: u32 = 0x401f8078; const GPIO_EMC_25_PAD_ADDR: u32 = 0x401f8268; pub type GPIO_EMC_25 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_25 { + impl crate::gpio::Pin<4> for GPIO_EMC_25 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U25; + const OFFSET: u32 = 25; } const GPIO_EMC_26_MUX_ADDR: u32 = 0x401f807c; const GPIO_EMC_26_PAD_ADDR: u32 = 0x401f826c; pub type GPIO_EMC_26 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_26 { + impl crate::gpio::Pin<4> for GPIO_EMC_26 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U26; + const OFFSET: u32 = 26; } const GPIO_EMC_27_MUX_ADDR: u32 = 0x401f8080; const GPIO_EMC_27_PAD_ADDR: u32 = 0x401f8270; pub type GPIO_EMC_27 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_27 { + impl crate::gpio::Pin<4> for GPIO_EMC_27 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U27; + const OFFSET: u32 = 27; } const GPIO_EMC_28_MUX_ADDR: u32 = 0x401f8084; const GPIO_EMC_28_PAD_ADDR: u32 = 0x401f8274; pub type GPIO_EMC_28 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_28 { + impl crate::gpio::Pin<4> for GPIO_EMC_28 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U28; + const OFFSET: u32 = 28; } const GPIO_EMC_29_MUX_ADDR: u32 = 0x401f8088; const GPIO_EMC_29_PAD_ADDR: u32 = 0x401f8278; pub type GPIO_EMC_29 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_29 { + impl crate::gpio::Pin<4> for GPIO_EMC_29 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U29; + const OFFSET: u32 = 29; } const GPIO_EMC_30_MUX_ADDR: u32 = 0x401f808c; const GPIO_EMC_30_PAD_ADDR: u32 = 0x401f827c; pub type GPIO_EMC_30 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_30 { + impl crate::gpio::Pin<4> for GPIO_EMC_30 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U30; + const OFFSET: u32 = 30; } const GPIO_EMC_31_MUX_ADDR: u32 = 0x401f8090; const GPIO_EMC_31_PAD_ADDR: u32 = 0x401f8280; pub type GPIO_EMC_31 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_31 { + impl crate::gpio::Pin<4> for GPIO_EMC_31 { const ALT: u32 = 5; - type Module = crate::consts::U4; - type Offset = crate::consts::U31; + const OFFSET: u32 = 31; } const GPIO_EMC_32_MUX_ADDR: u32 = 0x401f8094; const GPIO_EMC_32_PAD_ADDR: u32 = 0x401f8284; pub type GPIO_EMC_32 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_32 { + impl crate::gpio::Pin<3> for GPIO_EMC_32 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U18; + const OFFSET: u32 = 18; } const GPIO_EMC_33_MUX_ADDR: u32 = 0x401f8098; const GPIO_EMC_33_PAD_ADDR: u32 = 0x401f8288; pub type GPIO_EMC_33 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_33 { + impl crate::gpio::Pin<3> for GPIO_EMC_33 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U19; + const OFFSET: u32 = 19; } const GPIO_EMC_34_MUX_ADDR: u32 = 0x401f809c; const GPIO_EMC_34_PAD_ADDR: u32 = 0x401f828c; pub type GPIO_EMC_34 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_34 { + impl crate::gpio::Pin<3> for GPIO_EMC_34 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U20; + const OFFSET: u32 = 20; } const GPIO_EMC_35_MUX_ADDR: u32 = 0x401f80a0; const GPIO_EMC_35_PAD_ADDR: u32 = 0x401f8290; pub type GPIO_EMC_35 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_35 { + impl crate::gpio::Pin<3> for GPIO_EMC_35 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U21; + const OFFSET: u32 = 21; } const GPIO_EMC_36_MUX_ADDR: u32 = 0x401f80a4; const GPIO_EMC_36_PAD_ADDR: u32 = 0x401f8294; pub type GPIO_EMC_36 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_36 { + impl crate::gpio::Pin<3> for GPIO_EMC_36 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U22; + const OFFSET: u32 = 22; } const GPIO_EMC_37_MUX_ADDR: u32 = 0x401f80a8; const GPIO_EMC_37_PAD_ADDR: u32 = 0x401f8298; pub type GPIO_EMC_37 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_37 { + impl crate::gpio::Pin<3> for GPIO_EMC_37 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U23; + const OFFSET: u32 = 23; } const GPIO_EMC_38_MUX_ADDR: u32 = 0x401f80ac; const GPIO_EMC_38_PAD_ADDR: u32 = 0x401f829c; pub type GPIO_EMC_38 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_38 { + impl crate::gpio::Pin<3> for GPIO_EMC_38 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U24; + const OFFSET: u32 = 24; } const GPIO_EMC_39_MUX_ADDR: u32 = 0x401f80b0; const GPIO_EMC_39_PAD_ADDR: u32 = 0x401f82a0; pub type GPIO_EMC_39 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_39 { + impl crate::gpio::Pin<3> for GPIO_EMC_39 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U25; + const OFFSET: u32 = 25; } const GPIO_EMC_40_MUX_ADDR: u32 = 0x401f80b4; const GPIO_EMC_40_PAD_ADDR: u32 = 0x401f82a4; pub type GPIO_EMC_40 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_40 { + impl crate::gpio::Pin<3> for GPIO_EMC_40 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U26; + const OFFSET: u32 = 26; } const GPIO_EMC_41_MUX_ADDR: u32 = 0x401f80b8; const GPIO_EMC_41_PAD_ADDR: u32 = 0x401f82a8; pub type GPIO_EMC_41 = crate::Pad; - impl crate::gpio::Pin for GPIO_EMC_41 { + impl crate::gpio::Pin<3> for GPIO_EMC_41 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U27; + const OFFSET: u32 = 27; } /// All pads with prefix GPIO_EMC. @@ -593,160 +551,144 @@ pub mod gpio_ad_b0 { const GPIO_AD_B0_00_PAD_ADDR: u32 = 0x401f82ac; pub type GPIO_AD_B0_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_00 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_00 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U0; + const OFFSET: u32 = 0; } const GPIO_AD_B0_01_MUX_ADDR: u32 = 0x401f80c0; const GPIO_AD_B0_01_PAD_ADDR: u32 = 0x401f82b0; pub type GPIO_AD_B0_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_01 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_01 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U1; + const OFFSET: u32 = 1; } const GPIO_AD_B0_02_MUX_ADDR: u32 = 0x401f80c4; const GPIO_AD_B0_02_PAD_ADDR: u32 = 0x401f82b4; pub type GPIO_AD_B0_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_02 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_02 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U2; + const OFFSET: u32 = 2; } const GPIO_AD_B0_03_MUX_ADDR: u32 = 0x401f80c8; const GPIO_AD_B0_03_PAD_ADDR: u32 = 0x401f82b8; pub type GPIO_AD_B0_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_03 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_03 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U3; + const OFFSET: u32 = 3; } const GPIO_AD_B0_04_MUX_ADDR: u32 = 0x401f80cc; const GPIO_AD_B0_04_PAD_ADDR: u32 = 0x401f82bc; pub type GPIO_AD_B0_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_04 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_04 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U4; + const OFFSET: u32 = 4; } const GPIO_AD_B0_05_MUX_ADDR: u32 = 0x401f80d0; const GPIO_AD_B0_05_PAD_ADDR: u32 = 0x401f82c0; pub type GPIO_AD_B0_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_05 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_05 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U5; + const OFFSET: u32 = 5; } const GPIO_AD_B0_06_MUX_ADDR: u32 = 0x401f80d4; const GPIO_AD_B0_06_PAD_ADDR: u32 = 0x401f82c4; pub type GPIO_AD_B0_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_06 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_06 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U6; + const OFFSET: u32 = 6; } const GPIO_AD_B0_07_MUX_ADDR: u32 = 0x401f80d8; const GPIO_AD_B0_07_PAD_ADDR: u32 = 0x401f82c8; pub type GPIO_AD_B0_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_07 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_07 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U7; + const OFFSET: u32 = 7; } const GPIO_AD_B0_08_MUX_ADDR: u32 = 0x401f80dc; const GPIO_AD_B0_08_PAD_ADDR: u32 = 0x401f82cc; pub type GPIO_AD_B0_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_08 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_08 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U8; + const OFFSET: u32 = 8; } const GPIO_AD_B0_09_MUX_ADDR: u32 = 0x401f80e0; const GPIO_AD_B0_09_PAD_ADDR: u32 = 0x401f82d0; pub type GPIO_AD_B0_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_09 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_09 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U9; + const OFFSET: u32 = 9; } const GPIO_AD_B0_10_MUX_ADDR: u32 = 0x401f80e4; const GPIO_AD_B0_10_PAD_ADDR: u32 = 0x401f82d4; pub type GPIO_AD_B0_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_10 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_10 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U10; + const OFFSET: u32 = 10; } const GPIO_AD_B0_11_MUX_ADDR: u32 = 0x401f80e8; const GPIO_AD_B0_11_PAD_ADDR: u32 = 0x401f82d8; pub type GPIO_AD_B0_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_11 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_11 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U11; + const OFFSET: u32 = 11; } const GPIO_AD_B0_12_MUX_ADDR: u32 = 0x401f80ec; const GPIO_AD_B0_12_PAD_ADDR: u32 = 0x401f82dc; pub type GPIO_AD_B0_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_12 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_12 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U12; + const OFFSET: u32 = 12; } const GPIO_AD_B0_13_MUX_ADDR: u32 = 0x401f80f0; const GPIO_AD_B0_13_PAD_ADDR: u32 = 0x401f82e0; pub type GPIO_AD_B0_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_13 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_13 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U13; + const OFFSET: u32 = 13; } const GPIO_AD_B0_14_MUX_ADDR: u32 = 0x401f80f4; const GPIO_AD_B0_14_PAD_ADDR: u32 = 0x401f82e4; pub type GPIO_AD_B0_14 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_14 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_14 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U14; + const OFFSET: u32 = 14; } const GPIO_AD_B0_15_MUX_ADDR: u32 = 0x401f80f8; const GPIO_AD_B0_15_PAD_ADDR: u32 = 0x401f82e8; pub type GPIO_AD_B0_15 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B0_15 { + impl crate::gpio::Pin<1> for GPIO_AD_B0_15 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U15; + const OFFSET: u32 = 15; } /// All pads with prefix GPIO_AD_B0. @@ -840,160 +782,144 @@ pub mod gpio_ad_b1 { const GPIO_AD_B1_00_PAD_ADDR: u32 = 0x401f82ec; pub type GPIO_AD_B1_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_00 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_00 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U16; + const OFFSET: u32 = 16; } const GPIO_AD_B1_01_MUX_ADDR: u32 = 0x401f8100; const GPIO_AD_B1_01_PAD_ADDR: u32 = 0x401f82f0; pub type GPIO_AD_B1_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_01 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_01 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U17; + const OFFSET: u32 = 17; } const GPIO_AD_B1_02_MUX_ADDR: u32 = 0x401f8104; const GPIO_AD_B1_02_PAD_ADDR: u32 = 0x401f82f4; pub type GPIO_AD_B1_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_02 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_02 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U18; + const OFFSET: u32 = 18; } const GPIO_AD_B1_03_MUX_ADDR: u32 = 0x401f8108; const GPIO_AD_B1_03_PAD_ADDR: u32 = 0x401f82f8; pub type GPIO_AD_B1_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_03 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_03 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U19; + const OFFSET: u32 = 19; } const GPIO_AD_B1_04_MUX_ADDR: u32 = 0x401f810c; const GPIO_AD_B1_04_PAD_ADDR: u32 = 0x401f82fc; pub type GPIO_AD_B1_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_04 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_04 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U20; + const OFFSET: u32 = 20; } const GPIO_AD_B1_05_MUX_ADDR: u32 = 0x401f8110; const GPIO_AD_B1_05_PAD_ADDR: u32 = 0x401f8300; pub type GPIO_AD_B1_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_05 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_05 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U21; + const OFFSET: u32 = 21; } const GPIO_AD_B1_06_MUX_ADDR: u32 = 0x401f8114; const GPIO_AD_B1_06_PAD_ADDR: u32 = 0x401f8304; pub type GPIO_AD_B1_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_06 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_06 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U22; + const OFFSET: u32 = 22; } const GPIO_AD_B1_07_MUX_ADDR: u32 = 0x401f8118; const GPIO_AD_B1_07_PAD_ADDR: u32 = 0x401f8308; pub type GPIO_AD_B1_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_07 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_07 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U23; + const OFFSET: u32 = 23; } const GPIO_AD_B1_08_MUX_ADDR: u32 = 0x401f811c; const GPIO_AD_B1_08_PAD_ADDR: u32 = 0x401f830c; pub type GPIO_AD_B1_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_08 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_08 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U24; + const OFFSET: u32 = 24; } const GPIO_AD_B1_09_MUX_ADDR: u32 = 0x401f8120; const GPIO_AD_B1_09_PAD_ADDR: u32 = 0x401f8310; pub type GPIO_AD_B1_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_09 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_09 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U25; + const OFFSET: u32 = 25; } const GPIO_AD_B1_10_MUX_ADDR: u32 = 0x401f8124; const GPIO_AD_B1_10_PAD_ADDR: u32 = 0x401f8314; pub type GPIO_AD_B1_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_10 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_10 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U26; + const OFFSET: u32 = 26; } const GPIO_AD_B1_11_MUX_ADDR: u32 = 0x401f8128; const GPIO_AD_B1_11_PAD_ADDR: u32 = 0x401f8318; pub type GPIO_AD_B1_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_11 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_11 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U27; + const OFFSET: u32 = 27; } const GPIO_AD_B1_12_MUX_ADDR: u32 = 0x401f812c; const GPIO_AD_B1_12_PAD_ADDR: u32 = 0x401f831c; pub type GPIO_AD_B1_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_12 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_12 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U28; + const OFFSET: u32 = 28; } const GPIO_AD_B1_13_MUX_ADDR: u32 = 0x401f8130; const GPIO_AD_B1_13_PAD_ADDR: u32 = 0x401f8320; pub type GPIO_AD_B1_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_13 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_13 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U29; + const OFFSET: u32 = 29; } const GPIO_AD_B1_14_MUX_ADDR: u32 = 0x401f8134; const GPIO_AD_B1_14_PAD_ADDR: u32 = 0x401f8324; pub type GPIO_AD_B1_14 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_14 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_14 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U30; + const OFFSET: u32 = 30; } const GPIO_AD_B1_15_MUX_ADDR: u32 = 0x401f8138; const GPIO_AD_B1_15_PAD_ADDR: u32 = 0x401f8328; pub type GPIO_AD_B1_15 = crate::Pad; - impl crate::gpio::Pin for GPIO_AD_B1_15 { + impl crate::gpio::Pin<1> for GPIO_AD_B1_15 { const ALT: u32 = 5; - type Module = crate::consts::U1; - type Offset = crate::consts::U31; + const OFFSET: u32 = 31; } /// All pads with prefix GPIO_AD_B1. @@ -1087,160 +1013,144 @@ pub mod gpio_b0 { const GPIO_B0_00_PAD_ADDR: u32 = 0x401f832c; pub type GPIO_B0_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_00 { + impl crate::gpio::Pin<2> for GPIO_B0_00 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U0; + const OFFSET: u32 = 0; } const GPIO_B0_01_MUX_ADDR: u32 = 0x401f8140; const GPIO_B0_01_PAD_ADDR: u32 = 0x401f8330; pub type GPIO_B0_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_01 { + impl crate::gpio::Pin<2> for GPIO_B0_01 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U1; + const OFFSET: u32 = 1; } const GPIO_B0_02_MUX_ADDR: u32 = 0x401f8144; const GPIO_B0_02_PAD_ADDR: u32 = 0x401f8334; pub type GPIO_B0_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_02 { + impl crate::gpio::Pin<2> for GPIO_B0_02 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U2; + const OFFSET: u32 = 2; } const GPIO_B0_03_MUX_ADDR: u32 = 0x401f8148; const GPIO_B0_03_PAD_ADDR: u32 = 0x401f8338; pub type GPIO_B0_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_03 { + impl crate::gpio::Pin<2> for GPIO_B0_03 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U3; + const OFFSET: u32 = 3; } const GPIO_B0_04_MUX_ADDR: u32 = 0x401f814c; const GPIO_B0_04_PAD_ADDR: u32 = 0x401f833c; pub type GPIO_B0_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_04 { + impl crate::gpio::Pin<2> for GPIO_B0_04 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U4; + const OFFSET: u32 = 4; } const GPIO_B0_05_MUX_ADDR: u32 = 0x401f8150; const GPIO_B0_05_PAD_ADDR: u32 = 0x401f8340; pub type GPIO_B0_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_05 { + impl crate::gpio::Pin<2> for GPIO_B0_05 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U5; + const OFFSET: u32 = 5; } const GPIO_B0_06_MUX_ADDR: u32 = 0x401f8154; const GPIO_B0_06_PAD_ADDR: u32 = 0x401f8344; pub type GPIO_B0_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_06 { + impl crate::gpio::Pin<2> for GPIO_B0_06 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U6; + const OFFSET: u32 = 6; } const GPIO_B0_07_MUX_ADDR: u32 = 0x401f8158; const GPIO_B0_07_PAD_ADDR: u32 = 0x401f8348; pub type GPIO_B0_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_07 { + impl crate::gpio::Pin<2> for GPIO_B0_07 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U7; + const OFFSET: u32 = 7; } const GPIO_B0_08_MUX_ADDR: u32 = 0x401f815c; const GPIO_B0_08_PAD_ADDR: u32 = 0x401f834c; pub type GPIO_B0_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_08 { + impl crate::gpio::Pin<2> for GPIO_B0_08 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U8; + const OFFSET: u32 = 8; } const GPIO_B0_09_MUX_ADDR: u32 = 0x401f8160; const GPIO_B0_09_PAD_ADDR: u32 = 0x401f8350; pub type GPIO_B0_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_09 { + impl crate::gpio::Pin<2> for GPIO_B0_09 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U9; + const OFFSET: u32 = 9; } const GPIO_B0_10_MUX_ADDR: u32 = 0x401f8164; const GPIO_B0_10_PAD_ADDR: u32 = 0x401f8354; pub type GPIO_B0_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_10 { + impl crate::gpio::Pin<2> for GPIO_B0_10 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U10; + const OFFSET: u32 = 10; } const GPIO_B0_11_MUX_ADDR: u32 = 0x401f8168; const GPIO_B0_11_PAD_ADDR: u32 = 0x401f8358; pub type GPIO_B0_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_11 { + impl crate::gpio::Pin<2> for GPIO_B0_11 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U11; + const OFFSET: u32 = 11; } const GPIO_B0_12_MUX_ADDR: u32 = 0x401f816c; const GPIO_B0_12_PAD_ADDR: u32 = 0x401f835c; pub type GPIO_B0_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_12 { + impl crate::gpio::Pin<2> for GPIO_B0_12 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U12; + const OFFSET: u32 = 12; } const GPIO_B0_13_MUX_ADDR: u32 = 0x401f8170; const GPIO_B0_13_PAD_ADDR: u32 = 0x401f8360; pub type GPIO_B0_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_13 { + impl crate::gpio::Pin<2> for GPIO_B0_13 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U13; + const OFFSET: u32 = 13; } const GPIO_B0_14_MUX_ADDR: u32 = 0x401f8174; const GPIO_B0_14_PAD_ADDR: u32 = 0x401f8364; pub type GPIO_B0_14 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_14 { + impl crate::gpio::Pin<2> for GPIO_B0_14 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U14; + const OFFSET: u32 = 14; } const GPIO_B0_15_MUX_ADDR: u32 = 0x401f8178; const GPIO_B0_15_PAD_ADDR: u32 = 0x401f8368; pub type GPIO_B0_15 = crate::Pad; - impl crate::gpio::Pin for GPIO_B0_15 { + impl crate::gpio::Pin<2> for GPIO_B0_15 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U15; + const OFFSET: u32 = 15; } /// All pads with prefix GPIO_B0. @@ -1334,160 +1244,144 @@ pub mod gpio_b1 { const GPIO_B1_00_PAD_ADDR: u32 = 0x401f836c; pub type GPIO_B1_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_00 { + impl crate::gpio::Pin<2> for GPIO_B1_00 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U16; + const OFFSET: u32 = 16; } const GPIO_B1_01_MUX_ADDR: u32 = 0x401f8180; const GPIO_B1_01_PAD_ADDR: u32 = 0x401f8370; pub type GPIO_B1_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_01 { + impl crate::gpio::Pin<2> for GPIO_B1_01 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U17; + const OFFSET: u32 = 17; } const GPIO_B1_02_MUX_ADDR: u32 = 0x401f8184; const GPIO_B1_02_PAD_ADDR: u32 = 0x401f8374; pub type GPIO_B1_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_02 { + impl crate::gpio::Pin<2> for GPIO_B1_02 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U18; + const OFFSET: u32 = 18; } const GPIO_B1_03_MUX_ADDR: u32 = 0x401f8188; const GPIO_B1_03_PAD_ADDR: u32 = 0x401f8378; pub type GPIO_B1_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_03 { + impl crate::gpio::Pin<2> for GPIO_B1_03 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U19; + const OFFSET: u32 = 19; } const GPIO_B1_04_MUX_ADDR: u32 = 0x401f818c; const GPIO_B1_04_PAD_ADDR: u32 = 0x401f837c; pub type GPIO_B1_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_04 { + impl crate::gpio::Pin<2> for GPIO_B1_04 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U20; + const OFFSET: u32 = 20; } const GPIO_B1_05_MUX_ADDR: u32 = 0x401f8190; const GPIO_B1_05_PAD_ADDR: u32 = 0x401f8380; pub type GPIO_B1_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_05 { + impl crate::gpio::Pin<2> for GPIO_B1_05 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U21; + const OFFSET: u32 = 21; } const GPIO_B1_06_MUX_ADDR: u32 = 0x401f8194; const GPIO_B1_06_PAD_ADDR: u32 = 0x401f8384; pub type GPIO_B1_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_06 { + impl crate::gpio::Pin<2> for GPIO_B1_06 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U22; + const OFFSET: u32 = 22; } const GPIO_B1_07_MUX_ADDR: u32 = 0x401f8198; const GPIO_B1_07_PAD_ADDR: u32 = 0x401f8388; pub type GPIO_B1_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_07 { + impl crate::gpio::Pin<2> for GPIO_B1_07 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U23; + const OFFSET: u32 = 23; } const GPIO_B1_08_MUX_ADDR: u32 = 0x401f819c; const GPIO_B1_08_PAD_ADDR: u32 = 0x401f838c; pub type GPIO_B1_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_08 { + impl crate::gpio::Pin<2> for GPIO_B1_08 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U24; + const OFFSET: u32 = 24; } const GPIO_B1_09_MUX_ADDR: u32 = 0x401f81a0; const GPIO_B1_09_PAD_ADDR: u32 = 0x401f8390; pub type GPIO_B1_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_09 { + impl crate::gpio::Pin<2> for GPIO_B1_09 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U25; + const OFFSET: u32 = 25; } const GPIO_B1_10_MUX_ADDR: u32 = 0x401f81a4; const GPIO_B1_10_PAD_ADDR: u32 = 0x401f8394; pub type GPIO_B1_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_10 { + impl crate::gpio::Pin<2> for GPIO_B1_10 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U26; + const OFFSET: u32 = 26; } const GPIO_B1_11_MUX_ADDR: u32 = 0x401f81a8; const GPIO_B1_11_PAD_ADDR: u32 = 0x401f8398; pub type GPIO_B1_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_11 { + impl crate::gpio::Pin<2> for GPIO_B1_11 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U27; + const OFFSET: u32 = 27; } const GPIO_B1_12_MUX_ADDR: u32 = 0x401f81ac; const GPIO_B1_12_PAD_ADDR: u32 = 0x401f839c; pub type GPIO_B1_12 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_12 { + impl crate::gpio::Pin<2> for GPIO_B1_12 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U28; + const OFFSET: u32 = 28; } const GPIO_B1_13_MUX_ADDR: u32 = 0x401f81b0; const GPIO_B1_13_PAD_ADDR: u32 = 0x401f83a0; pub type GPIO_B1_13 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_13 { + impl crate::gpio::Pin<2> for GPIO_B1_13 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U29; + const OFFSET: u32 = 29; } const GPIO_B1_14_MUX_ADDR: u32 = 0x401f81b4; const GPIO_B1_14_PAD_ADDR: u32 = 0x401f83a4; pub type GPIO_B1_14 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_14 { + impl crate::gpio::Pin<2> for GPIO_B1_14 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U30; + const OFFSET: u32 = 30; } const GPIO_B1_15_MUX_ADDR: u32 = 0x401f81b8; const GPIO_B1_15_PAD_ADDR: u32 = 0x401f83a8; pub type GPIO_B1_15 = crate::Pad; - impl crate::gpio::Pin for GPIO_B1_15 { + impl crate::gpio::Pin<2> for GPIO_B1_15 { const ALT: u32 = 5; - type Module = crate::consts::U2; - type Offset = crate::consts::U31; + const OFFSET: u32 = 31; } /// All pads with prefix GPIO_B1. @@ -1581,60 +1475,54 @@ pub mod gpio_sd_b0 { const GPIO_SD_B0_00_PAD_ADDR: u32 = 0x401f83ac; pub type GPIO_SD_B0_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B0_00 { + impl crate::gpio::Pin<3> for GPIO_SD_B0_00 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U12; + const OFFSET: u32 = 12; } const GPIO_SD_B0_01_MUX_ADDR: u32 = 0x401f81c0; const GPIO_SD_B0_01_PAD_ADDR: u32 = 0x401f83b0; pub type GPIO_SD_B0_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B0_01 { + impl crate::gpio::Pin<3> for GPIO_SD_B0_01 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U13; + const OFFSET: u32 = 13; } const GPIO_SD_B0_02_MUX_ADDR: u32 = 0x401f81c4; const GPIO_SD_B0_02_PAD_ADDR: u32 = 0x401f83b4; pub type GPIO_SD_B0_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B0_02 { + impl crate::gpio::Pin<3> for GPIO_SD_B0_02 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U14; + const OFFSET: u32 = 14; } const GPIO_SD_B0_03_MUX_ADDR: u32 = 0x401f81c8; const GPIO_SD_B0_03_PAD_ADDR: u32 = 0x401f83b8; pub type GPIO_SD_B0_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B0_03 { + impl crate::gpio::Pin<3> for GPIO_SD_B0_03 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U15; + const OFFSET: u32 = 15; } const GPIO_SD_B0_04_MUX_ADDR: u32 = 0x401f81cc; const GPIO_SD_B0_04_PAD_ADDR: u32 = 0x401f83bc; pub type GPIO_SD_B0_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B0_04 { + impl crate::gpio::Pin<3> for GPIO_SD_B0_04 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U16; + const OFFSET: u32 = 16; } const GPIO_SD_B0_05_MUX_ADDR: u32 = 0x401f81d0; const GPIO_SD_B0_05_PAD_ADDR: u32 = 0x401f83c0; pub type GPIO_SD_B0_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B0_05 { + impl crate::gpio::Pin<3> for GPIO_SD_B0_05 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U17; + const OFFSET: u32 = 17; } /// All pads with prefix GPIO_SD_B0. @@ -1698,120 +1586,108 @@ pub mod gpio_sd_b1 { const GPIO_SD_B1_00_PAD_ADDR: u32 = 0x401f83c4; pub type GPIO_SD_B1_00 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_00 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_00 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U0; + const OFFSET: u32 = 0; } const GPIO_SD_B1_01_MUX_ADDR: u32 = 0x401f81d8; const GPIO_SD_B1_01_PAD_ADDR: u32 = 0x401f83c8; pub type GPIO_SD_B1_01 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_01 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_01 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U1; + const OFFSET: u32 = 1; } const GPIO_SD_B1_02_MUX_ADDR: u32 = 0x401f81dc; const GPIO_SD_B1_02_PAD_ADDR: u32 = 0x401f83cc; pub type GPIO_SD_B1_02 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_02 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_02 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U2; + const OFFSET: u32 = 2; } const GPIO_SD_B1_03_MUX_ADDR: u32 = 0x401f81e0; const GPIO_SD_B1_03_PAD_ADDR: u32 = 0x401f83d0; pub type GPIO_SD_B1_03 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_03 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_03 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U3; + const OFFSET: u32 = 3; } const GPIO_SD_B1_04_MUX_ADDR: u32 = 0x401f81e4; const GPIO_SD_B1_04_PAD_ADDR: u32 = 0x401f83d4; pub type GPIO_SD_B1_04 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_04 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_04 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U4; + const OFFSET: u32 = 4; } const GPIO_SD_B1_05_MUX_ADDR: u32 = 0x401f81e8; const GPIO_SD_B1_05_PAD_ADDR: u32 = 0x401f83d8; pub type GPIO_SD_B1_05 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_05 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_05 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U5; + const OFFSET: u32 = 5; } const GPIO_SD_B1_06_MUX_ADDR: u32 = 0x401f81ec; const GPIO_SD_B1_06_PAD_ADDR: u32 = 0x401f83dc; pub type GPIO_SD_B1_06 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_06 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_06 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U6; + const OFFSET: u32 = 6; } const GPIO_SD_B1_07_MUX_ADDR: u32 = 0x401f81f0; const GPIO_SD_B1_07_PAD_ADDR: u32 = 0x401f83e0; pub type GPIO_SD_B1_07 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_07 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_07 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U7; + const OFFSET: u32 = 7; } const GPIO_SD_B1_08_MUX_ADDR: u32 = 0x401f81f4; const GPIO_SD_B1_08_PAD_ADDR: u32 = 0x401f83e4; pub type GPIO_SD_B1_08 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_08 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_08 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U8; + const OFFSET: u32 = 8; } const GPIO_SD_B1_09_MUX_ADDR: u32 = 0x401f81f8; const GPIO_SD_B1_09_PAD_ADDR: u32 = 0x401f83e8; pub type GPIO_SD_B1_09 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_09 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_09 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U9; + const OFFSET: u32 = 9; } const GPIO_SD_B1_10_MUX_ADDR: u32 = 0x401f81fc; const GPIO_SD_B1_10_PAD_ADDR: u32 = 0x401f83ec; pub type GPIO_SD_B1_10 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_10 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_10 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U10; + const OFFSET: u32 = 10; } const GPIO_SD_B1_11_MUX_ADDR: u32 = 0x401f8200; const GPIO_SD_B1_11_PAD_ADDR: u32 = 0x401f83f0; pub type GPIO_SD_B1_11 = crate::Pad; - impl crate::gpio::Pin for GPIO_SD_B1_11 { + impl crate::gpio::Pin<3> for GPIO_SD_B1_11 { const ALT: u32 = 5; - type Module = crate::consts::U3; - type Offset = crate::consts::U11; + const OFFSET: u32 = 11; } /// All pads with prefix GPIO_SD_B1. @@ -1892,72 +1768,72 @@ pub mod gpio_spi_b0 { const GPIO_SPI_B0_00_MUX_ADDR: u32 = 0x401f865c; const GPIO_SPI_B0_00_PAD_ADDR: u32 = 0x401f86b4; pub type GPIO_SPI_B0_00 = crate::Pad; - // GPIO_SPI_B0_00 does not have a GPIO alternate. + // GPIO_SPI_B0_00 does not have any GPIO alternates. const GPIO_SPI_B0_01_MUX_ADDR: u32 = 0x401f8660; const GPIO_SPI_B0_01_PAD_ADDR: u32 = 0x401f86b8; pub type GPIO_SPI_B0_01 = crate::Pad; - // GPIO_SPI_B0_01 does not have a GPIO alternate. + // GPIO_SPI_B0_01 does not have any GPIO alternates. const GPIO_SPI_B0_02_MUX_ADDR: u32 = 0x401f8664; const GPIO_SPI_B0_02_PAD_ADDR: u32 = 0x401f86bc; pub type GPIO_SPI_B0_02 = crate::Pad; - // GPIO_SPI_B0_02 does not have a GPIO alternate. + // GPIO_SPI_B0_02 does not have any GPIO alternates. const GPIO_SPI_B0_03_MUX_ADDR: u32 = 0x401f8668; const GPIO_SPI_B0_03_PAD_ADDR: u32 = 0x401f86c0; pub type GPIO_SPI_B0_03 = crate::Pad; - // GPIO_SPI_B0_03 does not have a GPIO alternate. + // GPIO_SPI_B0_03 does not have any GPIO alternates. const GPIO_SPI_B0_04_MUX_ADDR: u32 = 0x401f866c; const GPIO_SPI_B0_04_PAD_ADDR: u32 = 0x401f86c4; pub type GPIO_SPI_B0_04 = crate::Pad; - // GPIO_SPI_B0_04 does not have a GPIO alternate. + // GPIO_SPI_B0_04 does not have any GPIO alternates. const GPIO_SPI_B0_05_MUX_ADDR: u32 = 0x401f8670; const GPIO_SPI_B0_05_PAD_ADDR: u32 = 0x401f86c8; pub type GPIO_SPI_B0_05 = crate::Pad; - // GPIO_SPI_B0_05 does not have a GPIO alternate. + // GPIO_SPI_B0_05 does not have any GPIO alternates. const GPIO_SPI_B0_06_MUX_ADDR: u32 = 0x401f8674; const GPIO_SPI_B0_06_PAD_ADDR: u32 = 0x401f86cc; pub type GPIO_SPI_B0_06 = crate::Pad; - // GPIO_SPI_B0_06 does not have a GPIO alternate. + // GPIO_SPI_B0_06 does not have any GPIO alternates. const GPIO_SPI_B0_07_MUX_ADDR: u32 = 0x401f8678; const GPIO_SPI_B0_07_PAD_ADDR: u32 = 0x401f86d0; pub type GPIO_SPI_B0_07 = crate::Pad; - // GPIO_SPI_B0_07 does not have a GPIO alternate. + // GPIO_SPI_B0_07 does not have any GPIO alternates. const GPIO_SPI_B0_08_MUX_ADDR: u32 = 0x401f867c; const GPIO_SPI_B0_08_PAD_ADDR: u32 = 0x401f86d4; pub type GPIO_SPI_B0_08 = crate::Pad; - // GPIO_SPI_B0_08 does not have a GPIO alternate. + // GPIO_SPI_B0_08 does not have any GPIO alternates. const GPIO_SPI_B0_09_MUX_ADDR: u32 = 0x401f8680; const GPIO_SPI_B0_09_PAD_ADDR: u32 = 0x401f86d8; pub type GPIO_SPI_B0_09 = crate::Pad; - // GPIO_SPI_B0_09 does not have a GPIO alternate. + // GPIO_SPI_B0_09 does not have any GPIO alternates. const GPIO_SPI_B0_10_MUX_ADDR: u32 = 0x401f8684; const GPIO_SPI_B0_10_PAD_ADDR: u32 = 0x401f86dc; pub type GPIO_SPI_B0_10 = crate::Pad; - // GPIO_SPI_B0_10 does not have a GPIO alternate. + // GPIO_SPI_B0_10 does not have any GPIO alternates. const GPIO_SPI_B0_11_MUX_ADDR: u32 = 0x401f8688; const GPIO_SPI_B0_11_PAD_ADDR: u32 = 0x401f86e0; pub type GPIO_SPI_B0_11 = crate::Pad; - // GPIO_SPI_B0_11 does not have a GPIO alternate. + // GPIO_SPI_B0_11 does not have any GPIO alternates. const GPIO_SPI_B0_12_MUX_ADDR: u32 = 0x401f868c; const GPIO_SPI_B0_12_PAD_ADDR: u32 = 0x401f86e4; pub type GPIO_SPI_B0_12 = crate::Pad; - // GPIO_SPI_B0_12 does not have a GPIO alternate. + // GPIO_SPI_B0_12 does not have any GPIO alternates. const GPIO_SPI_B0_13_MUX_ADDR: u32 = 0x401f8690; const GPIO_SPI_B0_13_PAD_ADDR: u32 = 0x401f86e8; pub type GPIO_SPI_B0_13 = crate::Pad; - // GPIO_SPI_B0_13 does not have a GPIO alternate. + // GPIO_SPI_B0_13 does not have any GPIO alternates. /// All pads with prefix GPIO_SPI_B0. pub struct Pads { @@ -2043,42 +1919,42 @@ pub mod gpio_spi_b1 { const GPIO_SPI_B1_00_MUX_ADDR: u32 = 0x401f8694; const GPIO_SPI_B1_00_PAD_ADDR: u32 = 0x401f86ec; pub type GPIO_SPI_B1_00 = crate::Pad; - // GPIO_SPI_B1_00 does not have a GPIO alternate. + // GPIO_SPI_B1_00 does not have any GPIO alternates. const GPIO_SPI_B1_01_MUX_ADDR: u32 = 0x401f8698; const GPIO_SPI_B1_01_PAD_ADDR: u32 = 0x401f86f0; pub type GPIO_SPI_B1_01 = crate::Pad; - // GPIO_SPI_B1_01 does not have a GPIO alternate. + // GPIO_SPI_B1_01 does not have any GPIO alternates. const GPIO_SPI_B1_02_MUX_ADDR: u32 = 0x401f869c; const GPIO_SPI_B1_02_PAD_ADDR: u32 = 0x401f86f4; pub type GPIO_SPI_B1_02 = crate::Pad; - // GPIO_SPI_B1_02 does not have a GPIO alternate. + // GPIO_SPI_B1_02 does not have any GPIO alternates. const GPIO_SPI_B1_03_MUX_ADDR: u32 = 0x401f86a0; const GPIO_SPI_B1_03_PAD_ADDR: u32 = 0x401f86f8; pub type GPIO_SPI_B1_03 = crate::Pad; - // GPIO_SPI_B1_03 does not have a GPIO alternate. + // GPIO_SPI_B1_03 does not have any GPIO alternates. const GPIO_SPI_B1_04_MUX_ADDR: u32 = 0x401f86a4; const GPIO_SPI_B1_04_PAD_ADDR: u32 = 0x401f86fc; pub type GPIO_SPI_B1_04 = crate::Pad; - // GPIO_SPI_B1_04 does not have a GPIO alternate. + // GPIO_SPI_B1_04 does not have any GPIO alternates. const GPIO_SPI_B1_05_MUX_ADDR: u32 = 0x401f86a8; const GPIO_SPI_B1_05_PAD_ADDR: u32 = 0x401f8700; pub type GPIO_SPI_B1_05 = crate::Pad; - // GPIO_SPI_B1_05 does not have a GPIO alternate. + // GPIO_SPI_B1_05 does not have any GPIO alternates. const GPIO_SPI_B1_06_MUX_ADDR: u32 = 0x401f86ac; const GPIO_SPI_B1_06_PAD_ADDR: u32 = 0x401f8704; pub type GPIO_SPI_B1_06 = crate::Pad; - // GPIO_SPI_B1_06 does not have a GPIO alternate. + // GPIO_SPI_B1_06 does not have any GPIO alternates. const GPIO_SPI_B1_07_MUX_ADDR: u32 = 0x401f86b0; const GPIO_SPI_B1_07_PAD_ADDR: u32 = 0x401f8708; pub type GPIO_SPI_B1_07 = crate::Pad; - // GPIO_SPI_B1_07 does not have a GPIO alternate. + // GPIO_SPI_B1_07 does not have any GPIO alternates. /// All pads with prefix GPIO_SPI_B1. pub struct Pads { @@ -2152,6 +2028,7 @@ pub struct Pads { pub gpio_spi_b0: gpio_spi_b0::Pads, pub gpio_spi_b1: gpio_spi_b1::Pads, } + impl Pads { /// Take all pads from this group /// @@ -2197,6 +2074,7 @@ impl Pads { } } } + /// All erased pads. pub struct ErasedPads { pub gpio_emc: gpio_emc::ErasedPads, diff --git a/src/imxrt1170/flexpwm.rs b/src/imxrt1170/flexpwm.rs new file mode 100644 index 0000000..d2b7b88 --- /dev/null +++ b/src/imxrt1170/flexpwm.rs @@ -0,0 +1,12 @@ +//! PWM implementation. + +use super::pads::gpio_ad::*; +use crate::{ + consts::*, + flexpwm::{Pin, A, B}, +}; + +pwm!(module: U1, submodule: U2, alt: 4, pad: GPIO_AD_04, output: A); +pwm!(module: U1, submodule: U2, alt: 4, pad: GPIO_AD_05, output: B); +pwm!(module: U2, submodule: U2, alt: 4, pad: GPIO_AD_28, output: A); +pwm!(module: U2, submodule: U2, alt: 4, pad: GPIO_AD_29, output: B); diff --git a/src/imxrt1170/lpi2c.rs b/src/imxrt1170/lpi2c.rs new file mode 100644 index 0000000..1c497bb --- /dev/null +++ b/src/imxrt1170/lpi2c.rs @@ -0,0 +1,70 @@ +//! I2C pin implementations + +use super::pads::gpio_lpsr::*; +use crate::{ + consts::*, + lpi2c::{Pin, Scl, Sda}, + Daisy, +}; + +// +// I2C5 +// +i2c!(module: U5, alt: 0, pad: GPIO_LPSR_05, signal: Scl, daisy: DAISY_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_GPIO_LPSR_05); +i2c!(module: U5, alt: 0, pad: GPIO_LPSR_04, signal: Sda, daisy: DAISY_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_GPIO_LPSR_04); + +mod daisy { + #![allow(unused)] + use super::Daisy; + + pub const DAISY_LPI2C1_LPI2C_SCL_SELECT_GPIO_AD_08: Daisy = + Daisy::new(0x400e85ac as *mut u32, 0); + pub const DAISY_LPI2C1_LPI2C_SCL_SELECT_GPIO_AD_32: Daisy = + Daisy::new(0x400e85ac as *mut u32, 1); + pub const DAISY_LPI2C1_LPI2C_SDA_SELECT_GPIO_AD_09: Daisy = + Daisy::new(0x400e85b0 as *mut u32, 0); + pub const DAISY_LPI2C1_LPI2C_SDA_SELECT_GPIO_AD_33: Daisy = + Daisy::new(0x400e85b0 as *mut u32, 1); + pub const DAISY_LPI2C2_LPI2C_SCL_SELECT_GPIO_EMC_B2_00: Daisy = + Daisy::new(0x400e85b4 as *mut u32, 0); + pub const DAISY_LPI2C2_LPI2C_SCL_SELECT_GPIO_AD_18: Daisy = + Daisy::new(0x400e85b4 as *mut u32, 1); + pub const DAISY_LPI2C2_LPI2C_SDA_SELECT_GPIO_EMC_B2_01: Daisy = + Daisy::new(0x400e85b8 as *mut u32, 0); + pub const DAISY_LPI2C2_LPI2C_SDA_SELECT_GPIO_AD_19: Daisy = + Daisy::new(0x400e85b8 as *mut u32, 1); + pub const DAISY_LPI2C3_LPI2C_SCL_SELECT_GPIO_DISP_B1_02: Daisy = + Daisy::new(0x400e85bc as *mut u32, 0); + pub const DAISY_LPI2C3_LPI2C_SCL_SELECT_GPIO_DISP_B2_10: Daisy = + Daisy::new(0x400e85bc as *mut u32, 1); + pub const DAISY_LPI2C3_LPI2C_SDA_SELECT_GPIO_DISP_B1_03: Daisy = + Daisy::new(0x400e85c0 as *mut u32, 0); + pub const DAISY_LPI2C3_LPI2C_SDA_SELECT_GPIO_DISP_B2_11: Daisy = + Daisy::new(0x400e85c0 as *mut u32, 1); + pub const DAISY_LPI2C4_LPI2C_SCL_SELECT_GPIO_AD_24: Daisy = + Daisy::new(0x400e85c4 as *mut u32, 0); + pub const DAISY_LPI2C4_LPI2C_SCL_SELECT_GPIO_DISP_B2_12: Daisy = + Daisy::new(0x400e85c4 as *mut u32, 1); + pub const DAISY_LPI2C4_LPI2C_SDA_SELECT_GPIO_AD_25: Daisy = + Daisy::new(0x400e85c8 as *mut u32, 0); + pub const DAISY_LPI2C4_LPI2C_SDA_SELECT_GPIO_DISP_B2_13: Daisy = + Daisy::new(0x400e85c8 as *mut u32, 1); + pub const DAISY_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_GPIO_LPSR_05: Daisy = + Daisy::new(0x40c08084 as *mut u32, 0); + pub const DAISY_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_GPIO_LPSR_09: Daisy = + Daisy::new(0x40c08084 as *mut u32, 1); + pub const DAISY_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_GPIO_LPSR_04: Daisy = + Daisy::new(0x40c08088 as *mut u32, 0); + pub const DAISY_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_GPIO_LPSR_08: Daisy = + Daisy::new(0x40c08088 as *mut u32, 1); + pub const DAISY_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_GPIO_LPSR_07: Daisy = + Daisy::new(0x40c0808c as *mut u32, 0); + pub const DAISY_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_GPIO_LPSR_11: Daisy = + Daisy::new(0x40c0808c as *mut u32, 1); + pub const DAISY_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_GPIO_LPSR_06: Daisy = + Daisy::new(0x40c08090 as *mut u32, 0); + pub const DAISY_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_GPIO_LPSR_10: Daisy = + Daisy::new(0x40c08090 as *mut u32, 1); +} + +use daisy::*; diff --git a/src/imxrt1170/lpspi.rs b/src/imxrt1170/lpspi.rs new file mode 100644 index 0000000..94580ca --- /dev/null +++ b/src/imxrt1170/lpspi.rs @@ -0,0 +1,126 @@ +use super::pads::gpio_ad::*; +use crate::{ + consts::*, + lpspi::{Pcs0, Pin, Sck, Sdi, Sdo}, + Daisy, +}; + +// +// SPI1 +// + +// PCS0 +spi!(module: U1, alt: 0, pad: GPIO_AD_29, signal: Pcs0, daisy: DAISY_LPSPI1_LPSPI_PCS_0_SELECT_GPIO_AD_29); + +// SCK +spi!(module: U1, alt: 0, pad: GPIO_AD_28, signal: Sck, daisy: DAISY_LPSPI1_LPSPI_SCK_SELECT_GPIO_AD_28); + +// SDI +spi!(module: U1, alt: 0, pad: GPIO_AD_31, signal: Sdi, daisy: DAISY_LPSPI1_LPSPI_SDI_SELECT_GPIO_AD_31); + +// SDO +spi!(module: U1, alt: 0, pad: GPIO_AD_30, signal: Sdo, daisy: DAISY_LPSPI1_LPSPI_SDO_SELECT_GPIO_AD_30); + +mod daisy { + #![allow(unused)] + use super::Daisy; + + pub const DAISY_LPSPI1_LPSPI_PCS_0_SELECT_GPIO_EMC_B2_01: Daisy = + Daisy::new(0x400e85cc as *mut u32, 0); + pub const DAISY_LPSPI1_LPSPI_PCS_0_SELECT_GPIO_AD_29: Daisy = + Daisy::new(0x400e85cc as *mut u32, 1); + pub const DAISY_LPSPI1_LPSPI_SCK_SELECT_GPIO_EMC_B2_00: Daisy = + Daisy::new(0x400e85d0 as *mut u32, 0); + pub const DAISY_LPSPI1_LPSPI_SCK_SELECT_GPIO_AD_28: Daisy = + Daisy::new(0x400e85d0 as *mut u32, 1); + pub const DAISY_LPSPI1_LPSPI_SDI_SELECT_GPIO_EMC_B2_03: Daisy = + Daisy::new(0x400e85d4 as *mut u32, 0); + pub const DAISY_LPSPI1_LPSPI_SDI_SELECT_GPIO_AD_31: Daisy = + Daisy::new(0x400e85d4 as *mut u32, 1); + pub const DAISY_LPSPI1_LPSPI_SDO_SELECT_GPIO_EMC_B2_02: Daisy = + Daisy::new(0x400e85d8 as *mut u32, 0); + pub const DAISY_LPSPI1_LPSPI_SDO_SELECT_GPIO_AD_30: Daisy = + Daisy::new(0x400e85d8 as *mut u32, 1); + pub const DAISY_LPSPI2_LPSPI_PCS_0_SELECT_GPIO_AD_25: Daisy = + Daisy::new(0x400e85dc as *mut u32, 0); + pub const DAISY_LPSPI2_LPSPI_PCS_0_SELECT_GPIO_SD_B2_08: Daisy = + Daisy::new(0x400e85dc as *mut u32, 1); + pub const DAISY_LPSPI2_LPSPI_PCS_1_SELECT_GPIO_AD_21: Daisy = + Daisy::new(0x400e85e0 as *mut u32, 0); + pub const DAISY_LPSPI2_LPSPI_PCS_1_SELECT_GPIO_SD_B2_11: Daisy = + Daisy::new(0x400e85e0 as *mut u32, 1); + pub const DAISY_LPSPI2_LPSPI_SCK_SELECT_GPIO_AD_24: Daisy = + Daisy::new(0x400e85e4 as *mut u32, 0); + pub const DAISY_LPSPI2_LPSPI_SCK_SELECT_GPIO_SD_B2_07: Daisy = + Daisy::new(0x400e85e4 as *mut u32, 1); + pub const DAISY_LPSPI2_LPSPI_SDI_SELECT_GPIO_AD_27: Daisy = + Daisy::new(0x400e85e8 as *mut u32, 0); + pub const DAISY_LPSPI2_LPSPI_SDI_SELECT_GPIO_SD_B2_10: Daisy = + Daisy::new(0x400e85e8 as *mut u32, 1); + pub const DAISY_LPSPI2_LPSPI_SDO_SELECT_GPIO_AD_26: Daisy = + Daisy::new(0x400e85ec as *mut u32, 0); + pub const DAISY_LPSPI2_LPSPI_SDO_SELECT_GPIO_SD_B2_09: Daisy = + Daisy::new(0x400e85ec as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_PCS_0_SELECT_GPIO_EMC_B2_05: Daisy = + Daisy::new(0x400e85f0 as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_PCS_0_SELECT_GPIO_DISP_B1_07: Daisy = + Daisy::new(0x400e85f0 as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_PCS_1_SELECT_GPIO_EMC_B2_08: Daisy = + Daisy::new(0x400e85f4 as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_PCS_1_SELECT_GPIO_DISP_B1_08: Daisy = + Daisy::new(0x400e85f4 as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_PCS_2_SELECT_GPIO_EMC_B2_09: Daisy = + Daisy::new(0x400e85f8 as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_PCS_2_SELECT_GPIO_DISP_B1_09: Daisy = + Daisy::new(0x400e85f8 as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_PCS_3_SELECT_GPIO_EMC_B2_10: Daisy = + Daisy::new(0x400e85fc as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_PCS_3_SELECT_GPIO_DISP_B1_10: Daisy = + Daisy::new(0x400e85fc as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_SCK_SELECT_GPIO_EMC_B2_04: Daisy = + Daisy::new(0x400e8600 as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_SCK_SELECT_GPIO_DISP_B1_04: Daisy = + Daisy::new(0x400e8600 as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_SDI_SELECT_GPIO_EMC_B2_07: Daisy = + Daisy::new(0x400e8604 as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_SDI_SELECT_GPIO_DISP_B1_05: Daisy = + Daisy::new(0x400e8604 as *mut u32, 1); + pub const DAISY_LPSPI3_LPSPI_SDO_SELECT_GPIO_EMC_B2_06: Daisy = + Daisy::new(0x400e8608 as *mut u32, 0); + pub const DAISY_LPSPI3_LPSPI_SDO_SELECT_GPIO_DISP_B1_06: Daisy = + Daisy::new(0x400e8608 as *mut u32, 1); + pub const DAISY_LPSPI4_LPSPI_PCS_0_SELECT_GPIO_SD_B2_01: Daisy = + Daisy::new(0x400e860c as *mut u32, 0); + pub const DAISY_LPSPI4_LPSPI_PCS_0_SELECT_GPIO_DISP_B2_15: Daisy = + Daisy::new(0x400e860c as *mut u32, 1); + pub const DAISY_LPSPI4_LPSPI_SCK_SELECT_GPIO_SD_B2_00: Daisy = + Daisy::new(0x400e8610 as *mut u32, 0); + pub const DAISY_LPSPI4_LPSPI_SCK_SELECT_GPIO_DISP_B2_12: Daisy = + Daisy::new(0x400e8610 as *mut u32, 1); + pub const DAISY_LPSPI4_LPSPI_SDI_SELECT_GPIO_SD_B2_03: Daisy = + Daisy::new(0x400e8614 as *mut u32, 0); + pub const DAISY_LPSPI4_LPSPI_SDI_SELECT_GPIO_DISP_B2_13: Daisy = + Daisy::new(0x400e8614 as *mut u32, 1); + pub const DAISY_LPSPI4_LPSPI_SDO_SELECT_GPIO_SD_B2_02: Daisy = + Daisy::new(0x400e8618 as *mut u32, 0); + pub const DAISY_LPSPI4_LPSPI_SDO_SELECT_GPIO_DISP_B2_14: Daisy = + Daisy::new(0x400e8618 as *mut u32, 1); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_PCS_0_SELECT_GPIO_LPSR_03: Daisy = + Daisy::new(0x40c08094 as *mut u32, 0); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_PCS_0_SELECT_GPIO_LPSR_13: Daisy = + Daisy::new(0x40c08094 as *mut u32, 1); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_GPIO_LPSR_02: Daisy = + Daisy::new(0x40c08098 as *mut u32, 0); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_GPIO_LPSR_12: Daisy = + Daisy::new(0x40c08098 as *mut u32, 1); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_GPIO_LPSR_05: Daisy = + Daisy::new(0x40c0809c as *mut u32, 0); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_GPIO_LPSR_15: Daisy = + Daisy::new(0x40c0809c as *mut u32, 1); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_GPIO_LPSR_04: Daisy = + Daisy::new(0x40c080a0 as *mut u32, 0); + pub const DAISY_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_GPIO_LPSR_14: Daisy = + Daisy::new(0x40c080a0 as *mut u32, 1); +} + +use daisy::*; diff --git a/src/imxrt1170/lpuart.rs b/src/imxrt1170/lpuart.rs new file mode 100644 index 0000000..4aafd33 --- /dev/null +++ b/src/imxrt1170/lpuart.rs @@ -0,0 +1,56 @@ +use super::pads::gpio_ad::*; +use crate::{ + consts::*, + lpuart::{Pin, Rx, Tx}, + Daisy, +}; + +// +// UART1 +// +uart!(module: U1, alt: 0, pad: GPIO_AD_24, direction: Tx, daisy: Some(DAISY_LPUART1_LPUART_TXD_SELECT_GPIO_AD_24)); +uart!(module: U1, alt: 0, pad: GPIO_AD_25, direction: Rx, daisy: Some(DAISY_LPUART1_LPUART_RXD_SELECT_GPIO_AD_25)); + +mod daisy { + #![allow(unused)] + use super::Daisy; + + pub const DAISY_LPUART1_LPUART_RXD_SELECT_GPIO_AD_25: Daisy = + Daisy::new(0x400e861c as *mut u32, 0); + pub const DAISY_LPUART1_LPUART_RXD_SELECT_GPIO_DISP_B1_03: Daisy = + Daisy::new(0x400e861c as *mut u32, 1); + pub const DAISY_LPUART1_LPUART_RXD_SELECT_GPIO_DISP_B2_09: Daisy = + Daisy::new(0x400e861c as *mut u32, 2); + pub const DAISY_LPUART1_LPUART_TXD_SELECT_GPIO_AD_24: Daisy = + Daisy::new(0x400e8620 as *mut u32, 0); + pub const DAISY_LPUART1_LPUART_TXD_SELECT_GPIO_DISP_B1_02: Daisy = + Daisy::new(0x400e8620 as *mut u32, 1); + pub const DAISY_LPUART1_LPUART_TXD_SELECT_GPIO_DISP_B2_08: Daisy = + Daisy::new(0x400e8620 as *mut u32, 2); + pub const DAISY_LPUART10_LPUART_RXD_SELECT_GPIO_AD_16: Daisy = + Daisy::new(0x400e8624 as *mut u32, 0); + pub const DAISY_LPUART10_LPUART_RXD_SELECT_GPIO_AD_33: Daisy = + Daisy::new(0x400e8624 as *mut u32, 1); + pub const DAISY_LPUART10_LPUART_TXD_SELECT_GPIO_AD_15: Daisy = + Daisy::new(0x400e8628 as *mut u32, 0); + pub const DAISY_LPUART10_LPUART_TXD_SELECT_GPIO_AD_32: Daisy = + Daisy::new(0x400e8628 as *mut u32, 1); + pub const DAISY_LPUART7_LPUART_RXD_SELECT_GPIO_AD_01: Daisy = + Daisy::new(0x400e862c as *mut u32, 0); + pub const DAISY_LPUART7_LPUART_RXD_SELECT_GPIO_DISP_B2_07: Daisy = + Daisy::new(0x400e862c as *mut u32, 1); + pub const DAISY_LPUART7_LPUART_TXD_SELECT_GPIO_AD_00: Daisy = + Daisy::new(0x400e8630 as *mut u32, 0); + pub const DAISY_LPUART7_LPUART_TXD_SELECT_GPIO_DISP_B2_06: Daisy = + Daisy::new(0x400e8630 as *mut u32, 1); + pub const DAISY_LPUART8_LPUART_RXD_SELECT_GPIO_AD_03: Daisy = + Daisy::new(0x400e8634 as *mut u32, 0); + pub const DAISY_LPUART8_LPUART_RXD_SELECT_GPIO_DISP_B2_09: Daisy = + Daisy::new(0x400e8634 as *mut u32, 1); + pub const DAISY_LPUART8_LPUART_TXD_SELECT_GPIO_AD_02: Daisy = + Daisy::new(0x400e8638 as *mut u32, 0); + pub const DAISY_LPUART8_LPUART_TXD_SELECT_GPIO_DISP_B2_08: Daisy = + Daisy::new(0x400e8638 as *mut u32, 1); +} + +use daisy::*; diff --git a/src/imxrt1170/mod.rs b/src/imxrt1170/mod.rs new file mode 100644 index 0000000..0f59a06 --- /dev/null +++ b/src/imxrt1170/mod.rs @@ -0,0 +1,22 @@ +//! Pads for the i.MX RT 1170 processor family. + +mod pads; +pub use pads::*; + +mod flexpwm; +mod lpi2c; +mod lpspi; +mod lpuart; + +mod ccm { + pub use crate::ccm::{Function, Observable, Pin}; + + impl Pin for super::pads::gpio_emc_b1::GPIO_EMC_B1_40 { + const ALT: u32 = 9; + type Function = Observable<1>; + } + impl Pin for super::pads::gpio_emc_b1::GPIO_EMC_B1_41 { + const ALT: u32 = 9; + type Function = Observable<2>; + } +} diff --git a/src/imxrt1170/pads.rs b/src/imxrt1170/pads.rs new file mode 100644 index 0000000..0c49e51 --- /dev/null +++ b/src/imxrt1170/pads.rs @@ -0,0 +1,2794 @@ +// Generated by iomuxc.py +#![allow(non_camel_case_types)] + +/// Pads with the prefix GPIO_EMC_B1. +pub mod gpio_emc_b1 { + + const GPIO_EMC_B1_00_MUX_ADDR: u32 = 0x400e8010; + const GPIO_EMC_B1_00_PAD_ADDR: u32 = 0x400e8254; + pub type GPIO_EMC_B1_00 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_00 { + const ALT: u32 = 10; + const OFFSET: u32 = 0; + } + + const GPIO_EMC_B1_01_MUX_ADDR: u32 = 0x400e8014; + const GPIO_EMC_B1_01_PAD_ADDR: u32 = 0x400e8258; + pub type GPIO_EMC_B1_01 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_01 { + const ALT: u32 = 10; + const OFFSET: u32 = 1; + } + + const GPIO_EMC_B1_02_MUX_ADDR: u32 = 0x400e8018; + const GPIO_EMC_B1_02_PAD_ADDR: u32 = 0x400e825c; + pub type GPIO_EMC_B1_02 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_02 { + const ALT: u32 = 10; + const OFFSET: u32 = 2; + } + + const GPIO_EMC_B1_03_MUX_ADDR: u32 = 0x400e801c; + const GPIO_EMC_B1_03_PAD_ADDR: u32 = 0x400e8260; + pub type GPIO_EMC_B1_03 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_03 { + const ALT: u32 = 10; + const OFFSET: u32 = 3; + } + + const GPIO_EMC_B1_04_MUX_ADDR: u32 = 0x400e8020; + const GPIO_EMC_B1_04_PAD_ADDR: u32 = 0x400e8264; + pub type GPIO_EMC_B1_04 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_04 { + const ALT: u32 = 10; + const OFFSET: u32 = 4; + } + + const GPIO_EMC_B1_05_MUX_ADDR: u32 = 0x400e8024; + const GPIO_EMC_B1_05_PAD_ADDR: u32 = 0x400e8268; + pub type GPIO_EMC_B1_05 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_05 { + const ALT: u32 = 10; + const OFFSET: u32 = 5; + } + + const GPIO_EMC_B1_06_MUX_ADDR: u32 = 0x400e8028; + const GPIO_EMC_B1_06_PAD_ADDR: u32 = 0x400e826c; + pub type GPIO_EMC_B1_06 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_06 { + const ALT: u32 = 10; + const OFFSET: u32 = 6; + } + + const GPIO_EMC_B1_07_MUX_ADDR: u32 = 0x400e802c; + const GPIO_EMC_B1_07_PAD_ADDR: u32 = 0x400e8270; + pub type GPIO_EMC_B1_07 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_07 { + const ALT: u32 = 10; + const OFFSET: u32 = 7; + } + + const GPIO_EMC_B1_08_MUX_ADDR: u32 = 0x400e8030; + const GPIO_EMC_B1_08_PAD_ADDR: u32 = 0x400e8274; + pub type GPIO_EMC_B1_08 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_08 { + const ALT: u32 = 10; + const OFFSET: u32 = 8; + } + + const GPIO_EMC_B1_09_MUX_ADDR: u32 = 0x400e8034; + const GPIO_EMC_B1_09_PAD_ADDR: u32 = 0x400e8278; + pub type GPIO_EMC_B1_09 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_09 { + const ALT: u32 = 10; + const OFFSET: u32 = 9; + } + + const GPIO_EMC_B1_10_MUX_ADDR: u32 = 0x400e8038; + const GPIO_EMC_B1_10_PAD_ADDR: u32 = 0x400e827c; + pub type GPIO_EMC_B1_10 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_10 { + const ALT: u32 = 10; + const OFFSET: u32 = 10; + } + + const GPIO_EMC_B1_11_MUX_ADDR: u32 = 0x400e803c; + const GPIO_EMC_B1_11_PAD_ADDR: u32 = 0x400e8280; + pub type GPIO_EMC_B1_11 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_11 { + const ALT: u32 = 10; + const OFFSET: u32 = 11; + } + + const GPIO_EMC_B1_12_MUX_ADDR: u32 = 0x400e8040; + const GPIO_EMC_B1_12_PAD_ADDR: u32 = 0x400e8284; + pub type GPIO_EMC_B1_12 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_12 { + const ALT: u32 = 10; + const OFFSET: u32 = 12; + } + + const GPIO_EMC_B1_13_MUX_ADDR: u32 = 0x400e8044; + const GPIO_EMC_B1_13_PAD_ADDR: u32 = 0x400e8288; + pub type GPIO_EMC_B1_13 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_13 { + const ALT: u32 = 10; + const OFFSET: u32 = 13; + } + + const GPIO_EMC_B1_14_MUX_ADDR: u32 = 0x400e8048; + const GPIO_EMC_B1_14_PAD_ADDR: u32 = 0x400e828c; + pub type GPIO_EMC_B1_14 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_14 { + const ALT: u32 = 10; + const OFFSET: u32 = 14; + } + + const GPIO_EMC_B1_15_MUX_ADDR: u32 = 0x400e804c; + const GPIO_EMC_B1_15_PAD_ADDR: u32 = 0x400e8290; + pub type GPIO_EMC_B1_15 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_15 { + const ALT: u32 = 10; + const OFFSET: u32 = 15; + } + + const GPIO_EMC_B1_16_MUX_ADDR: u32 = 0x400e8050; + const GPIO_EMC_B1_16_PAD_ADDR: u32 = 0x400e8294; + pub type GPIO_EMC_B1_16 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_16 { + const ALT: u32 = 10; + const OFFSET: u32 = 16; + } + + const GPIO_EMC_B1_17_MUX_ADDR: u32 = 0x400e8054; + const GPIO_EMC_B1_17_PAD_ADDR: u32 = 0x400e8298; + pub type GPIO_EMC_B1_17 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_17 { + const ALT: u32 = 10; + const OFFSET: u32 = 17; + } + + const GPIO_EMC_B1_18_MUX_ADDR: u32 = 0x400e8058; + const GPIO_EMC_B1_18_PAD_ADDR: u32 = 0x400e829c; + pub type GPIO_EMC_B1_18 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_18 { + const ALT: u32 = 10; + const OFFSET: u32 = 18; + } + + const GPIO_EMC_B1_19_MUX_ADDR: u32 = 0x400e805c; + const GPIO_EMC_B1_19_PAD_ADDR: u32 = 0x400e82a0; + pub type GPIO_EMC_B1_19 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_19 { + const ALT: u32 = 10; + const OFFSET: u32 = 19; + } + + const GPIO_EMC_B1_20_MUX_ADDR: u32 = 0x400e8060; + const GPIO_EMC_B1_20_PAD_ADDR: u32 = 0x400e82a4; + pub type GPIO_EMC_B1_20 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_20 { + const ALT: u32 = 10; + const OFFSET: u32 = 20; + } + + const GPIO_EMC_B1_21_MUX_ADDR: u32 = 0x400e8064; + const GPIO_EMC_B1_21_PAD_ADDR: u32 = 0x400e82a8; + pub type GPIO_EMC_B1_21 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_21 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_21 { + const ALT: u32 = 10; + const OFFSET: u32 = 21; + } + + const GPIO_EMC_B1_22_MUX_ADDR: u32 = 0x400e8068; + const GPIO_EMC_B1_22_PAD_ADDR: u32 = 0x400e82ac; + pub type GPIO_EMC_B1_22 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_22 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_22 { + const ALT: u32 = 10; + const OFFSET: u32 = 22; + } + + const GPIO_EMC_B1_23_MUX_ADDR: u32 = 0x400e806c; + const GPIO_EMC_B1_23_PAD_ADDR: u32 = 0x400e82b0; + pub type GPIO_EMC_B1_23 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_23 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_23 { + const ALT: u32 = 10; + const OFFSET: u32 = 23; + } + + const GPIO_EMC_B1_24_MUX_ADDR: u32 = 0x400e8070; + const GPIO_EMC_B1_24_PAD_ADDR: u32 = 0x400e82b4; + pub type GPIO_EMC_B1_24 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_24 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_24 { + const ALT: u32 = 10; + const OFFSET: u32 = 24; + } + + const GPIO_EMC_B1_25_MUX_ADDR: u32 = 0x400e8074; + const GPIO_EMC_B1_25_PAD_ADDR: u32 = 0x400e82b8; + pub type GPIO_EMC_B1_25 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_25 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_25 { + const ALT: u32 = 10; + const OFFSET: u32 = 25; + } + + const GPIO_EMC_B1_26_MUX_ADDR: u32 = 0x400e8078; + const GPIO_EMC_B1_26_PAD_ADDR: u32 = 0x400e82bc; + pub type GPIO_EMC_B1_26 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_26 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_26 { + const ALT: u32 = 10; + const OFFSET: u32 = 26; + } + + const GPIO_EMC_B1_27_MUX_ADDR: u32 = 0x400e807c; + const GPIO_EMC_B1_27_PAD_ADDR: u32 = 0x400e82c0; + pub type GPIO_EMC_B1_27 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_27 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_27 { + const ALT: u32 = 10; + const OFFSET: u32 = 27; + } + + const GPIO_EMC_B1_28_MUX_ADDR: u32 = 0x400e8080; + const GPIO_EMC_B1_28_PAD_ADDR: u32 = 0x400e82c4; + pub type GPIO_EMC_B1_28 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_28 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_28 { + const ALT: u32 = 10; + const OFFSET: u32 = 28; + } + + const GPIO_EMC_B1_29_MUX_ADDR: u32 = 0x400e8084; + const GPIO_EMC_B1_29_PAD_ADDR: u32 = 0x400e82c8; + pub type GPIO_EMC_B1_29 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_29 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_29 { + const ALT: u32 = 10; + const OFFSET: u32 = 29; + } + + const GPIO_EMC_B1_30_MUX_ADDR: u32 = 0x400e8088; + const GPIO_EMC_B1_30_PAD_ADDR: u32 = 0x400e82cc; + pub type GPIO_EMC_B1_30 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_30 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_30 { + const ALT: u32 = 10; + const OFFSET: u32 = 30; + } + + const GPIO_EMC_B1_31_MUX_ADDR: u32 = 0x400e808c; + const GPIO_EMC_B1_31_PAD_ADDR: u32 = 0x400e82d0; + pub type GPIO_EMC_B1_31 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_EMC_B1_31 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + impl crate::gpio::Pin<7> for GPIO_EMC_B1_31 { + const ALT: u32 = 10; + const OFFSET: u32 = 31; + } + + const GPIO_EMC_B1_32_MUX_ADDR: u32 = 0x400e8090; + const GPIO_EMC_B1_32_PAD_ADDR: u32 = 0x400e82d4; + pub type GPIO_EMC_B1_32 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_32 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_32 { + const ALT: u32 = 10; + const OFFSET: u32 = 0; + } + + const GPIO_EMC_B1_33_MUX_ADDR: u32 = 0x400e8094; + const GPIO_EMC_B1_33_PAD_ADDR: u32 = 0x400e82d8; + pub type GPIO_EMC_B1_33 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_33 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_33 { + const ALT: u32 = 10; + const OFFSET: u32 = 1; + } + + const GPIO_EMC_B1_34_MUX_ADDR: u32 = 0x400e8098; + const GPIO_EMC_B1_34_PAD_ADDR: u32 = 0x400e82dc; + pub type GPIO_EMC_B1_34 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_34 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_34 { + const ALT: u32 = 10; + const OFFSET: u32 = 2; + } + + const GPIO_EMC_B1_35_MUX_ADDR: u32 = 0x400e809c; + const GPIO_EMC_B1_35_PAD_ADDR: u32 = 0x400e82e0; + pub type GPIO_EMC_B1_35 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_35 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_35 { + const ALT: u32 = 10; + const OFFSET: u32 = 3; + } + + const GPIO_EMC_B1_36_MUX_ADDR: u32 = 0x400e80a0; + const GPIO_EMC_B1_36_PAD_ADDR: u32 = 0x400e82e4; + pub type GPIO_EMC_B1_36 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_36 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_36 { + const ALT: u32 = 10; + const OFFSET: u32 = 4; + } + + const GPIO_EMC_B1_37_MUX_ADDR: u32 = 0x400e80a4; + const GPIO_EMC_B1_37_PAD_ADDR: u32 = 0x400e82e8; + pub type GPIO_EMC_B1_37 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_37 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_37 { + const ALT: u32 = 10; + const OFFSET: u32 = 5; + } + + const GPIO_EMC_B1_38_MUX_ADDR: u32 = 0x400e80a8; + const GPIO_EMC_B1_38_PAD_ADDR: u32 = 0x400e82ec; + pub type GPIO_EMC_B1_38 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_38 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_38 { + const ALT: u32 = 10; + const OFFSET: u32 = 6; + } + + const GPIO_EMC_B1_39_MUX_ADDR: u32 = 0x400e80ac; + const GPIO_EMC_B1_39_PAD_ADDR: u32 = 0x400e82f0; + pub type GPIO_EMC_B1_39 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_39 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_39 { + const ALT: u32 = 10; + const OFFSET: u32 = 7; + } + + const GPIO_EMC_B1_40_MUX_ADDR: u32 = 0x400e80b0; + const GPIO_EMC_B1_40_PAD_ADDR: u32 = 0x400e82f4; + pub type GPIO_EMC_B1_40 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_40 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_40 { + const ALT: u32 = 10; + const OFFSET: u32 = 8; + } + + const GPIO_EMC_B1_41_MUX_ADDR: u32 = 0x400e80b4; + const GPIO_EMC_B1_41_PAD_ADDR: u32 = 0x400e82f8; + pub type GPIO_EMC_B1_41 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_41 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B1_41 { + const ALT: u32 = 10; + const OFFSET: u32 = 9; + } + + /// All pads with prefix GPIO_EMC_B1. + pub struct Pads { + pub p00: GPIO_EMC_B1_00, + pub p01: GPIO_EMC_B1_01, + pub p02: GPIO_EMC_B1_02, + pub p03: GPIO_EMC_B1_03, + pub p04: GPIO_EMC_B1_04, + pub p05: GPIO_EMC_B1_05, + pub p06: GPIO_EMC_B1_06, + pub p07: GPIO_EMC_B1_07, + pub p08: GPIO_EMC_B1_08, + pub p09: GPIO_EMC_B1_09, + pub p10: GPIO_EMC_B1_10, + pub p11: GPIO_EMC_B1_11, + pub p12: GPIO_EMC_B1_12, + pub p13: GPIO_EMC_B1_13, + pub p14: GPIO_EMC_B1_14, + pub p15: GPIO_EMC_B1_15, + pub p16: GPIO_EMC_B1_16, + pub p17: GPIO_EMC_B1_17, + pub p18: GPIO_EMC_B1_18, + pub p19: GPIO_EMC_B1_19, + pub p20: GPIO_EMC_B1_20, + pub p21: GPIO_EMC_B1_21, + pub p22: GPIO_EMC_B1_22, + pub p23: GPIO_EMC_B1_23, + pub p24: GPIO_EMC_B1_24, + pub p25: GPIO_EMC_B1_25, + pub p26: GPIO_EMC_B1_26, + pub p27: GPIO_EMC_B1_27, + pub p28: GPIO_EMC_B1_28, + pub p29: GPIO_EMC_B1_29, + pub p30: GPIO_EMC_B1_30, + pub p31: GPIO_EMC_B1_31, + pub p32: GPIO_EMC_B1_32, + pub p33: GPIO_EMC_B1_33, + pub p34: GPIO_EMC_B1_34, + pub p35: GPIO_EMC_B1_35, + pub p36: GPIO_EMC_B1_36, + pub p37: GPIO_EMC_B1_37, + pub p38: GPIO_EMC_B1_38, + pub p39: GPIO_EMC_B1_39, + pub p40: GPIO_EMC_B1_40, + pub p41: GPIO_EMC_B1_41, + } + /// Erased pads with prefix GPIO_EMC_B1. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 42]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_EMC_B1_00::new(), + p01: GPIO_EMC_B1_01::new(), + p02: GPIO_EMC_B1_02::new(), + p03: GPIO_EMC_B1_03::new(), + p04: GPIO_EMC_B1_04::new(), + p05: GPIO_EMC_B1_05::new(), + p06: GPIO_EMC_B1_06::new(), + p07: GPIO_EMC_B1_07::new(), + p08: GPIO_EMC_B1_08::new(), + p09: GPIO_EMC_B1_09::new(), + p10: GPIO_EMC_B1_10::new(), + p11: GPIO_EMC_B1_11::new(), + p12: GPIO_EMC_B1_12::new(), + p13: GPIO_EMC_B1_13::new(), + p14: GPIO_EMC_B1_14::new(), + p15: GPIO_EMC_B1_15::new(), + p16: GPIO_EMC_B1_16::new(), + p17: GPIO_EMC_B1_17::new(), + p18: GPIO_EMC_B1_18::new(), + p19: GPIO_EMC_B1_19::new(), + p20: GPIO_EMC_B1_20::new(), + p21: GPIO_EMC_B1_21::new(), + p22: GPIO_EMC_B1_22::new(), + p23: GPIO_EMC_B1_23::new(), + p24: GPIO_EMC_B1_24::new(), + p25: GPIO_EMC_B1_25::new(), + p26: GPIO_EMC_B1_26::new(), + p27: GPIO_EMC_B1_27::new(), + p28: GPIO_EMC_B1_28::new(), + p29: GPIO_EMC_B1_29::new(), + p30: GPIO_EMC_B1_30::new(), + p31: GPIO_EMC_B1_31::new(), + p32: GPIO_EMC_B1_32::new(), + p33: GPIO_EMC_B1_33::new(), + p34: GPIO_EMC_B1_34::new(), + p35: GPIO_EMC_B1_35::new(), + p36: GPIO_EMC_B1_36::new(), + p37: GPIO_EMC_B1_37::new(), + p38: GPIO_EMC_B1_38::new(), + p39: GPIO_EMC_B1_39::new(), + p40: GPIO_EMC_B1_40::new(), + p41: GPIO_EMC_B1_41::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + self.p21.erase(), + self.p22.erase(), + self.p23.erase(), + self.p24.erase(), + self.p25.erase(), + self.p26.erase(), + self.p27.erase(), + self.p28.erase(), + self.p29.erase(), + self.p30.erase(), + self.p31.erase(), + self.p32.erase(), + self.p33.erase(), + self.p34.erase(), + self.p35.erase(), + self.p36.erase(), + self.p37.erase(), + self.p38.erase(), + self.p39.erase(), + self.p40.erase(), + self.p41.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_EMC_B2. +pub mod gpio_emc_b2 { + + const GPIO_EMC_B2_00_MUX_ADDR: u32 = 0x400e80b8; + const GPIO_EMC_B2_00_PAD_ADDR: u32 = 0x400e82fc; + pub type GPIO_EMC_B2_00 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_00 { + const ALT: u32 = 10; + const OFFSET: u32 = 10; + } + + const GPIO_EMC_B2_01_MUX_ADDR: u32 = 0x400e80bc; + const GPIO_EMC_B2_01_PAD_ADDR: u32 = 0x400e8300; + pub type GPIO_EMC_B2_01 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_01 { + const ALT: u32 = 10; + const OFFSET: u32 = 11; + } + + const GPIO_EMC_B2_02_MUX_ADDR: u32 = 0x400e80c0; + const GPIO_EMC_B2_02_PAD_ADDR: u32 = 0x400e8304; + pub type GPIO_EMC_B2_02 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_02 { + const ALT: u32 = 10; + const OFFSET: u32 = 12; + } + + const GPIO_EMC_B2_03_MUX_ADDR: u32 = 0x400e80c4; + const GPIO_EMC_B2_03_PAD_ADDR: u32 = 0x400e8308; + pub type GPIO_EMC_B2_03 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_03 { + const ALT: u32 = 10; + const OFFSET: u32 = 13; + } + + const GPIO_EMC_B2_04_MUX_ADDR: u32 = 0x400e80c8; + const GPIO_EMC_B2_04_PAD_ADDR: u32 = 0x400e830c; + pub type GPIO_EMC_B2_04 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_04 { + const ALT: u32 = 10; + const OFFSET: u32 = 14; + } + + const GPIO_EMC_B2_05_MUX_ADDR: u32 = 0x400e80cc; + const GPIO_EMC_B2_05_PAD_ADDR: u32 = 0x400e8310; + pub type GPIO_EMC_B2_05 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_05 { + const ALT: u32 = 10; + const OFFSET: u32 = 15; + } + + const GPIO_EMC_B2_06_MUX_ADDR: u32 = 0x400e80d0; + const GPIO_EMC_B2_06_PAD_ADDR: u32 = 0x400e8314; + pub type GPIO_EMC_B2_06 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_06 { + const ALT: u32 = 10; + const OFFSET: u32 = 16; + } + + const GPIO_EMC_B2_07_MUX_ADDR: u32 = 0x400e80d4; + const GPIO_EMC_B2_07_PAD_ADDR: u32 = 0x400e8318; + pub type GPIO_EMC_B2_07 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_07 { + const ALT: u32 = 10; + const OFFSET: u32 = 17; + } + + const GPIO_EMC_B2_08_MUX_ADDR: u32 = 0x400e80d8; + const GPIO_EMC_B2_08_PAD_ADDR: u32 = 0x400e831c; + pub type GPIO_EMC_B2_08 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_08 { + const ALT: u32 = 10; + const OFFSET: u32 = 18; + } + + const GPIO_EMC_B2_09_MUX_ADDR: u32 = 0x400e80dc; + const GPIO_EMC_B2_09_PAD_ADDR: u32 = 0x400e8320; + pub type GPIO_EMC_B2_09 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_09 { + const ALT: u32 = 10; + const OFFSET: u32 = 19; + } + + const GPIO_EMC_B2_10_MUX_ADDR: u32 = 0x400e80e0; + const GPIO_EMC_B2_10_PAD_ADDR: u32 = 0x400e8324; + pub type GPIO_EMC_B2_10 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_10 { + const ALT: u32 = 10; + const OFFSET: u32 = 20; + } + + const GPIO_EMC_B2_11_MUX_ADDR: u32 = 0x400e80e4; + const GPIO_EMC_B2_11_PAD_ADDR: u32 = 0x400e8328; + pub type GPIO_EMC_B2_11 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_11 { + const ALT: u32 = 10; + const OFFSET: u32 = 21; + } + + const GPIO_EMC_B2_12_MUX_ADDR: u32 = 0x400e80e8; + const GPIO_EMC_B2_12_PAD_ADDR: u32 = 0x400e832c; + pub type GPIO_EMC_B2_12 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_12 { + const ALT: u32 = 10; + const OFFSET: u32 = 22; + } + + const GPIO_EMC_B2_13_MUX_ADDR: u32 = 0x400e80ec; + const GPIO_EMC_B2_13_PAD_ADDR: u32 = 0x400e8330; + pub type GPIO_EMC_B2_13 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_13 { + const ALT: u32 = 10; + const OFFSET: u32 = 23; + } + + const GPIO_EMC_B2_14_MUX_ADDR: u32 = 0x400e80f0; + const GPIO_EMC_B2_14_PAD_ADDR: u32 = 0x400e8334; + pub type GPIO_EMC_B2_14 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_14 { + const ALT: u32 = 10; + const OFFSET: u32 = 24; + } + + const GPIO_EMC_B2_15_MUX_ADDR: u32 = 0x400e80f4; + const GPIO_EMC_B2_15_PAD_ADDR: u32 = 0x400e8338; + pub type GPIO_EMC_B2_15 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_15 { + const ALT: u32 = 10; + const OFFSET: u32 = 25; + } + + const GPIO_EMC_B2_16_MUX_ADDR: u32 = 0x400e80f8; + const GPIO_EMC_B2_16_PAD_ADDR: u32 = 0x400e833c; + pub type GPIO_EMC_B2_16 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_16 { + const ALT: u32 = 10; + const OFFSET: u32 = 26; + } + + const GPIO_EMC_B2_17_MUX_ADDR: u32 = 0x400e80fc; + const GPIO_EMC_B2_17_PAD_ADDR: u32 = 0x400e8340; + pub type GPIO_EMC_B2_17 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_17 { + const ALT: u32 = 10; + const OFFSET: u32 = 27; + } + + const GPIO_EMC_B2_18_MUX_ADDR: u32 = 0x400e8100; + const GPIO_EMC_B2_18_PAD_ADDR: u32 = 0x400e8344; + pub type GPIO_EMC_B2_18 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_18 { + const ALT: u32 = 10; + const OFFSET: u32 = 28; + } + + const GPIO_EMC_B2_19_MUX_ADDR: u32 = 0x400e8104; + const GPIO_EMC_B2_19_PAD_ADDR: u32 = 0x400e8348; + pub type GPIO_EMC_B2_19 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_19 { + const ALT: u32 = 10; + const OFFSET: u32 = 29; + } + + const GPIO_EMC_B2_20_MUX_ADDR: u32 = 0x400e8108; + const GPIO_EMC_B2_20_PAD_ADDR: u32 = 0x400e834c; + pub type GPIO_EMC_B2_20 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B2_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + impl crate::gpio::Pin<8> for GPIO_EMC_B2_20 { + const ALT: u32 = 10; + const OFFSET: u32 = 30; + } + + /// All pads with prefix GPIO_EMC_B2. + pub struct Pads { + pub p00: GPIO_EMC_B2_00, + pub p01: GPIO_EMC_B2_01, + pub p02: GPIO_EMC_B2_02, + pub p03: GPIO_EMC_B2_03, + pub p04: GPIO_EMC_B2_04, + pub p05: GPIO_EMC_B2_05, + pub p06: GPIO_EMC_B2_06, + pub p07: GPIO_EMC_B2_07, + pub p08: GPIO_EMC_B2_08, + pub p09: GPIO_EMC_B2_09, + pub p10: GPIO_EMC_B2_10, + pub p11: GPIO_EMC_B2_11, + pub p12: GPIO_EMC_B2_12, + pub p13: GPIO_EMC_B2_13, + pub p14: GPIO_EMC_B2_14, + pub p15: GPIO_EMC_B2_15, + pub p16: GPIO_EMC_B2_16, + pub p17: GPIO_EMC_B2_17, + pub p18: GPIO_EMC_B2_18, + pub p19: GPIO_EMC_B2_19, + pub p20: GPIO_EMC_B2_20, + } + /// Erased pads with prefix GPIO_EMC_B2. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 21]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_EMC_B2_00::new(), + p01: GPIO_EMC_B2_01::new(), + p02: GPIO_EMC_B2_02::new(), + p03: GPIO_EMC_B2_03::new(), + p04: GPIO_EMC_B2_04::new(), + p05: GPIO_EMC_B2_05::new(), + p06: GPIO_EMC_B2_06::new(), + p07: GPIO_EMC_B2_07::new(), + p08: GPIO_EMC_B2_08::new(), + p09: GPIO_EMC_B2_09::new(), + p10: GPIO_EMC_B2_10::new(), + p11: GPIO_EMC_B2_11::new(), + p12: GPIO_EMC_B2_12::new(), + p13: GPIO_EMC_B2_13::new(), + p14: GPIO_EMC_B2_14::new(), + p15: GPIO_EMC_B2_15::new(), + p16: GPIO_EMC_B2_16::new(), + p17: GPIO_EMC_B2_17::new(), + p18: GPIO_EMC_B2_18::new(), + p19: GPIO_EMC_B2_19::new(), + p20: GPIO_EMC_B2_20::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_AD. +pub mod gpio_ad { + + const GPIO_AD_00_MUX_ADDR: u32 = 0x400e810c; + const GPIO_AD_00_PAD_ADDR: u32 = 0x400e8350; + pub type GPIO_AD_00 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_AD_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + impl crate::gpio::Pin<8> for GPIO_AD_00 { + const ALT: u32 = 10; + const OFFSET: u32 = 31; + } + + const GPIO_AD_01_MUX_ADDR: u32 = 0x400e8110; + const GPIO_AD_01_PAD_ADDR: u32 = 0x400e8354; + pub type GPIO_AD_01 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_01 { + const ALT: u32 = 10; + const OFFSET: u32 = 0; + } + + const GPIO_AD_02_MUX_ADDR: u32 = 0x400e8114; + const GPIO_AD_02_PAD_ADDR: u32 = 0x400e8358; + pub type GPIO_AD_02 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_02 { + const ALT: u32 = 10; + const OFFSET: u32 = 1; + } + + const GPIO_AD_03_MUX_ADDR: u32 = 0x400e8118; + const GPIO_AD_03_PAD_ADDR: u32 = 0x400e835c; + pub type GPIO_AD_03 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_03 { + const ALT: u32 = 10; + const OFFSET: u32 = 2; + } + + const GPIO_AD_04_MUX_ADDR: u32 = 0x400e811c; + const GPIO_AD_04_PAD_ADDR: u32 = 0x400e8360; + pub type GPIO_AD_04 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_04 { + const ALT: u32 = 10; + const OFFSET: u32 = 3; + } + + const GPIO_AD_05_MUX_ADDR: u32 = 0x400e8120; + const GPIO_AD_05_PAD_ADDR: u32 = 0x400e8364; + pub type GPIO_AD_05 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_05 { + const ALT: u32 = 10; + const OFFSET: u32 = 4; + } + + const GPIO_AD_06_MUX_ADDR: u32 = 0x400e8124; + const GPIO_AD_06_PAD_ADDR: u32 = 0x400e8368; + pub type GPIO_AD_06 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_06 { + const ALT: u32 = 10; + const OFFSET: u32 = 5; + } + + const GPIO_AD_07_MUX_ADDR: u32 = 0x400e8128; + const GPIO_AD_07_PAD_ADDR: u32 = 0x400e836c; + pub type GPIO_AD_07 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_07 { + const ALT: u32 = 10; + const OFFSET: u32 = 6; + } + + const GPIO_AD_08_MUX_ADDR: u32 = 0x400e812c; + const GPIO_AD_08_PAD_ADDR: u32 = 0x400e8370; + pub type GPIO_AD_08 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_08 { + const ALT: u32 = 10; + const OFFSET: u32 = 7; + } + + const GPIO_AD_09_MUX_ADDR: u32 = 0x400e8130; + const GPIO_AD_09_PAD_ADDR: u32 = 0x400e8374; + pub type GPIO_AD_09 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_09 { + const ALT: u32 = 10; + const OFFSET: u32 = 8; + } + + const GPIO_AD_10_MUX_ADDR: u32 = 0x400e8134; + const GPIO_AD_10_PAD_ADDR: u32 = 0x400e8378; + pub type GPIO_AD_10 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + impl crate::gpio::Pin<9> for GPIO_AD_10 { + const ALT: u32 = 10; + const OFFSET: u32 = 9; + } + + const GPIO_AD_11_MUX_ADDR: u32 = 0x400e8138; + const GPIO_AD_11_PAD_ADDR: u32 = 0x400e837c; + pub type GPIO_AD_11 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_11 { + const ALT: u32 = 10; + const OFFSET: u32 = 10; + } + + const GPIO_AD_12_MUX_ADDR: u32 = 0x400e813c; + const GPIO_AD_12_PAD_ADDR: u32 = 0x400e8380; + pub type GPIO_AD_12 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_12 { + const ALT: u32 = 10; + const OFFSET: u32 = 11; + } + + const GPIO_AD_13_MUX_ADDR: u32 = 0x400e8140; + const GPIO_AD_13_PAD_ADDR: u32 = 0x400e8384; + pub type GPIO_AD_13 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_13 { + const ALT: u32 = 10; + const OFFSET: u32 = 12; + } + + const GPIO_AD_14_MUX_ADDR: u32 = 0x400e8144; + const GPIO_AD_14_PAD_ADDR: u32 = 0x400e8388; + pub type GPIO_AD_14 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_14 { + const ALT: u32 = 10; + const OFFSET: u32 = 13; + } + + const GPIO_AD_15_MUX_ADDR: u32 = 0x400e8148; + const GPIO_AD_15_PAD_ADDR: u32 = 0x400e838c; + pub type GPIO_AD_15 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_15 { + const ALT: u32 = 10; + const OFFSET: u32 = 14; + } + + const GPIO_AD_16_MUX_ADDR: u32 = 0x400e814c; + const GPIO_AD_16_PAD_ADDR: u32 = 0x400e8390; + pub type GPIO_AD_16 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_16 { + const ALT: u32 = 10; + const OFFSET: u32 = 15; + } + + const GPIO_AD_17_MUX_ADDR: u32 = 0x400e8150; + const GPIO_AD_17_PAD_ADDR: u32 = 0x400e8394; + pub type GPIO_AD_17 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_17 { + const ALT: u32 = 10; + const OFFSET: u32 = 16; + } + + const GPIO_AD_18_MUX_ADDR: u32 = 0x400e8154; + const GPIO_AD_18_PAD_ADDR: u32 = 0x400e8398; + pub type GPIO_AD_18 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_18 { + const ALT: u32 = 10; + const OFFSET: u32 = 17; + } + + const GPIO_AD_19_MUX_ADDR: u32 = 0x400e8158; + const GPIO_AD_19_PAD_ADDR: u32 = 0x400e839c; + pub type GPIO_AD_19 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_19 { + const ALT: u32 = 10; + const OFFSET: u32 = 18; + } + + const GPIO_AD_20_MUX_ADDR: u32 = 0x400e815c; + const GPIO_AD_20_PAD_ADDR: u32 = 0x400e83a0; + pub type GPIO_AD_20 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + impl crate::gpio::Pin<9> for GPIO_AD_20 { + const ALT: u32 = 10; + const OFFSET: u32 = 19; + } + + const GPIO_AD_21_MUX_ADDR: u32 = 0x400e8160; + const GPIO_AD_21_PAD_ADDR: u32 = 0x400e83a4; + pub type GPIO_AD_21 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_21 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_21 { + const ALT: u32 = 10; + const OFFSET: u32 = 20; + } + + const GPIO_AD_22_MUX_ADDR: u32 = 0x400e8164; + const GPIO_AD_22_PAD_ADDR: u32 = 0x400e83a8; + pub type GPIO_AD_22 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_22 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_22 { + const ALT: u32 = 10; + const OFFSET: u32 = 21; + } + + const GPIO_AD_23_MUX_ADDR: u32 = 0x400e8168; + const GPIO_AD_23_PAD_ADDR: u32 = 0x400e83ac; + pub type GPIO_AD_23 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_23 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_23 { + const ALT: u32 = 10; + const OFFSET: u32 = 22; + } + + const GPIO_AD_24_MUX_ADDR: u32 = 0x400e816c; + const GPIO_AD_24_PAD_ADDR: u32 = 0x400e83b0; + pub type GPIO_AD_24 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_24 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_24 { + const ALT: u32 = 10; + const OFFSET: u32 = 23; + } + + const GPIO_AD_25_MUX_ADDR: u32 = 0x400e8170; + const GPIO_AD_25_PAD_ADDR: u32 = 0x400e83b4; + pub type GPIO_AD_25 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_25 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_25 { + const ALT: u32 = 10; + const OFFSET: u32 = 24; + } + + const GPIO_AD_26_MUX_ADDR: u32 = 0x400e8174; + const GPIO_AD_26_PAD_ADDR: u32 = 0x400e83b8; + pub type GPIO_AD_26 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_26 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_26 { + const ALT: u32 = 10; + const OFFSET: u32 = 25; + } + + const GPIO_AD_27_MUX_ADDR: u32 = 0x400e8178; + const GPIO_AD_27_PAD_ADDR: u32 = 0x400e83bc; + pub type GPIO_AD_27 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_27 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_27 { + const ALT: u32 = 10; + const OFFSET: u32 = 26; + } + + const GPIO_AD_28_MUX_ADDR: u32 = 0x400e817c; + const GPIO_AD_28_PAD_ADDR: u32 = 0x400e83c0; + pub type GPIO_AD_28 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_28 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_28 { + const ALT: u32 = 10; + const OFFSET: u32 = 27; + } + + const GPIO_AD_29_MUX_ADDR: u32 = 0x400e8180; + const GPIO_AD_29_PAD_ADDR: u32 = 0x400e83c4; + pub type GPIO_AD_29 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_29 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_29 { + const ALT: u32 = 10; + const OFFSET: u32 = 28; + } + + const GPIO_AD_30_MUX_ADDR: u32 = 0x400e8184; + const GPIO_AD_30_PAD_ADDR: u32 = 0x400e83c8; + pub type GPIO_AD_30 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_30 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + impl crate::gpio::Pin<9> for GPIO_AD_30 { + const ALT: u32 = 10; + const OFFSET: u32 = 29; + } + + const GPIO_AD_31_MUX_ADDR: u32 = 0x400e8188; + const GPIO_AD_31_PAD_ADDR: u32 = 0x400e83cc; + pub type GPIO_AD_31 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_31 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + impl crate::gpio::Pin<9> for GPIO_AD_31 { + const ALT: u32 = 10; + const OFFSET: u32 = 30; + } + + const GPIO_AD_32_MUX_ADDR: u32 = 0x400e818c; + const GPIO_AD_32_PAD_ADDR: u32 = 0x400e83d0; + pub type GPIO_AD_32 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_AD_32 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + impl crate::gpio::Pin<9> for GPIO_AD_32 { + const ALT: u32 = 10; + const OFFSET: u32 = 31; + } + + const GPIO_AD_33_MUX_ADDR: u32 = 0x400e8190; + const GPIO_AD_33_PAD_ADDR: u32 = 0x400e83d4; + pub type GPIO_AD_33 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_33 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_AD_34_MUX_ADDR: u32 = 0x400e8194; + const GPIO_AD_34_PAD_ADDR: u32 = 0x400e83d8; + pub type GPIO_AD_34 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_34 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_AD_35_MUX_ADDR: u32 = 0x400e8198; + const GPIO_AD_35_PAD_ADDR: u32 = 0x400e83dc; + pub type GPIO_AD_35 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_35 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + /// All pads with prefix GPIO_AD. + pub struct Pads { + pub p00: GPIO_AD_00, + pub p01: GPIO_AD_01, + pub p02: GPIO_AD_02, + pub p03: GPIO_AD_03, + pub p04: GPIO_AD_04, + pub p05: GPIO_AD_05, + pub p06: GPIO_AD_06, + pub p07: GPIO_AD_07, + pub p08: GPIO_AD_08, + pub p09: GPIO_AD_09, + pub p10: GPIO_AD_10, + pub p11: GPIO_AD_11, + pub p12: GPIO_AD_12, + pub p13: GPIO_AD_13, + pub p14: GPIO_AD_14, + pub p15: GPIO_AD_15, + pub p16: GPIO_AD_16, + pub p17: GPIO_AD_17, + pub p18: GPIO_AD_18, + pub p19: GPIO_AD_19, + pub p20: GPIO_AD_20, + pub p21: GPIO_AD_21, + pub p22: GPIO_AD_22, + pub p23: GPIO_AD_23, + pub p24: GPIO_AD_24, + pub p25: GPIO_AD_25, + pub p26: GPIO_AD_26, + pub p27: GPIO_AD_27, + pub p28: GPIO_AD_28, + pub p29: GPIO_AD_29, + pub p30: GPIO_AD_30, + pub p31: GPIO_AD_31, + pub p32: GPIO_AD_32, + pub p33: GPIO_AD_33, + pub p34: GPIO_AD_34, + pub p35: GPIO_AD_35, + } + /// Erased pads with prefix GPIO_AD. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 36]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_AD_00::new(), + p01: GPIO_AD_01::new(), + p02: GPIO_AD_02::new(), + p03: GPIO_AD_03::new(), + p04: GPIO_AD_04::new(), + p05: GPIO_AD_05::new(), + p06: GPIO_AD_06::new(), + p07: GPIO_AD_07::new(), + p08: GPIO_AD_08::new(), + p09: GPIO_AD_09::new(), + p10: GPIO_AD_10::new(), + p11: GPIO_AD_11::new(), + p12: GPIO_AD_12::new(), + p13: GPIO_AD_13::new(), + p14: GPIO_AD_14::new(), + p15: GPIO_AD_15::new(), + p16: GPIO_AD_16::new(), + p17: GPIO_AD_17::new(), + p18: GPIO_AD_18::new(), + p19: GPIO_AD_19::new(), + p20: GPIO_AD_20::new(), + p21: GPIO_AD_21::new(), + p22: GPIO_AD_22::new(), + p23: GPIO_AD_23::new(), + p24: GPIO_AD_24::new(), + p25: GPIO_AD_25::new(), + p26: GPIO_AD_26::new(), + p27: GPIO_AD_27::new(), + p28: GPIO_AD_28::new(), + p29: GPIO_AD_29::new(), + p30: GPIO_AD_30::new(), + p31: GPIO_AD_31::new(), + p32: GPIO_AD_32::new(), + p33: GPIO_AD_33::new(), + p34: GPIO_AD_34::new(), + p35: GPIO_AD_35::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + self.p21.erase(), + self.p22.erase(), + self.p23.erase(), + self.p24.erase(), + self.p25.erase(), + self.p26.erase(), + self.p27.erase(), + self.p28.erase(), + self.p29.erase(), + self.p30.erase(), + self.p31.erase(), + self.p32.erase(), + self.p33.erase(), + self.p34.erase(), + self.p35.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_SD_B1. +pub mod gpio_sd_b1 { + + const GPIO_SD_B1_00_MUX_ADDR: u32 = 0x400e819c; + const GPIO_SD_B1_00_PAD_ADDR: u32 = 0x400e83e0; + pub type GPIO_SD_B1_00 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B1_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_SD_B1_01_MUX_ADDR: u32 = 0x400e81a0; + const GPIO_SD_B1_01_PAD_ADDR: u32 = 0x400e83e4; + pub type GPIO_SD_B1_01 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B1_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_SD_B1_02_MUX_ADDR: u32 = 0x400e81a4; + const GPIO_SD_B1_02_PAD_ADDR: u32 = 0x400e83e8; + pub type GPIO_SD_B1_02 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B1_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_SD_B1_03_MUX_ADDR: u32 = 0x400e81a8; + const GPIO_SD_B1_03_PAD_ADDR: u32 = 0x400e83ec; + pub type GPIO_SD_B1_03 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B1_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_SD_B1_04_MUX_ADDR: u32 = 0x400e81ac; + const GPIO_SD_B1_04_PAD_ADDR: u32 = 0x400e83f0; + pub type GPIO_SD_B1_04 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B1_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_SD_B1_05_MUX_ADDR: u32 = 0x400e81b0; + const GPIO_SD_B1_05_PAD_ADDR: u32 = 0x400e83f4; + pub type GPIO_SD_B1_05 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B1_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + /// All pads with prefix GPIO_SD_B1. + pub struct Pads { + pub p00: GPIO_SD_B1_00, + pub p01: GPIO_SD_B1_01, + pub p02: GPIO_SD_B1_02, + pub p03: GPIO_SD_B1_03, + pub p04: GPIO_SD_B1_04, + pub p05: GPIO_SD_B1_05, + } + /// Erased pads with prefix GPIO_SD_B1. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 6]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_SD_B1_00::new(), + p01: GPIO_SD_B1_01::new(), + p02: GPIO_SD_B1_02::new(), + p03: GPIO_SD_B1_03::new(), + p04: GPIO_SD_B1_04::new(), + p05: GPIO_SD_B1_05::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_SD_B2. +pub mod gpio_sd_b2 { + + const GPIO_SD_B2_00_MUX_ADDR: u32 = 0x400e81b4; + const GPIO_SD_B2_00_PAD_ADDR: u32 = 0x400e83f8; + pub type GPIO_SD_B2_00 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_SD_B2_01_MUX_ADDR: u32 = 0x400e81b8; + const GPIO_SD_B2_01_PAD_ADDR: u32 = 0x400e83fc; + pub type GPIO_SD_B2_01 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_02_MUX_ADDR: u32 = 0x400e81bc; + const GPIO_SD_B2_02_PAD_ADDR: u32 = 0x400e8400; + pub type GPIO_SD_B2_02 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_03_MUX_ADDR: u32 = 0x400e81c0; + const GPIO_SD_B2_03_PAD_ADDR: u32 = 0x400e8404; + pub type GPIO_SD_B2_03 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_04_MUX_ADDR: u32 = 0x400e81c4; + const GPIO_SD_B2_04_PAD_ADDR: u32 = 0x400e8408; + pub type GPIO_SD_B2_04 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_05_MUX_ADDR: u32 = 0x400e81c8; + const GPIO_SD_B2_05_PAD_ADDR: u32 = 0x400e840c; + pub type GPIO_SD_B2_05 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_06_MUX_ADDR: u32 = 0x400e81cc; + const GPIO_SD_B2_06_PAD_ADDR: u32 = 0x400e8410; + pub type GPIO_SD_B2_06 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_07_MUX_ADDR: u32 = 0x400e81d0; + const GPIO_SD_B2_07_PAD_ADDR: u32 = 0x400e8414; + pub type GPIO_SD_B2_07 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_08_MUX_ADDR: u32 = 0x400e81d4; + const GPIO_SD_B2_08_PAD_ADDR: u32 = 0x400e8418; + pub type GPIO_SD_B2_08 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_09_MUX_ADDR: u32 = 0x400e81d8; + const GPIO_SD_B2_09_PAD_ADDR: u32 = 0x400e841c; + pub type GPIO_SD_B2_09 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_10_MUX_ADDR: u32 = 0x400e81dc; + const GPIO_SD_B2_10_PAD_ADDR: u32 = 0x400e8420; + pub type GPIO_SD_B2_10 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_SD_B2_11_MUX_ADDR: u32 = 0x400e81e0; + const GPIO_SD_B2_11_PAD_ADDR: u32 = 0x400e8424; + pub type GPIO_SD_B2_11 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_SD_B2_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + /// All pads with prefix GPIO_SD_B2. + pub struct Pads { + pub p00: GPIO_SD_B2_00, + pub p01: GPIO_SD_B2_01, + pub p02: GPIO_SD_B2_02, + pub p03: GPIO_SD_B2_03, + pub p04: GPIO_SD_B2_04, + pub p05: GPIO_SD_B2_05, + pub p06: GPIO_SD_B2_06, + pub p07: GPIO_SD_B2_07, + pub p08: GPIO_SD_B2_08, + pub p09: GPIO_SD_B2_09, + pub p10: GPIO_SD_B2_10, + pub p11: GPIO_SD_B2_11, + } + /// Erased pads with prefix GPIO_SD_B2. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 12]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_SD_B2_00::new(), + p01: GPIO_SD_B2_01::new(), + p02: GPIO_SD_B2_02::new(), + p03: GPIO_SD_B2_03::new(), + p04: GPIO_SD_B2_04::new(), + p05: GPIO_SD_B2_05::new(), + p06: GPIO_SD_B2_06::new(), + p07: GPIO_SD_B2_07::new(), + p08: GPIO_SD_B2_08::new(), + p09: GPIO_SD_B2_09::new(), + p10: GPIO_SD_B2_10::new(), + p11: GPIO_SD_B2_11::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_DISP_B1. +pub mod gpio_disp_b1 { + + const GPIO_DISP_B1_00_MUX_ADDR: u32 = 0x400e81e4; + const GPIO_DISP_B1_00_PAD_ADDR: u32 = 0x400e8428; + pub type GPIO_DISP_B1_00 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_01_MUX_ADDR: u32 = 0x400e81e8; + const GPIO_DISP_B1_01_PAD_ADDR: u32 = 0x400e842c; + pub type GPIO_DISP_B1_01 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_02_MUX_ADDR: u32 = 0x400e81ec; + const GPIO_DISP_B1_02_PAD_ADDR: u32 = 0x400e8430; + pub type GPIO_DISP_B1_02 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_03_MUX_ADDR: u32 = 0x400e81f0; + const GPIO_DISP_B1_03_PAD_ADDR: u32 = 0x400e8434; + pub type GPIO_DISP_B1_03 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_04_MUX_ADDR: u32 = 0x400e81f4; + const GPIO_DISP_B1_04_PAD_ADDR: u32 = 0x400e8438; + pub type GPIO_DISP_B1_04 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_05_MUX_ADDR: u32 = 0x400e81f8; + const GPIO_DISP_B1_05_PAD_ADDR: u32 = 0x400e843c; + pub type GPIO_DISP_B1_05 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_06_MUX_ADDR: u32 = 0x400e81fc; + const GPIO_DISP_B1_06_PAD_ADDR: u32 = 0x400e8440; + pub type GPIO_DISP_B1_06 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_07_MUX_ADDR: u32 = 0x400e8200; + const GPIO_DISP_B1_07_PAD_ADDR: u32 = 0x400e8444; + pub type GPIO_DISP_B1_07 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_08_MUX_ADDR: u32 = 0x400e8204; + const GPIO_DISP_B1_08_PAD_ADDR: u32 = 0x400e8448; + pub type GPIO_DISP_B1_08 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_DISP_B1_09_MUX_ADDR: u32 = 0x400e8208; + const GPIO_DISP_B1_09_PAD_ADDR: u32 = 0x400e844c; + pub type GPIO_DISP_B1_09 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_DISP_B1_10_MUX_ADDR: u32 = 0x400e820c; + const GPIO_DISP_B1_10_PAD_ADDR: u32 = 0x400e8450; + pub type GPIO_DISP_B1_10 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_DISP_B1_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_DISP_B1_11_MUX_ADDR: u32 = 0x400e8210; + const GPIO_DISP_B1_11_PAD_ADDR: u32 = 0x400e8454; + pub type GPIO_DISP_B1_11 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B1_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + /// All pads with prefix GPIO_DISP_B1. + pub struct Pads { + pub p00: GPIO_DISP_B1_00, + pub p01: GPIO_DISP_B1_01, + pub p02: GPIO_DISP_B1_02, + pub p03: GPIO_DISP_B1_03, + pub p04: GPIO_DISP_B1_04, + pub p05: GPIO_DISP_B1_05, + pub p06: GPIO_DISP_B1_06, + pub p07: GPIO_DISP_B1_07, + pub p08: GPIO_DISP_B1_08, + pub p09: GPIO_DISP_B1_09, + pub p10: GPIO_DISP_B1_10, + pub p11: GPIO_DISP_B1_11, + } + /// Erased pads with prefix GPIO_DISP_B1. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 12]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_DISP_B1_00::new(), + p01: GPIO_DISP_B1_01::new(), + p02: GPIO_DISP_B1_02::new(), + p03: GPIO_DISP_B1_03::new(), + p04: GPIO_DISP_B1_04::new(), + p05: GPIO_DISP_B1_05::new(), + p06: GPIO_DISP_B1_06::new(), + p07: GPIO_DISP_B1_07::new(), + p08: GPIO_DISP_B1_08::new(), + p09: GPIO_DISP_B1_09::new(), + p10: GPIO_DISP_B1_10::new(), + p11: GPIO_DISP_B1_11::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_DISP_B2. +pub mod gpio_disp_b2 { + + const GPIO_DISP_B2_00_MUX_ADDR: u32 = 0x400e8214; + const GPIO_DISP_B2_00_PAD_ADDR: u32 = 0x400e8458; + pub type GPIO_DISP_B2_00 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_01_MUX_ADDR: u32 = 0x400e8218; + const GPIO_DISP_B2_01_PAD_ADDR: u32 = 0x400e845c; + pub type GPIO_DISP_B2_01 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_02_MUX_ADDR: u32 = 0x400e821c; + const GPIO_DISP_B2_02_PAD_ADDR: u32 = 0x400e8460; + pub type GPIO_DISP_B2_02 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_03_MUX_ADDR: u32 = 0x400e8220; + const GPIO_DISP_B2_03_PAD_ADDR: u32 = 0x400e8464; + pub type GPIO_DISP_B2_03 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_04_MUX_ADDR: u32 = 0x400e8224; + const GPIO_DISP_B2_04_PAD_ADDR: u32 = 0x400e8468; + pub type GPIO_DISP_B2_04 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_05_MUX_ADDR: u32 = 0x400e8228; + const GPIO_DISP_B2_05_PAD_ADDR: u32 = 0x400e846c; + pub type GPIO_DISP_B2_05 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_06_MUX_ADDR: u32 = 0x400e822c; + const GPIO_DISP_B2_06_PAD_ADDR: u32 = 0x400e8470; + pub type GPIO_DISP_B2_06 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_07_MUX_ADDR: u32 = 0x400e8230; + const GPIO_DISP_B2_07_PAD_ADDR: u32 = 0x400e8474; + pub type GPIO_DISP_B2_07 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_08_MUX_ADDR: u32 = 0x400e8234; + const GPIO_DISP_B2_08_PAD_ADDR: u32 = 0x400e8478; + pub type GPIO_DISP_B2_08 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_DISP_B2_09_MUX_ADDR: u32 = 0x400e8238; + const GPIO_DISP_B2_09_PAD_ADDR: u32 = 0x400e847c; + pub type GPIO_DISP_B2_09 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_DISP_B2_10_MUX_ADDR: u32 = 0x400e823c; + const GPIO_DISP_B2_10_PAD_ADDR: u32 = 0x400e8480; + pub type GPIO_DISP_B2_10 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_DISP_B2_11_MUX_ADDR: u32 = 0x400e8240; + const GPIO_DISP_B2_11_PAD_ADDR: u32 = 0x400e8484; + pub type GPIO_DISP_B2_11 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_DISP_B2_12_MUX_ADDR: u32 = 0x400e8244; + const GPIO_DISP_B2_12_PAD_ADDR: u32 = 0x400e8488; + pub type GPIO_DISP_B2_12 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_DISP_B2_13_MUX_ADDR: u32 = 0x400e8248; + const GPIO_DISP_B2_13_PAD_ADDR: u32 = 0x400e848c; + pub type GPIO_DISP_B2_13 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_DISP_B2_14_MUX_ADDR: u32 = 0x400e824c; + const GPIO_DISP_B2_14_PAD_ADDR: u32 = 0x400e8490; + pub type GPIO_DISP_B2_14 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_DISP_B2_15_MUX_ADDR: u32 = 0x400e8250; + const GPIO_DISP_B2_15_PAD_ADDR: u32 = 0x400e8494; + pub type GPIO_DISP_B2_15 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_DISP_B2_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + /// All pads with prefix GPIO_DISP_B2. + pub struct Pads { + pub p00: GPIO_DISP_B2_00, + pub p01: GPIO_DISP_B2_01, + pub p02: GPIO_DISP_B2_02, + pub p03: GPIO_DISP_B2_03, + pub p04: GPIO_DISP_B2_04, + pub p05: GPIO_DISP_B2_05, + pub p06: GPIO_DISP_B2_06, + pub p07: GPIO_DISP_B2_07, + pub p08: GPIO_DISP_B2_08, + pub p09: GPIO_DISP_B2_09, + pub p10: GPIO_DISP_B2_10, + pub p11: GPIO_DISP_B2_11, + pub p12: GPIO_DISP_B2_12, + pub p13: GPIO_DISP_B2_13, + pub p14: GPIO_DISP_B2_14, + pub p15: GPIO_DISP_B2_15, + } + /// Erased pads with prefix GPIO_DISP_B2. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 16]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_DISP_B2_00::new(), + p01: GPIO_DISP_B2_01::new(), + p02: GPIO_DISP_B2_02::new(), + p03: GPIO_DISP_B2_03::new(), + p04: GPIO_DISP_B2_04::new(), + p05: GPIO_DISP_B2_05::new(), + p06: GPIO_DISP_B2_06::new(), + p07: GPIO_DISP_B2_07::new(), + p08: GPIO_DISP_B2_08::new(), + p09: GPIO_DISP_B2_09::new(), + p10: GPIO_DISP_B2_10::new(), + p11: GPIO_DISP_B2_11::new(), + p12: GPIO_DISP_B2_12::new(), + p13: GPIO_DISP_B2_13::new(), + p14: GPIO_DISP_B2_14::new(), + p15: GPIO_DISP_B2_15::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_LPSR. +pub mod gpio_lpsr { + + const GPIO_LPSR_00_MUX_ADDR: u32 = 0x40c08000; + const GPIO_LPSR_00_PAD_ADDR: u32 = 0x40c08040; + pub type GPIO_LPSR_00 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_01_MUX_ADDR: u32 = 0x40c08004; + const GPIO_LPSR_01_PAD_ADDR: u32 = 0x40c08044; + pub type GPIO_LPSR_01 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_02_MUX_ADDR: u32 = 0x40c08008; + const GPIO_LPSR_02_PAD_ADDR: u32 = 0x40c08048; + pub type GPIO_LPSR_02 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_03_MUX_ADDR: u32 = 0x40c0800c; + const GPIO_LPSR_03_PAD_ADDR: u32 = 0x40c0804c; + pub type GPIO_LPSR_03 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_04_MUX_ADDR: u32 = 0x40c08010; + const GPIO_LPSR_04_PAD_ADDR: u32 = 0x40c08050; + pub type GPIO_LPSR_04 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_05_MUX_ADDR: u32 = 0x40c08014; + const GPIO_LPSR_05_PAD_ADDR: u32 = 0x40c08054; + pub type GPIO_LPSR_05 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_06_MUX_ADDR: u32 = 0x40c08018; + const GPIO_LPSR_06_PAD_ADDR: u32 = 0x40c08058; + pub type GPIO_LPSR_06 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_07_MUX_ADDR: u32 = 0x40c0801c; + const GPIO_LPSR_07_PAD_ADDR: u32 = 0x40c0805c; + pub type GPIO_LPSR_07 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_08_MUX_ADDR: u32 = 0x40c08020; + const GPIO_LPSR_08_PAD_ADDR: u32 = 0x40c08060; + pub type GPIO_LPSR_08 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_09_MUX_ADDR: u32 = 0x40c08024; + const GPIO_LPSR_09_PAD_ADDR: u32 = 0x40c08064; + pub type GPIO_LPSR_09 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_LPSR_10_MUX_ADDR: u32 = 0x40c08028; + const GPIO_LPSR_10_PAD_ADDR: u32 = 0x40c08068; + pub type GPIO_LPSR_10 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_LPSR_11_MUX_ADDR: u32 = 0x40c0802c; + const GPIO_LPSR_11_PAD_ADDR: u32 = 0x40c0806c; + pub type GPIO_LPSR_11 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_LPSR_12_MUX_ADDR: u32 = 0x40c08030; + const GPIO_LPSR_12_PAD_ADDR: u32 = 0x40c08070; + pub type GPIO_LPSR_12 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_LPSR_13_MUX_ADDR: u32 = 0x40c08034; + const GPIO_LPSR_13_PAD_ADDR: u32 = 0x40c08074; + pub type GPIO_LPSR_13 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_LPSR_14_MUX_ADDR: u32 = 0x40c08038; + const GPIO_LPSR_14_PAD_ADDR: u32 = 0x40c08078; + pub type GPIO_LPSR_14 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_LPSR_15_MUX_ADDR: u32 = 0x40c0803c; + const GPIO_LPSR_15_PAD_ADDR: u32 = 0x40c0807c; + pub type GPIO_LPSR_15 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_LPSR_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + /// All pads with prefix GPIO_LPSR. + pub struct Pads { + pub p00: GPIO_LPSR_00, + pub p01: GPIO_LPSR_01, + pub p02: GPIO_LPSR_02, + pub p03: GPIO_LPSR_03, + pub p04: GPIO_LPSR_04, + pub p05: GPIO_LPSR_05, + pub p06: GPIO_LPSR_06, + pub p07: GPIO_LPSR_07, + pub p08: GPIO_LPSR_08, + pub p09: GPIO_LPSR_09, + pub p10: GPIO_LPSR_10, + pub p11: GPIO_LPSR_11, + pub p12: GPIO_LPSR_12, + pub p13: GPIO_LPSR_13, + pub p14: GPIO_LPSR_14, + pub p15: GPIO_LPSR_15, + } + /// Erased pads with prefix GPIO_LPSR. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 16]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_LPSR_00::new(), + p01: GPIO_LPSR_01::new(), + p02: GPIO_LPSR_02::new(), + p03: GPIO_LPSR_03::new(), + p04: GPIO_LPSR_04::new(), + p05: GPIO_LPSR_05::new(), + p06: GPIO_LPSR_06::new(), + p07: GPIO_LPSR_07::new(), + p08: GPIO_LPSR_08::new(), + p09: GPIO_LPSR_09::new(), + p10: GPIO_LPSR_10::new(), + p11: GPIO_LPSR_11::new(), + p12: GPIO_LPSR_12::new(), + p13: GPIO_LPSR_13::new(), + p14: GPIO_LPSR_14::new(), + p15: GPIO_LPSR_15::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + ] + } + } +} + +/// All of the pads. +pub struct Pads { + pub gpio_emc_b1: gpio_emc_b1::Pads, + pub gpio_emc_b2: gpio_emc_b2::Pads, + pub gpio_ad: gpio_ad::Pads, + pub gpio_sd_b1: gpio_sd_b1::Pads, + pub gpio_sd_b2: gpio_sd_b2::Pads, + pub gpio_disp_b1: gpio_disp_b1::Pads, + pub gpio_disp_b2: gpio_disp_b2::Pads, + pub gpio_lpsr: gpio_lpsr::Pads, +} + +impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + gpio_emc_b1: gpio_emc_b1::Pads::new(), + gpio_emc_b2: gpio_emc_b2::Pads::new(), + gpio_ad: gpio_ad::Pads::new(), + gpio_sd_b1: gpio_sd_b1::Pads::new(), + gpio_sd_b2: gpio_sd_b2::Pads::new(), + gpio_disp_b1: gpio_disp_b1::Pads::new(), + gpio_disp_b2: gpio_disp_b2::Pads::new(), + gpio_lpsr: gpio_lpsr::Pads::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + ErasedPads { + gpio_emc_b1: self.gpio_emc_b1.erase(), + gpio_emc_b2: self.gpio_emc_b2.erase(), + gpio_ad: self.gpio_ad.erase(), + gpio_sd_b1: self.gpio_sd_b1.erase(), + gpio_sd_b2: self.gpio_sd_b2.erase(), + gpio_disp_b1: self.gpio_disp_b1.erase(), + gpio_disp_b2: self.gpio_disp_b2.erase(), + gpio_lpsr: self.gpio_lpsr.erase(), + } + } +} + +/// All erased pads. +pub struct ErasedPads { + pub gpio_emc_b1: gpio_emc_b1::ErasedPads, + pub gpio_emc_b2: gpio_emc_b2::ErasedPads, + pub gpio_ad: gpio_ad::ErasedPads, + pub gpio_sd_b1: gpio_sd_b1::ErasedPads, + pub gpio_sd_b2: gpio_sd_b2::ErasedPads, + pub gpio_disp_b1: gpio_disp_b1::ErasedPads, + pub gpio_disp_b2: gpio_disp_b2::ErasedPads, + pub gpio_lpsr: gpio_lpsr::ErasedPads, +} diff --git a/src/lib.rs b/src/lib.rs index 57d856f..ba5499e 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -173,6 +173,10 @@ pub mod imxrt1010; #[cfg_attr(docsrs, doc(cfg(feature = "imxrt1060")))] pub mod imxrt1060; +#[cfg(feature = "imxrt1170")] +#[cfg_attr(docsrs, doc(cfg(feature = "imxrt1170")))] +pub mod imxrt1170; + /// An IOMUXC-capable pad which can support I/O multiplexing /// /// # Safety @@ -485,19 +489,52 @@ impl Daisy { /// GPIO pad configuration pub mod gpio { /// A GPIO pin - pub trait Pin: super::Iomuxc { + /// + /// The constant `N` is the associated GPIO module + /// (a `3` for `GPIO3`). + pub trait Pin: super::Iomuxc { /// The alternate value for this pad const ALT: u32; - /// The GPIO module; `U5` for `GPIO5` - type Module: super::consts::Unsigned; /// The offset; `U13` for `GPIO5_IO13` - type Offset: super::consts::Unsigned; + const OFFSET: u32; } /// Prepare a pad to be used as a GPIO pin + pub fn prepare, const N: u8>(pin: &mut P) { + super::alternate(pin, P::ALT); + } +} + +/// CCM pad configuration. +pub mod ccm { + /// A CCM pin. + /// + /// These can be used for observing clock outputs, or for generating + /// outputs for your PMIC. + pub trait Pin: super::Iomuxc { + /// The alternate value for this pad. + const ALT: u32; + /// The pin function. + type Function: Function; + } + + /// Prepare a pad to be used as a CCM pin. pub fn prepare(pin: &mut P) { super::alternate(pin, P::ALT); } + + mod private { + pub trait Sealed {} + } + /// A CCM pin function. + pub trait Function: private::Sealed {} + + /// Observability output. + pub enum Observable {} + impl private::Sealed for Observable<1> {} + impl private::Sealed for Observable<2> {} + impl Function for Observable<1> {} + impl Function for Observable<2> {} } #[cfg(test)]