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Reintroduce logging in the full-speed driver
1 parent e92599a commit 88d048d

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5 files changed

+37
-21
lines changed

5 files changed

+37
-21
lines changed

.gitignore

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
11
/target
22
Cargo.lock
3-
.vscode/
3+
.vscode/
4+
screenlog.*

examples/teensy4/Cargo.toml

+2-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ publish = false # This is an example package
1010
path = "../../"
1111
features = [
1212
"double-instance", # Required to pair with imxrt-[hal|ral]/imxrt1062
13-
# "__log" # Only for driver development and debugging
13+
"__log" # Only for driver development and debugging
1414
]
1515

1616
# Supporting other hardware access, start-up
@@ -51,6 +51,7 @@ version = "0.2"
5151
# examples
5252
[dependencies.log]
5353
version = "0.4"
54+
features = ["release_max_level_info"]
5455

5556
[[bin]]
5657
name = "configured"

src/full_speed/bus.rs

-16
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,6 @@ impl UsbBus for BusAdapter {
187187
fn set_device_address(&self, addr: u8) {
188188
self.with_usb_mut(|usb| {
189189
usb.set_address(addr);
190-
debug!("ADDRESS {}", addr);
191190
});
192191
}
193192

@@ -198,7 +197,6 @@ impl UsbBus for BusAdapter {
198197
fn reset(&self) {
199198
self.with_usb_mut(|usb| {
200199
usb.bus_reset();
201-
debug!("RESET");
202200
});
203201
}
204202

@@ -208,13 +206,6 @@ impl UsbBus for BusAdapter {
208206
return Err(usb_device::UsbError::InvalidEndpoint);
209207
}
210208

211-
debug!(
212-
"EP{} {:?} WRITE {}",
213-
ep_addr.index(),
214-
ep_addr.direction(),
215-
buf.len()
216-
);
217-
218209
let written = if ep_addr.index() == 0 {
219210
usb.ctrl0_write(buf)
220211
} else {
@@ -240,13 +231,6 @@ impl UsbBus for BusAdapter {
240231
return Err(usb_device::UsbError::InvalidEndpoint);
241232
}
242233

243-
debug!(
244-
"EP{} {:?} READ {}",
245-
ep_addr.index(),
246-
ep_addr.direction(),
247-
buf.len()
248-
);
249-
250234
let read = if ep_addr.index() == 0 {
251235
usb.ctrl0_read(buf)
252236
} else {

src/full_speed/driver.rs

+15-1
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,7 @@ impl FullSpeed {
120120
// See the "quirk" note in the UsbBus impl. We're using USBADRA to let
121121
// the hardware set the address before the status phase.
122122
ral::write_reg!(ral::usb, self.usb, DEVICEADDR, USBADR: address as u32, USBADRA: 1);
123+
info!("ADDRESS {}", address);
123124
}
124125

125126
pub fn attach(&mut self) {
@@ -144,6 +145,7 @@ impl FullSpeed {
144145
ral::read_reg!(ral::usb, self.usb, PORTSC1, PR == 1),
145146
"Took too long to handle bus reset"
146147
);
148+
info!("RESET");
147149
}
148150

149151
/// Check if the endpoint is valid
@@ -164,6 +166,7 @@ impl FullSpeed {
164166
pub fn ctrl0_read(&mut self, buffer: &mut [u8]) -> Result<usize, Status> {
165167
let ctrl_out = self.endpoints[0].as_mut().unwrap();
166168
if ctrl_out.has_setup(&self.usb) && buffer.len() >= 8 {
169+
debug!("EP0 Out SETUP");
167170
let setup = ctrl_out.read_setup(&self.usb);
168171
buffer[..8].copy_from_slice(&setup.to_le_bytes());
169172

@@ -180,6 +183,7 @@ impl FullSpeed {
180183
ctrl_out.clear_nack(&self.usb);
181184

182185
let read = ctrl_out.read(buffer);
186+
debug!("EP0 Out {}", read);
183187
let max_packet_len = ctrl_out.max_packet_len();
184188
ctrl_out.schedule_transfer(&self.usb, max_packet_len);
185189

@@ -196,6 +200,7 @@ impl FullSpeed {
196200
/// Panics if EP0 IN isn't allocated, or if EP0 OUT isn't allocated.
197201
pub fn ctrl0_write(&mut self, buffer: &[u8]) -> Result<usize, Status> {
198202
let ctrl_in = self.endpoints[1].as_mut().unwrap();
203+
debug!("EP1 In {}", buffer.len());
199204
ctrl_in.check_status()?;
200205

201206
ctrl_in.clear_nack(&self.usb);
@@ -295,7 +300,8 @@ impl FullSpeed {
295300
let qh = self.qhs[index(addr)].take().unwrap();
296301
let td = self.tds[index(addr)].take().unwrap();
297302

298-
qh.set_max_packet_len(buffer.len());
303+
let max_packet_size = buffer.len();
304+
qh.set_max_packet_len(max_packet_size);
299305
qh.set_zero_length_termination(false);
300306
qh.set_interrupt_on_setup(
301307
EndpointType::Control == kind && addr.direction() == UsbDirection::Out,
@@ -307,6 +313,14 @@ impl FullSpeed {
307313
let mut ep = Endpoint::new(addr, qh, td, buffer);
308314
ep.initialize(&self.usb, kind);
309315
self.endpoints[index(addr)] = Some(ep);
316+
317+
info!(
318+
"ALLOC EP{} {:?} {:?} {}",
319+
addr.index(),
320+
addr.direction(),
321+
kind,
322+
max_packet_size
323+
);
310324
}
311325

312326
/// Enable all non-zero endpoints, and schedule OUT transfers

src/log.rs

+18-2
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,32 @@
33
//! Only enable `__log` when debugging, and when you're certain that your
44
//! logger isn't using USB!
55
6+
#![allow(unused)]
7+
8+
macro_rules! trace {
9+
($($args:tt)*) => {
10+
#[cfg(feature = "__log")]
11+
::__log::trace!(target: "", $($args)*)
12+
};
13+
}
14+
615
macro_rules! debug {
716
($($args:tt)*) => {
817
#[cfg(feature = "__log")]
9-
::__log::debug!($($args)*)
18+
::__log::debug!(target: "", $($args)*)
19+
};
20+
}
21+
22+
macro_rules! info {
23+
($($args:tt)*) => {
24+
#[cfg(feature = "__log")]
25+
::__log::info!(target: "", $($args)*)
1026
};
1127
}
1228

1329
macro_rules! warn {
1430
($($args:tt)*) => {
1531
#[cfg(feature = "__log")]
16-
::__log::warn!($($args)*)
32+
::__log::warn!(target: "", $($args)*)
1733
};
1834
}

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