Fix clang format

Author: changhoon-sung

src/Target.cpp

@@ -155,7 +155,7 @@ Target::Processor get_amd_processor(unsigned family, unsigned model, bool have_s
         }
         break;
     case 0x19:  // AMD Family 19h
-	if (
+        if (
             // Zen 3
             (0x50 <= model && model <= 0x5F) ||  // Cezanne
             (0x40 <= model && model <= 0x4F) ||  // Rembrandt
@@ -165,17 +165,17 @@ Target::Processor get_amd_processor(unsigned family, unsigned model, bool have_s
         ) {
             return Target::Processor::ZnVer3;
         } else if (
-	    // Zen 4
-	    (0xA0 <= model && model <= 0xAF) ||  // Genoa, Dragon Range
+            // Zen 4
+            (0xA0 <= model && model <= 0xAF) ||  // Genoa, Dragon Range
             (0x78 <= model && model <= 0x7F) ||  // Phoenix 2, Hawk Point 2 (Zen 4c)
             (0x70 <= model && model <= 0x77) ||  // Phoenix, Hawk Point 1
             (0x60 <= model && model <= 0x6F) ||  // Raphael
             (0x10 <= model && model <= 0x1F)     // Storm Peak
-	) {
+        ) {
             return Target::Processor::ZnVer4;
         }
         break;
-    case 0x1a:  // AMD Family 1Ah
+    case 0x1a:                             // AMD Family 1Ah
         return Target::Processor::ZnVer5;  // Zen5
     default:
         break;  // Unknown AMD CPU.

src/runtime/HalideRuntime.h

@@ -1360,13 +1360,13 @@ typedef enum halide_target_feature_t {
     halide_target_feature_no_asserts,       ///< Disable all runtime checks, for slightly tighter code.
     halide_target_feature_no_bounds_query,  ///< Disable the bounds querying functionality.
 
-    halide_target_feature_sse41,  ///< Use SSE 4.1 and earlier instructions. Only relevant on x86.
-    halide_target_feature_avx,    ///< Use AVX 1 instructions. Only relevant on x86.
-    halide_target_feature_avx2,   ///< Use AVX 2 instructions. Only relevant on x86.
-    halide_target_feature_avxvnni,///< Enable the AVX-VNNI features supported by AVX2 instructions. Supports 256-bit VNNI instructions without EVEX encoding.
-    halide_target_feature_fma,    ///< Enable x86 FMA instruction
-    halide_target_feature_fma4,   ///< Enable x86 (AMD) FMA4 instruction set
-    halide_target_feature_f16c,   ///< Enable x86 16-bit float support
+    halide_target_feature_sse41,    ///< Use SSE 4.1 and earlier instructions. Only relevant on x86.
+    halide_target_feature_avx,      ///< Use AVX 1 instructions. Only relevant on x86.
+    halide_target_feature_avx2,     ///< Use AVX 2 instructions. Only relevant on x86.
+    halide_target_feature_avxvnni,  ///< Enable the AVX-VNNI features supported by AVX2 instructions. Supports 256-bit VNNI instructions without EVEX encoding.
+    halide_target_feature_fma,      ///< Enable x86 FMA instruction
+    halide_target_feature_fma4,     ///< Enable x86 (AMD) FMA4 instruction set
+    halide_target_feature_f16c,     ///< Enable x86 16-bit float support
 
     halide_target_feature_armv7s,   ///< Generate code for ARMv7s. Only relevant for 32-bit ARM.
     halide_target_feature_no_neon,  ///< Avoid using NEON instructions. Only relevant for 32-bit ARM.