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add some vscode stuff i guess to the release
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,47 +1,47 @@ | ||
| { | ||
| "cSpell.words": [ | ||
| "TXFULL", | ||
| "Uart", | ||
| "asid", | ||
| "concat", | ||
| "ebreak", | ||
| "ebss", | ||
| "edata", | ||
| "eheap", | ||
| "estack", | ||
| "etext", | ||
| "getc", | ||
| "irqs", | ||
| "kernel", | ||
| "mcause", | ||
| "mext", | ||
| "msoft", | ||
| "mstatus", | ||
| "mtimer", | ||
| "pagetable", | ||
| "pending", | ||
| "processtable", | ||
| "putc", | ||
| "riscv", | ||
| "rt", | ||
| "satp", | ||
| "sbss", | ||
| "sdata", | ||
| "set", | ||
| "sheap", | ||
| "sidata", | ||
| "sstack", | ||
| "stext", | ||
| "syscalls", | ||
| "virt", | ||
| "vmim", | ||
| "vmip", | ||
| "xous" | ||
| ], | ||
| "rust-analyzer.checkOnSave.allTargets": false, | ||
| "rust-analyzer.cargo.target": "riscv32imac-unknown-none-elf" | ||
| // "rust-analyzer.checkOnSave.extraArgs": [ | ||
| // "--target", | ||
| // "riscv32imac-unknown-none-elf" | ||
| // ] | ||
| } | ||
| { | ||
| "cSpell.words": [ | ||
| "TXFULL", | ||
| "Uart", | ||
| "asid", | ||
| "concat", | ||
| "ebreak", | ||
| "ebss", | ||
| "edata", | ||
| "eheap", | ||
| "estack", | ||
| "etext", | ||
| "getc", | ||
| "irqs", | ||
| "kernel", | ||
| "mcause", | ||
| "mext", | ||
| "msoft", | ||
| "mstatus", | ||
| "mtimer", | ||
| "pagetable", | ||
| "pending", | ||
| "processtable", | ||
| "putc", | ||
| "riscv", | ||
| "rt", | ||
| "satp", | ||
| "sbss", | ||
| "sdata", | ||
| "set", | ||
| "sheap", | ||
| "sidata", | ||
| "sstack", | ||
| "stext", | ||
| "syscalls", | ||
| "virt", | ||
| "vmim", | ||
| "vmip", | ||
| "xous" | ||
| ], | ||
| "rust-analyzer.checkOnSave.allTargets": false, | ||
| "rust-analyzer.cargo.target": "riscv32imac-unknown-none-elf" | ||
| // "rust-analyzer.checkOnSave.extraArgs": [ | ||
| // "--target", | ||
| // "riscv32imac-unknown-none-elf" | ||
| // ] | ||
| } |