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1 parent 4ce322b commit 6dd17f5Copy full SHA for 6dd17f5
cpu/msp430/f2xxx/uart0.c
@@ -146,8 +146,8 @@ uart0_init(unsigned long ubr)
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UCA0CTL1 |= UCSWRST; /* Hold peripheral in reset state */
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UCA0CTL1 |= UCSSEL_2; /* CLK = SMCLK */
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- UCA0BR0 = ubr; /* 8MHz/115200 = 69 = 0x45 */
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- UCA0BR1 = 0x00;
+ UCA0BR0 = ((uint8_t *)&ubr)[0]; /* 8MHz/115200 = 69 = 0x45 */
+ UCA0BR1 = ((uint8_t *)&ubr)[1];
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UCA0MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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P3DIR &= ~0x20; /* P3.5 = USCI_A0 RXD as input */
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