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aarch64-tdep.c
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/* Common target dependent code for GDB on AArch64 systems.
Copyright (C) 2009-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "dis-asm.h"
#include "regcache.h"
#include "reggroups.h"
#include "value.h"
#include "arch-utils.h"
#include "osabi.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "objfiles.h"
#include "dwarf2.h"
#include "dwarf2/frame.h"
#include "gdbtypes.h"
#include "prologue-value.h"
#include "target-descriptions.h"
#include "user-regs.h"
#include "ax-gdb.h"
#include "gdbsupport/selftest.h"
#include "aarch64-tdep.h"
#include "aarch64-ravenscar-thread.h"
#include "record.h"
#include "record-full.h"
#include "arch/aarch64-insn.h"
#include "gdbarch.h"
#include "opcode/aarch64.h"
#include <algorithm>
/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
four members. */
#define HA_MAX_NUM_FLDS 4
/* All possible aarch64 target descriptors. */
static target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/][2 /* mte */];
/* The standard register names, and all the valid aliases for them. */
static const struct
{
const char *const name;
int regnum;
} aarch64_register_aliases[] =
{
/* 64-bit register names. */
{"fp", AARCH64_FP_REGNUM},
{"lr", AARCH64_LR_REGNUM},
{"sp", AARCH64_SP_REGNUM},
/* 32-bit register names. */
{"w0", AARCH64_X0_REGNUM + 0},
{"w1", AARCH64_X0_REGNUM + 1},
{"w2", AARCH64_X0_REGNUM + 2},
{"w3", AARCH64_X0_REGNUM + 3},
{"w4", AARCH64_X0_REGNUM + 4},
{"w5", AARCH64_X0_REGNUM + 5},
{"w6", AARCH64_X0_REGNUM + 6},
{"w7", AARCH64_X0_REGNUM + 7},
{"w8", AARCH64_X0_REGNUM + 8},
{"w9", AARCH64_X0_REGNUM + 9},
{"w10", AARCH64_X0_REGNUM + 10},
{"w11", AARCH64_X0_REGNUM + 11},
{"w12", AARCH64_X0_REGNUM + 12},
{"w13", AARCH64_X0_REGNUM + 13},
{"w14", AARCH64_X0_REGNUM + 14},
{"w15", AARCH64_X0_REGNUM + 15},
{"w16", AARCH64_X0_REGNUM + 16},
{"w17", AARCH64_X0_REGNUM + 17},
{"w18", AARCH64_X0_REGNUM + 18},
{"w19", AARCH64_X0_REGNUM + 19},
{"w20", AARCH64_X0_REGNUM + 20},
{"w21", AARCH64_X0_REGNUM + 21},
{"w22", AARCH64_X0_REGNUM + 22},
{"w23", AARCH64_X0_REGNUM + 23},
{"w24", AARCH64_X0_REGNUM + 24},
{"w25", AARCH64_X0_REGNUM + 25},
{"w26", AARCH64_X0_REGNUM + 26},
{"w27", AARCH64_X0_REGNUM + 27},
{"w28", AARCH64_X0_REGNUM + 28},
{"w29", AARCH64_X0_REGNUM + 29},
{"w30", AARCH64_X0_REGNUM + 30},
/* specials */
{"ip0", AARCH64_X0_REGNUM + 16},
{"ip1", AARCH64_X0_REGNUM + 17}
};
/* The required core 'R' registers. */
static const char *const aarch64_r_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_X0_REGNUM! */
"x0", "x1", "x2", "x3",
"x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11",
"x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19",
"x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27",
"x28", "x29", "x30", "sp",
"pc", "cpsr"
};
/* The FP/SIMD 'V' registers. */
static const char *const aarch64_v_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_V0_REGNUM! */
"v0", "v1", "v2", "v3",
"v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11",
"v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19",
"v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27",
"v28", "v29", "v30", "v31",
"fpsr",
"fpcr"
};
/* The SVE 'Z' and 'P' registers. */
static const char *const aarch64_sve_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_SVE_Z0_REGNUM! */
"z0", "z1", "z2", "z3",
"z4", "z5", "z6", "z7",
"z8", "z9", "z10", "z11",
"z12", "z13", "z14", "z15",
"z16", "z17", "z18", "z19",
"z20", "z21", "z22", "z23",
"z24", "z25", "z26", "z27",
"z28", "z29", "z30", "z31",
"fpsr", "fpcr",
"p0", "p1", "p2", "p3",
"p4", "p5", "p6", "p7",
"p8", "p9", "p10", "p11",
"p12", "p13", "p14", "p15",
"ffr", "vg"
};
static const char *const aarch64_pauth_register_names[] =
{
/* Authentication mask for data pointer. */
"pauth_dmask",
/* Authentication mask for code pointer. */
"pauth_cmask"
};
static const char *const aarch64_mte_register_names[] =
{
/* Tag Control Register. */
"tag_ctl"
};
/* AArch64 prologue cache structure. */
struct aarch64_prologue_cache
{
/* The program counter at the start of the function. It is used to
identify this frame as a prologue frame. */
CORE_ADDR func;
/* The program counter at the time this frame was created; i.e. where
this function was called from. It is used to identify this frame as a
stub frame. */
CORE_ADDR prev_pc;
/* The stack pointer at the time this frame was created; i.e. the
caller's stack pointer when this function was called. It is used
to identify this frame. */
CORE_ADDR prev_sp;
/* Is the target available to read from? */
int available_p;
/* The frame base for this frame is just prev_sp - frame size.
FRAMESIZE is the distance from the frame pointer to the
initial stack pointer. */
int framesize;
/* The register used to hold the frame pointer for this frame. */
int framereg;
/* Saved register offsets. */
trad_frame_saved_reg *saved_regs;
};
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
{
fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
}
namespace {
/* Abstract instruction reader. */
class abstract_instruction_reader
{
public:
/* Read in one instruction. */
virtual ULONGEST read (CORE_ADDR memaddr, int len,
enum bfd_endian byte_order) = 0;
};
/* Instruction reader from real target. */
class instruction_reader : public abstract_instruction_reader
{
public:
ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
override
{
return read_code_unsigned_integer (memaddr, len, byte_order);
}
};
} // namespace
/* If address signing is enabled, mask off the signature bits from the link
register, which is passed by value in ADDR, using the register values in
THIS_FRAME. */
static CORE_ADDR
aarch64_frame_unmask_lr (aarch64_gdbarch_tdep *tdep,
struct frame_info *this_frame, CORE_ADDR addr)
{
if (tdep->has_pauth ()
&& frame_unwind_register_unsigned (this_frame,
tdep->pauth_ra_state_regnum))
{
int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
addr = addr & ~cmask;
/* Record in the frame that the link register required unmasking. */
set_frame_previous_pc_masked (this_frame);
}
return addr;
}
/* Implement the "get_pc_address_flags" gdbarch method. */
static std::string
aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
{
if (pc != 0 && get_frame_pc_masked (frame))
return "PAC";
return "";
}
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
static CORE_ADDR
aarch64_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR start, CORE_ADDR limit,
struct aarch64_prologue_cache *cache,
abstract_instruction_reader& reader)
{
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
int i;
/* Whether the stack has been set. This should be true when we notice a SP
to FP move or if we are using the SP as the base register for storing
data, in case the FP is ommitted. */
bool seen_stack_set = false;
/* Track X registers and D registers in prologue. */
pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
regs[i] = pv_register (i, 0);
pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
for (; start < limit; start += 4)
{
uint32_t insn;
aarch64_inst inst;
insn = reader.read (start, 4, byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
break;
if (inst.opcode->iclass == addsub_imm
&& (inst.opcode->op == OP_ADD
|| strcmp ("sub", inst.opcode->name) == 0))
{
unsigned rd = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].reg.regno;
gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
if (inst.opcode->op == OP_ADD)
{
regs[rd] = pv_add_constant (regs[rn],
inst.operands[2].imm.value);
}
else
{
regs[rd] = pv_add_constant (regs[rn],
-inst.operands[2].imm.value);
}
/* Did we move SP to FP? */
if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM)
seen_stack_set = true;
}
else if (inst.opcode->iclass == pcreladdr
&& inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
{
gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
regs[inst.operands[0].reg.regno] = pv_unknown ();
}
else if (inst.opcode->iclass == branch_imm)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == condbranch)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == branch_reg)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == compbranch)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->op == OP_MOVZ)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
/* If this shows up before we set the stack, keep going. Otherwise
stop the analysis. */
if (seen_stack_set)
break;
regs[inst.operands[0].reg.regno] = pv_unknown ();
}
else if (inst.opcode->iclass == log_shift
&& strcmp (inst.opcode->name, "orr") == 0)
{
unsigned rd = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].reg.regno;
unsigned rm = inst.operands[2].reg.regno;
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
if (inst.operands[2].shifter.amount == 0
&& rn == AARCH64_SP_REGNUM)
regs[rd] = regs[rm];
else
{
aarch64_debug_printf ("prologue analysis gave up "
"addr=%s opcode=0x%x (orr x register)",
core_addr_to_string_nz (start), insn);
break;
}
}
else if (inst.opcode->op == OP_STUR)
{
unsigned rt = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].addr.base_regno;
int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
gdb_assert (!inst.operands[1].addr.offset.is_reg);
stack.store
(pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
size, regs[rt]);
/* Are we storing with SP as a base? */
if (rn == AARCH64_SP_REGNUM)
seen_stack_set = true;
}
else if ((inst.opcode->iclass == ldstpair_off
|| (inst.opcode->iclass == ldstpair_indexed
&& inst.operands[2].addr.preind))
&& strcmp ("stp", inst.opcode->name) == 0)
{
/* STP with addressing mode Pre-indexed and Base register. */
unsigned rt1;
unsigned rt2;
unsigned rn = inst.operands[2].addr.base_regno;
int32_t imm = inst.operands[2].addr.offset.imm;
int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
|| inst.operands[0].type == AARCH64_OPND_Ft);
gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
|| inst.operands[1].type == AARCH64_OPND_Ft2);
gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
gdb_assert (!inst.operands[2].addr.offset.is_reg);
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
further prologue analysis. */
if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
break;
if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
break;
rt1 = inst.operands[0].reg.regno;
rt2 = inst.operands[1].reg.regno;
if (inst.operands[0].type == AARCH64_OPND_Ft)
{
rt1 += AARCH64_X_REGISTER_COUNT;
rt2 += AARCH64_X_REGISTER_COUNT;
}
stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
if (inst.operands[2].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
/* Ignore the instruction that allocates stack space and sets
the SP. */
if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback)
seen_stack_set = true;
}
else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
|| (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
&& (inst.opcode->op == OP_STR_POS
|| inst.opcode->op == OP_STRF_POS)))
&& inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
&& strcmp ("str", inst.opcode->name) == 0)
{
/* STR (immediate) */
unsigned int rt = inst.operands[0].reg.regno;
int32_t imm = inst.operands[1].addr.offset.imm;
unsigned int rn = inst.operands[1].addr.base_regno;
int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
|| inst.operands[0].type == AARCH64_OPND_Ft);
if (inst.operands[0].type == AARCH64_OPND_Ft)
rt += AARCH64_X_REGISTER_COUNT;
stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
if (inst.operands[1].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
/* Are we storing with SP as a base? */
if (rn == AARCH64_SP_REGNUM)
seen_stack_set = true;
}
else if (inst.opcode->iclass == testbranch)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == ic_system)
{
aarch64_gdbarch_tdep *tdep
= (aarch64_gdbarch_tdep *) gdbarch_tdep (gdbarch);
int ra_state_val = 0;
if (insn == 0xd503233f /* paciasp. */
|| insn == 0xd503237f /* pacibsp. */)
{
/* Return addresses are mangled. */
ra_state_val = 1;
}
else if (insn == 0xd50323bf /* autiasp. */
|| insn == 0xd50323ff /* autibsp. */)
{
/* Return addresses are not mangled. */
ra_state_val = 0;
}
else if (IS_BTI (insn))
/* We don't need to do anything special for a BTI instruction. */
continue;
else
{
aarch64_debug_printf ("prologue analysis gave up addr=%s"
" opcode=0x%x (iclass)",
core_addr_to_string_nz (start), insn);
break;
}
if (tdep->has_pauth () && cache != nullptr)
{
int regnum = tdep->pauth_ra_state_regnum;
cache->saved_regs[regnum].set_value (ra_state_val);
}
}
else
{
aarch64_debug_printf ("prologue analysis gave up addr=%s"
" opcode=0x%x",
core_addr_to_string_nz (start), insn);
break;
}
}
if (cache == NULL)
return start;
if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
{
/* Frame pointer is fp. Frame size is constant. */
cache->framereg = AARCH64_FP_REGNUM;
cache->framesize = -regs[AARCH64_FP_REGNUM].k;
}
else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
{
/* Try the stack pointer. */
cache->framesize = -regs[AARCH64_SP_REGNUM].k;
cache->framereg = AARCH64_SP_REGNUM;
}
else
{
/* We're just out of luck. We don't know where the frame is. */
cache->framereg = -1;
cache->framesize = 0;
}
for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i, &offset))
cache->saved_regs[i].set_addr (offset);
}
for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
{
int regnum = gdbarch_num_regs (gdbarch);
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
&offset))
cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].set_addr (offset);
}
return start;
}
static CORE_ADDR
aarch64_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR start, CORE_ADDR limit,
struct aarch64_prologue_cache *cache)
{
instruction_reader reader;
return aarch64_analyze_prologue (gdbarch, start, limit, cache,
reader);
}
#if GDB_SELF_TEST
namespace selftests {
/* Instruction reader from manually cooked instruction sequences. */
class instruction_reader_test : public abstract_instruction_reader
{
public:
template<size_t SIZE>
explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
: m_insns (insns), m_insns_size (SIZE)
{}
ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
override
{
SELF_CHECK (len == 4);
SELF_CHECK (memaddr % 4 == 0);
SELF_CHECK (memaddr / 4 < m_insns_size);
return m_insns[memaddr / 4];
}
private:
const uint32_t *m_insns;
size_t m_insns_size;
};
static void
aarch64_analyze_prologue_test (void)
{
struct gdbarch_info info;
info.bfd_arch_info = bfd_scan_arch ("aarch64");
struct gdbarch *gdbarch = gdbarch_find_by_info (info);
SELF_CHECK (gdbarch != NULL);
struct aarch64_prologue_cache cache;
cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
aarch64_gdbarch_tdep *tdep = (aarch64_gdbarch_tdep *) gdbarch_tdep (gdbarch);
/* Test the simple prologue in which frame pointer is used. */
{
static const uint32_t insns[] = {
0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
0x910003fd, /* mov x29, sp */
0x97ffffe6, /* bl 0x400580 */
};
instruction_reader_test reader (insns);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
SELF_CHECK (end == 4 * 2);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 272);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == AARCH64_FP_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -272);
else if (i == AARCH64_LR_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -264);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
{
int num_regs = gdbarch_num_regs (gdbarch);
int regnum = i + num_regs + AARCH64_D0_REGNUM;
SELF_CHECK (cache.saved_regs[regnum].is_realreg ()
&& cache.saved_regs[regnum].realreg () == regnum);
}
}
/* Test a prologue in which STR is used and frame pointer is not
used. */
{
static const uint32_t insns[] = {
0xf81d0ff3, /* str x19, [sp, #-48]! */
0xb9002fe0, /* str w0, [sp, #44] */
0xf90013e1, /* str x1, [sp, #32]*/
0xfd000fe0, /* str d0, [sp, #24] */
0xaa0203f3, /* mov x19, x2 */
0xf94013e0, /* ldr x0, [sp, #32] */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
SELF_CHECK (end == 4 * 5);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 48);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == 1)
SELF_CHECK (cache.saved_regs[i].addr () == -16);
else if (i == 19)
SELF_CHECK (cache.saved_regs[i].addr () == -48);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
{
int num_regs = gdbarch_num_regs (gdbarch);
int regnum = i + num_regs + AARCH64_D0_REGNUM;
if (i == 0)
SELF_CHECK (cache.saved_regs[regnum].addr () == -24);
else
SELF_CHECK (cache.saved_regs[regnum].is_realreg ()
&& cache.saved_regs[regnum].realreg () == regnum);
}
}
/* Test handling of movz before setting the frame pointer. */
{
static const uint32_t insns[] = {
0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
0x52800020, /* mov w0, #0x1 */
0x910003fd, /* mov x29, sp */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 4th instruction. */
SELF_CHECK (end == (4 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 16);
}
/* Test handling of movz/stp when using the stack pointer as frame
pointer. */
{
static const uint32_t insns[] = {
0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
0x52800020, /* mov w0, #0x1 */
0x290207e0, /* stp w0, w1, [sp, #16] */
0xa9018fe2, /* stp x2, x3, [sp, #24] */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 5th instruction. */
SELF_CHECK (end == (5 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 64);
}
/* Test handling of movz/str when using the stack pointer as frame
pointer */
{
static const uint32_t insns[] = {
0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
0x52800020, /* mov w0, #0x1 */
0xb9002be4, /* str w4, [sp, #40] */
0xf9001be5, /* str x5, [sp, #48] */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 5th instruction. */
SELF_CHECK (end == (5 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 64);
}
/* Test handling of movz/stur when using the stack pointer as frame
pointer. */
{
static const uint32_t insns[] = {
0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
0x52800020, /* mov w0, #0x1 */
0xb80343e6, /* stur w6, [sp, #52] */
0xf80383e7, /* stur x7, [sp, #56] */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 5th instruction. */
SELF_CHECK (end == (5 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 64);
}
/* Test handling of movz when there is no frame pointer set or no stack
pointer used. */
{
static const uint32_t insns[] = {
0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
0x52800020, /* mov w0, #0x1 */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 4th instruction. */
SELF_CHECK (end == (4 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 16);
}
/* Test a prologue in which there is a return address signing instruction. */
if (tdep->has_pauth ())
{
static const uint32_t insns[] = {
0xd503233f, /* paciasp */
0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
0x910003fd, /* mov x29, sp */
0xf801c3f3, /* str x19, [sp, #28] */
0xb9401fa0, /* ldr x19, [x29, #28] */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
reader);
SELF_CHECK (end == 4 * 4);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 48);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == 19)
SELF_CHECK (cache.saved_regs[i].addr () == -20);
else if (i == AARCH64_FP_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -48);
else if (i == AARCH64_LR_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -40);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
if (tdep->has_pauth ())
{
int regnum = tdep->pauth_ra_state_regnum;
SELF_CHECK (cache.saved_regs[regnum].is_value ());
}
}
/* Test a prologue with a BTI instruction. */
{
static const uint32_t insns[] = {
0xd503245f, /* bti */
0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
0x910003fd, /* mov x29, sp */
0xf801c3f3, /* str x19, [sp, #28] */
0xb9401fa0, /* ldr x19, [x29, #28] */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
reader);
SELF_CHECK (end == 4 * 4);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 48);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == 19)
SELF_CHECK (cache.saved_regs[i].addr () == -20);
else if (i == AARCH64_FP_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -48);
else if (i == AARCH64_LR_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -40);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
}
}
} // namespace selftests
#endif /* GDB_SELF_TEST */
/* Implement the "skip_prologue" gdbarch method. */
static CORE_ADDR
aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR func_addr, limit_pc;
/* See if we can determine the end of the prologue via the symbol
table. If so, then return either PC, or the PC after the
prologue, whichever is greater. */
if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
{
CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (gdbarch, func_addr);
if (post_prologue_pc != 0)
return std::max (pc, post_prologue_pc);
}
/* Can't determine prologue from the symbol table, need to examine
instructions. */
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to
provide that bound, then use an arbitrary large number as the
upper bound. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
limit_pc = pc + 128; /* Magic. */
/* Try disassembling prologue. */
return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
}
/* Scan the function prologue for THIS_FRAME and populate the prologue
cache CACHE. */
static void
aarch64_scan_prologue (struct frame_info *this_frame,
struct aarch64_prologue_cache *cache)
{
CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
CORE_ADDR prologue_start;
CORE_ADDR prologue_end;
CORE_ADDR prev_pc = get_frame_pc (this_frame);
struct gdbarch *gdbarch = get_frame_arch (this_frame);
cache->prev_pc = prev_pc;
/* Assume we do not find a frame. */
cache->framereg = -1;
cache->framesize = 0;
if (find_pc_partial_function (block_addr, NULL, &prologue_start,
&prologue_end))
{
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
if (sal.line == 0)
{
/* No line info so use the current PC. */
prologue_end = prev_pc;
}
else if (sal.end < prologue_end)
{
/* The next line begins after the function end. */
prologue_end = sal.end;
}
prologue_end = std::min (prologue_end, prev_pc);
aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
}
else
{
CORE_ADDR frame_loc;
frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
if (frame_loc == 0)
return;
cache->framereg = AARCH64_FP_REGNUM;
cache->framesize = 16;
cache->saved_regs[29].set_addr (0);
cache->saved_regs[30].set_addr (8);
}
}
/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This