From ea58895c9d90a72729aa91d24a0d1fe844b053e6 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Thu, 7 Mar 2024 08:30:16 -0800 Subject: [PATCH 1/4] Use the `xtask` to generate eFuse fields from CSV, instead of at build time --- esp-hal/build.rs | 70 +-- esp-hal/devices/esp32/efuse.csv | 118 ----- esp-hal/devices/esp32c2/efuse.csv | 107 ---- esp-hal/devices/esp32c3/efuse.csv | 187 ------- esp-hal/devices/esp32c6/efuse.csv | 181 ------- esp-hal/devices/esp32h2/efuse.csv | 155 ------ esp-hal/devices/esp32p4/efuse.csv | 119 ----- esp-hal/devices/esp32s2/efuse.csv | 207 -------- esp-hal/devices/esp32s3/efuse.csv | 227 --------- esp-hal/src/soc/efuse_field.rs | 2 - esp-hal/src/soc/esp32/efuse/fields.rs | 225 +++++++++ .../src/soc/esp32/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32c2/efuse/fields.rs | 207 ++++++++ .../soc/esp32c2/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32c3/efuse/fields.rs | 380 ++++++++++++++ .../soc/esp32c3/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32c6/efuse/fields.rs | 384 +++++++++++++++ .../soc/esp32c6/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32h2/efuse/fields.rs | 332 +++++++++++++ .../soc/esp32h2/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32p4/efuse/fields.rs | 259 ++++++++++ .../soc/esp32p4/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32s2/efuse/fields.rs | 413 ++++++++++++++++ .../soc/esp32s2/{efuse.rs => efuse/mod.rs} | 4 +- esp-hal/src/soc/esp32s3/efuse/fields.rs | 464 ++++++++++++++++++ .../soc/esp32s3/{efuse.rs => efuse/mod.rs} | 4 +- xtask/README.md | 12 +- xtask/src/lib.rs | 112 ++++- xtask/src/main.rs | 73 ++- 29 files changed, 2860 insertions(+), 1406 deletions(-) delete mode 100644 esp-hal/devices/esp32/efuse.csv delete mode 100644 esp-hal/devices/esp32c2/efuse.csv delete mode 100644 esp-hal/devices/esp32c3/efuse.csv delete mode 100644 esp-hal/devices/esp32c6/efuse.csv delete mode 100644 esp-hal/devices/esp32h2/efuse.csv delete mode 100644 esp-hal/devices/esp32p4/efuse.csv delete mode 100644 esp-hal/devices/esp32s2/efuse.csv delete mode 100644 esp-hal/devices/esp32s3/efuse.csv create mode 100644 esp-hal/src/soc/esp32/efuse/fields.rs rename esp-hal/src/soc/esp32/{efuse.rs => efuse/mod.rs} (98%) create mode 100644 esp-hal/src/soc/esp32c2/efuse/fields.rs rename esp-hal/src/soc/esp32c2/{efuse.rs => efuse/mod.rs} (99%) create mode 100644 esp-hal/src/soc/esp32c3/efuse/fields.rs rename esp-hal/src/soc/esp32c3/{efuse.rs => efuse/mod.rs} (99%) create mode 100644 esp-hal/src/soc/esp32c6/efuse/fields.rs rename esp-hal/src/soc/esp32c6/{efuse.rs => efuse/mod.rs} (99%) create mode 100644 esp-hal/src/soc/esp32h2/efuse/fields.rs rename esp-hal/src/soc/esp32h2/{efuse.rs => efuse/mod.rs} (98%) create mode 100644 esp-hal/src/soc/esp32p4/efuse/fields.rs rename esp-hal/src/soc/esp32p4/{efuse.rs => efuse/mod.rs} (97%) create mode 100644 esp-hal/src/soc/esp32s2/efuse/fields.rs rename esp-hal/src/soc/esp32s2/{efuse.rs => efuse/mod.rs} (98%) create mode 100644 esp-hal/src/soc/esp32s3/efuse/fields.rs rename esp-hal/src/soc/esp32s3/{efuse.rs => efuse/mod.rs} (99%) diff --git a/esp-hal/build.rs b/esp-hal/build.rs index 7e931f2159b..baae87d4633 100644 --- a/esp-hal/build.rs +++ b/esp-hal/build.rs @@ -2,7 +2,7 @@ use std::{ env, error::Error, fs::{self, File}, - io::{BufRead, BufReader, Write}, + io::{BufRead, Write}, path::{Path, PathBuf}, }; @@ -256,9 +256,6 @@ fn main() -> Result<(), Box> { #[cfg(any(feature = "esp32", feature = "esp32s2"))] File::create(out.join("memory_extras.x"))?.write_all(&generate_memory_extras())?; - // Generate the eFuse table from the selected device's CSV file: - gen_efuse_table(device_name, out)?; - Ok(()) } @@ -329,71 +326,6 @@ fn preprocess_file( Ok(()) } -fn gen_efuse_table(device_name: &str, out_dir: impl AsRef) -> Result<(), Box> { - let src_path = PathBuf::from(format!("devices/{device_name}/efuse.csv")); - let out_path = out_dir.as_ref().join("efuse_fields.rs"); - - println!("cargo:rerun-if-changed={}", src_path.display()); - - let mut writer = File::create(out_path)?; - let mut reader = BufReader::new(File::open(src_path)?); - let mut line = String::with_capacity(128); - - while reader.read_line(&mut line)? > 0 { - if line.ends_with('\n') { - line.pop(); - if line.ends_with('\r') { - line.pop(); - } - } - // drop comment and trim - line.truncate( - if let Some((pfx, _cmt)) = line.split_once('#') { - pfx - } else { - &line - } - .trim() - .len(), - ); - // skip empty - if line.is_empty() { - continue; - } - - let mut fields = line.split(','); - match ( - fields.next().map(|s| s.trim().replace('.', "_")), - fields - .next() - .map(|s| s.trim().replace(|c: char| !c.is_ascii_digit(), "")), - fields - .next() - .map(|s| s.trim()) - .and_then(|s| s.parse::().ok()), - fields - .next() - .map(|s| s.trim()) - .and_then(|s| s.parse::().ok()), - fields.next().map(|s| s.trim()), - ) { - (Some(name), Some(block), Some(bit_off), Some(bit_len), Some(desc)) => { - let desc = desc.replace('[', "`[").replace(']', "]`"); - writeln!(writer, "/// {desc}")?; - writeln!( - writer, - "pub const {name}: EfuseField = EfuseField::new(EfuseBlock::Block{block}, {bit_off}, {bit_len});" - )?; - } - other => eprintln!("Invalid data: {other:?}"), - } - - line.clear(); - } - - Ok(()) -} - fn detect_atomic_extension(ext: &str) -> bool { let rustflags = env::var_os("CARGO_ENCODED_RUSTFLAGS") .unwrap() diff --git a/esp-hal/devices/esp32/efuse.csv b/esp-hal/devices/esp32/efuse.csv deleted file mode 100644 index bd45b0468bb..00000000000 --- a/esp-hal/devices/esp32/efuse.csv +++ /dev/null @@ -1,118 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 369d2d860d34e777c0f7d545a7dfc3c4 - -WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS -WR_DIS.WR_DIS, EFUSE_BLK0, 1, 1, [] wr_dis of WR_DIS -WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of FLASH_CRYPT_CNT -WR_DIS.UART_DOWNLOAD_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of UART_DOWNLOAD_DIS -WR_DIS.MAC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.MAC_CRC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC -WR_DIS.DISABLE_APP_CPU, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU -WR_DIS.DISABLE_BT, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT -WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE -WR_DIS.VOL_LEVEL_HP_INV, EFUSE_BLK0, 3, 1, [] wr_dis of VOL_LEVEL_HP_INV -WR_DIS.CLK8M_FREQ, EFUSE_BLK0, 4, 1, [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ -WR_DIS.ADC_VREF, EFUSE_BLK0, 4, 1, [] wr_dis of ADC_VREF -WR_DIS.XPD_SDIO_REG, EFUSE_BLK0, 5, 1, [] wr_dis of XPD_SDIO_REG -WR_DIS.XPD_SDIO_TIEH, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH -WR_DIS.XPD_SDIO_FORCE, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE -WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CLK -WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_Q -WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_D -WR_DIS.SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_CS0 -WR_DIS.BLOCK1, EFUSE_BLK0, 7, 1, [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1 -WR_DIS.BLOCK2, EFUSE_BLK0, 8, 1, [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2 -WR_DIS.BLOCK3, EFUSE_BLK0, 9, 1, [WR_DIS.BLK3] wr_dis of BLOCK3 -WR_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.ADC1_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_LOW -WR_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_HIGH -WR_DIS.ADC2_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_LOW -WR_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_HIGH -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 9, 1, [] wr_dis of SECURE_VERSION -WR_DIS.MAC_VERSION, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION -WR_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 10, 1, [] wr_dis of BLK3_PART_RESERVE -WR_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 10, 1, [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG -WR_DIS.CODING_SCHEME, EFUSE_BLK0, 10, 1, [] wr_dis of CODING_SCHEME -WR_DIS.KEY_STATUS, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_STATUS -WR_DIS.ABS_DONE_0, EFUSE_BLK0, 12, 1, [] wr_dis of ABS_DONE_0 -WR_DIS.ABS_DONE_1, EFUSE_BLK0, 13, 1, [] wr_dis of ABS_DONE_1 -WR_DIS.JTAG_DISABLE, EFUSE_BLK0, 14, 1, [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE -WR_DIS.CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 15, 1, [] wr_dis of CONSOLE_DEBUG_DISABLE -WR_DIS.DISABLE_DL_ENCRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_ENCRYPT -WR_DIS.DISABLE_DL_DECRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_DECRYPT -WR_DIS.DISABLE_DL_CACHE, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_CACHE -RD_DIS, EFUSE_BLK0, 16, 4, [] Disable reading from BlOCK1-3 -RD_DIS.BLOCK1, EFUSE_BLK0, 16, 1, [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1 -RD_DIS.BLOCK2, EFUSE_BLK0, 17, 1, [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2 -RD_DIS.BLOCK3, EFUSE_BLK0, 18, 1, [RD_DIS.BLK3] rd_dis of BLOCK3 -RD_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC -RD_DIS.CUSTOM_MAC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC -RD_DIS.ADC1_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_LOW -RD_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_HIGH -RD_DIS.ADC2_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_LOW -RD_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_HIGH -RD_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] rd_dis of SECURE_VERSION -RD_DIS.MAC_VERSION, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION -RD_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 19, 1, [] rd_dis of BLK3_PART_RESERVE -RD_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 19, 1, [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG -RD_DIS.CODING_SCHEME, EFUSE_BLK0, 19, 1, [] rd_dis of CODING_SCHEME -RD_DIS.KEY_STATUS, EFUSE_BLK0, 19, 1, [] rd_dis of KEY_STATUS -FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, [] Flash encryption is enabled if this field has an odd number of bits set -UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, [] Disable UART download mode. Valid for ESP32 V3 and newer; only -MAC_FACTORY, EFUSE_BLK0, 32, 48, [MAC_FACTORY] MAC address -MAC_CRC, EFUSE_BLK0, 80, 8, [MAC_FACTORY_CRC] CRC8 for MAC address -DISABLE_APP_CPU, EFUSE_BLK0, 96, 1, [CHIP_VER_DIS_APP_CPU] Disables APP CPU -DISABLE_BT, EFUSE_BLK0, 97, 1, [CHIP_VER_DIS_BT] Disables Bluetooth -CHIP_PACKAGE_4BIT, EFUSE_BLK0, 98, 1, [CHIP_VER_PKG_4BIT] Chip package identifier #4bit -DIS_CACHE, EFUSE_BLK0, 99, 1, [CHIP_VER_DIS_CACHE] Disables cache -SPI_PAD_CONFIG_HD, EFUSE_BLK0, 100, 5, [] read for SPI_pad_config_hd -CHIP_PACKAGE, EFUSE_BLK0, 105, 3, [CHIP_VER_PKG] Chip package identifier -CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise -CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, [] If set; the ESP32's maximum CPU frequency has been rated -BLK3_PART_RESERVE, EFUSE_BLK0, 110, 1, [] BLOCK3 partially served for ADC calibration data -CHIP_VER_REV1, EFUSE_BLK0, 111, 1, [] bit is set to 1 for rev1 silicon -CLK8M_FREQ, EFUSE_BLK0, 128, 8, [CK8M_FREQ] 8MHz clock freq override -ADC_VREF, EFUSE_BLK0, 136, 5, [] True ADC reference voltage -XPD_SDIO_REG, EFUSE_BLK0, 142, 1, [] read for XPD_SDIO_REG -XPD_SDIO_TIEH, EFUSE_BLK0, 143, 1, [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"} -XPD_SDIO_FORCE, EFUSE_BLK0, 144, 1, [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset -SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 160, 5, [] Override SD_CLK pad (GPIO6/SPICLK) -SPI_PAD_CONFIG_Q, EFUSE_BLK0, 165, 5, [] Override SD_DATA_0 pad (GPIO7/SPIQ) -SPI_PAD_CONFIG_D, EFUSE_BLK0, 170, 5, [] Override SD_DATA_1 pad (GPIO8/SPID) -SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 175, 5, [] Override SD_CMD pad (GPIO11/SPICS0) -CHIP_VER_REV2, EFUSE_BLK0, 180, 1, [] -VOL_LEVEL_HP_INV, EFUSE_BLK0, 182, 2, [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) -WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, [] -FLASH_CRYPT_CONFIG, EFUSE_BLK0, 188, 4, [ENCRYPT_CONFIG] Flash encryption config (key tweak bits) -CODING_SCHEME, EFUSE_BLK0, 192, 2, [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"} -CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, [] Disable ROM BASIC interpreter fallback -DISABLE_SDIO_HOST, EFUSE_BLK0, 195, 1, [] -ABS_DONE_0, EFUSE_BLK0, 196, 1, [] Secure boot V1 is enabled for bootloader image -ABS_DONE_1, EFUSE_BLK0, 197, 1, [] Secure boot V2 is enabled for bootloader image -JTAG_DISABLE, EFUSE_BLK0, 198, 1, [DISABLE_JTAG] Disable JTAG -DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, [] Disable flash encryption in UART bootloader -DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, [] Disable flash decryption in UART bootloader -DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, [] Disable flash cache in UART bootloader -KEY_STATUS, EFUSE_BLK0, 202, 1, [] Usage of efuse block 3 (reserved) -BLOCK1, EFUSE_BLK1, 0, MAX_BLK_LEN, [ENCRYPT_FLASH_KEY] Flash encryption key -BLOCK2, EFUSE_BLK2, 0, MAX_BLK_LEN, [SECURE_BOOT_KEY] Security boot key -CUSTOM_MAC_CRC, EFUSE_BLK3, 0, 8, [MAC_CUSTOM_CRC] CRC8 for custom MAC address -MAC_CUSTOM, EFUSE_BLK3, 8, 48, [MAC_CUSTOM] Custom MAC address -ADC1_TP_LOW, EFUSE_BLK3, 96, 7, [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE -ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE -ADC2_TP_LOW, EFUSE_BLK3, 112, 7, [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE -ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE -SECURE_VERSION, EFUSE_BLK3, 128, 32, [] Secure version for anti-rollback -MAC_VERSION, EFUSE_BLK3, 184, 8, [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"} diff --git a/esp-hal/devices/esp32c2/efuse.csv b/esp-hal/devices/esp32c2/efuse.csv deleted file mode 100644 index 129618e649a..00000000000 --- a/esp-hal/devices/esp32c2/efuse.csv +++ /dev/null @@ -1,107 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 897499b0349a608b895d467abbcf006b - -WR_DIS, EFUSE_BLK0, 0, 8, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 1, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 1, 1, [] wr_dis of DIS_PAD_JTAG -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 1, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.XTS_KEY_LENGTH_256, EFUSE_BLK0, 2, 1, [] wr_dis of XTS_KEY_LENGTH_256 -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 3, 1, [] wr_dis of UART_PRINT_CONTROL -WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 3, 1, [] wr_dis of FORCE_SEND_RESUME -WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_DOWNLOAD_MODE -WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 3, 1, [] wr_dis of DIS_DIRECT_BOOT -WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 3, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD -WR_DIS.FLASH_TPUW, EFUSE_BLK0, 3, 1, [] wr_dis of FLASH_TPUW -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 4, 1, [] wr_dis of SECURE_VERSION -WR_DIS.CUSTOM_MAC_USED, EFUSE_BLK0, 4, 1, [WR_DIS.ENABLE_CUSTOM_MAC] wr_dis of CUSTOM_MAC_USED -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 4, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 4, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 5, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.MAC, EFUSE_BLK0, 6, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 6, 1, [] wr_dis of WAFER_VERSION_MINOR -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 6, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.PKG_VERSION, EFUSE_BLK0, 6, 1, [] wr_dis of PKG_VERSION -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 6, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 6, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.OCODE, EFUSE_BLK0, 6, 1, [] wr_dis of OCODE -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 6, 1, [] wr_dis of TEMP_CALIB -WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 -WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 -WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 -WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 -WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_DBIAS_HVT -WR_DIS.DIG_LDO_SLP_DBIAS2, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_SLP_DBIAS2 -WR_DIS.DIG_LDO_SLP_DBIAS26, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_SLP_DBIAS26 -WR_DIS.DIG_LDO_ACT_DBIAS26, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_ACT_DBIAS26 -WR_DIS.DIG_LDO_ACT_STEPD10, EFUSE_BLK0, 6, 1, [] wr_dis of DIG_LDO_ACT_STEPD10 -WR_DIS.RTC_LDO_SLP_DBIAS13, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS13 -WR_DIS.RTC_LDO_SLP_DBIAS29, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS29 -WR_DIS.RTC_LDO_SLP_DBIAS31, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_SLP_DBIAS31 -WR_DIS.RTC_LDO_ACT_DBIAS31, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_ACT_DBIAS31 -WR_DIS.RTC_LDO_ACT_DBIAS13, EFUSE_BLK0, 6, 1, [] wr_dis of RTC_LDO_ACT_DBIAS13 -WR_DIS.ADC_CALIBRATION_3, EFUSE_BLK0, 6, 1, [] wr_dis of ADC_CALIBRATION_3 -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 7, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -RD_DIS, EFUSE_BLK0, 32, 2, [] Disable reading from BlOCK3 -RD_DIS.KEY0, EFUSE_BLK0, 32, 2, [] Read protection for EFUSE_BLK3. KEY0 -RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, [] Read protection for EFUSE_BLK3. KEY0 lower 128-bit key -RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, [] Read protection for EFUSE_BLK3. KEY0 higher 128-bit key -WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} -DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, [] Set this bit to disable pad jtag -DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, [] The bit be set to disable icache in download mode -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, [] The bit be set to disable manual encryption -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, [] Flash encryption key length {0: "128 bits key"; 1: "256 bits key"} -UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, [] Set this bit to force ROM code to send a resume command during SPI boot -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7) -DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, [] This bit set means disable direct_boot mode -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, [] Set this bit to enable secure UART download mode -FLASH_TPUW, EFUSE_BLK0, 49, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value -SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, [] The bit be set to enable secure boot -SECURE_VERSION, EFUSE_BLK0, 54, 4, [] Secure version for anti-rollback -CUSTOM_MAC_USED, EFUSE_BLK0, 58, 1, [ENABLE_CUSTOM_MAC] True if MAC_CUSTOM is burned -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 59, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 60, 1, [] Disables check of blk version major -USER_DATA, EFUSE_BLK1, 0, 88, [] User data block -USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address -MAC_FACTORY, EFUSE_BLK2, 0, 48, [MAC_FACTORY] MAC address -WAFER_VERSION_MINOR, EFUSE_BLK2, 48, 4, [] WAFER_VERSION_MINOR -WAFER_VERSION_MAJOR, EFUSE_BLK2, 52, 2, [] WAFER_VERSION_MAJOR -PKG_VERSION, EFUSE_BLK2, 54, 3, [] EFUSE_PKG_VERSION -BLK_VERSION_MINOR, EFUSE_BLK2, 57, 3, [] Minor version of BLOCK2 {0: "No calib"; 1: "With calib"} -BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, [] Major version of BLOCK2 -OCODE, EFUSE_BLK2, 62, 7, [] OCode -TEMP_CALIB, EFUSE_BLK2, 69, 9, [] Temperature calibration data -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 78, 8, [] ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 86, 5, [] ADC1 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 91, 8, [] ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 99, 6, [] ADC1 calibration voltage at atten3 -DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, [] BLOCK2 digital dbias when hvt -DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, [] BLOCK2 DIG_LDO_DBG0_DBIAS2 -DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, [] BLOCK2 DIG_LDO_DBG0_DBIAS26 -DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, [] BLOCK2 DIG_LDO_ACT_DBIAS26 -DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, [] BLOCK2 DIG_LDO_ACT_STEPD10 -RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, [] BLOCK2 DIG_LDO_SLP_DBIAS13 -RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, [] BLOCK2 DIG_LDO_SLP_DBIAS29 -RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, [] BLOCK2 DIG_LDO_SLP_DBIAS31 -RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, [] BLOCK2 DIG_LDO_ACT_DBIAS31 -RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, [] BLOCK2 DIG_LDO_ACT_DBIAS13 -ADC_CALIBRATION_3, EFUSE_BLK2, 192, 11, [] Store the bit [86:96] of ADC calibration data -KEY0, EFUSE_BLK3, 0, 256, [BLOCK_KEY0] BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption -KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [] 256bit FE key -KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [] 128bit FE key -KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [] 128bit SB key diff --git a/esp-hal/devices/esp32c3/efuse.csv b/esp-hal/devices/esp32c3/efuse.csv deleted file mode 100644 index 4565653928b..00000000000 --- a/esp-hal/devices/esp32c3/efuse.csv +++ /dev/null @@ -1,187 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: a85f874ae2b6538ca48b7c3db4a79531 - -WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE -WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG -WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI -WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE -WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG -WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT -WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 -WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 -WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 -WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 -WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 -WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 -WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 -WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW -WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE -WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT -WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE -WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD -WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL -WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.ERR_RST_ENABLE, EFUSE_BLK0, 19, 1, [] wr_dis of ERR_RST_ENABLE -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR -WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 -WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK -WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q -WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D -WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS -WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD -WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP -WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS -WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 -WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 -WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 -WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 -WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO -WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO -WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20 -WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20 -WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT -WR_DIS.THRES_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of THRES_HVT -WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE -WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 -WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 -WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 -WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 -WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 -WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 -WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 -WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 -WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 -WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 -WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 -WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS -WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO -WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 -RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 -RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 -RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 -RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 -RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache -DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device -DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) -DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"} -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes -USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins -VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Set this bit to vdd spi pin function as gpio -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key -SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key -SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5 -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Disable UART download mode through USB-Serial-JTAG -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode -UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot -SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature) -ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, [] Use BLOCK0 to check error record registers {0: "without check"; 1: "with check"} -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major -MAC_FACTORY, EFUSE_BLK1, 0, 48, [MAC_FACTORY] MAC address -SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI PAD CLK -SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI PAD Q(D1) -SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI PAD D(D0) -SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI PAD CS -SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI PAD HD(D3) -SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI PAD WP(D2) -SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI PAD DQS -SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI PAD D4 -SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI PAD D5 -SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI PAD D6 -SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI PAD D7 -WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits -PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version -BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR -K_RTC_LDO, EFUSE_BLK1, 135, 7, [] BLOCK1 K_RTC_LDO -K_DIG_LDO, EFUSE_BLK1, 142, 7, [] BLOCK1 K_DIG_LDO -V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, [] BLOCK1 voltage of rtc dbias20 -V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, [] BLOCK1 voltage of digital dbias20 -DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, [] BLOCK1 digital dbias when hvt -THRES_HVT, EFUSE_BLK1, 170, 10, [] BLOCK1 pvt threshold when hvt -WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit -WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With calibration"} -TEMP_CALIB, EFUSE_BLK2, 131, 9, [] Temperature calibration data -OCODE, EFUSE_BLK2, 140, 8, [] ADC OCode -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, [] ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, [] ADC1 init code at atten1 -ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, [] ADC1 init code at atten2 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, [] ADC1 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, [] ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, [] ADC1 calibration voltage at atten1 -ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, [] ADC1 calibration voltage at atten2 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, [] ADC1 calibration voltage at atten3 -USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address -KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/esp-hal/devices/esp32c6/efuse.csv b/esp-hal/devices/esp32c6/efuse.csv deleted file mode 100644 index 7d329ee5aa5..00000000000 --- a/esp-hal/devices/esp32c6/efuse.csv +++ /dev/null @@ -1,181 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 709e8ea096e8a03a10006d40d5451a49 - -WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 1, 1, [] wr_dis of CRYPT_DPA_ENABLE -WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SWAP_UART_SDIO_EN -WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE -WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_SERIAL_JTAG -WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI -WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE -WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG -WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT -WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 -WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 -WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 -WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 -WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 -WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 -WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 -WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS -WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW -WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE -WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT -WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE -WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD -WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL -WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR -WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 -WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP -WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP -WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR -WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE -WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 -WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 -WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 -WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 -WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 -WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 -WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 -WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 -WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 -WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 -WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 -WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS -WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO -WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 -RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 -RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 -RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 -RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 -RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged -VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key -SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key -SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5 -SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode -CRYPT_DPA_ENABLE, EFUSE_BLK0, 114, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled -UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced -SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major -MAC_FACTORY, EFUSE_BLK1, 0, 48, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 48, 16, [] Stores the extended bits of MAC address -WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] -WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] -PKG_VERSION, EFUSE_BLK1, 120, 3, [] Package version -BLK_VERSION_MINOR, EFUSE_BLK1, 123, 3, [] BLK_VERSION_MINOR of BLOCK2 -BLK_VERSION_MAJOR, EFUSE_BLK1, 126, 2, [] BLK_VERSION_MAJOR of BLOCK2 -FLASH_CAP, EFUSE_BLK1, 128, 3, [] -FLASH_TEMP, EFUSE_BLK1, 131, 2, [] -FLASH_VENDOR, EFUSE_BLK1, 133, 3, [] -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -TEMP_CALIB, EFUSE_BLK2, 128, 9, [] Temperature calibration data -OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1 -ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1 -ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3 -ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0 -ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1 -ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2 -ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3 -ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4 -ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5 -ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK2, 249, 4, [] ADC1 init code at atten0 ch6 -USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC -KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/esp-hal/devices/esp32h2/efuse.csv b/esp-hal/devices/esp32h2/efuse.csv deleted file mode 100644 index 2df2aad95aa..00000000000 --- a/esp-hal/devices/esp32h2/efuse.csv +++ /dev/null @@ -1,155 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 4df10f83de85f2d830b7c466aabb28e7 - -WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE -WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG -WR_DIS.POWERGLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of POWERGLITCH_EN -WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI -WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE -WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG -WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT -WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 -WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 -WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 -WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 -WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 -WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 -WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 -WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL -WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.ECDSA_FORCE_USE_HARDWARE_K, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K -WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW -WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE -WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT -WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE -WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD -WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL -WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE -WR_DIS.HYS_EN_PAD0, EFUSE_BLK0, 19, 1, [] wr_dis of HYS_EN_PAD0 -WR_DIS.HYS_EN_PAD1, EFUSE_BLK0, 19, 1, [] wr_dis of HYS_EN_PAD1 -WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 -WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.RXIQ_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_VERSION -WR_DIS.RXIQ_0, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_0 -WR_DIS.RXIQ_1, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_1 -WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP -WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP -WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR -WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 -WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 -WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 -WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS -WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO -WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 -RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 -RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 -RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 -RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 -RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -POWERGLITCH_EN, EFUSE_BLK0, 42, 1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged -VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key -SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key -SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5 -SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode -ECDSA_FORCE_USE_HARDWARE_K, EFUSE_BLK0, 114, 1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used -CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled -UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced -SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -HYS_EN_PAD0, EFUSE_BLK0, 154, 6, [] Set bits to enable hysteresis function of PAD0~5 -HYS_EN_PAD1, EFUSE_BLK0, 160, 22, [] Set bits to enable hysteresis function of PAD6~27 -MAC_FACTORY, EFUSE_BLK1, 0, 48, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 48, 16, [] Stores the extended bits of MAC address -RXIQ_VERSION, EFUSE_BLK1, 64, 3, [] RF Calibration data. RXIQ version -RXIQ_0, EFUSE_BLK1, 67, 7, [] RF Calibration data. RXIQ data 0 -RXIQ_1, EFUSE_BLK1, 74, 7, [] RF Calibration data. RXIQ data 1 -WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, [] -WAFER_VERSION_MAJOR, EFUSE_BLK1, 117, 2, [] -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 119, 1, [] Disables check of wafer version major -FLASH_CAP, EFUSE_BLK1, 120, 3, [] -FLASH_TEMP, EFUSE_BLK1, 123, 2, [] -FLASH_VENDOR, EFUSE_BLK1, 125, 3, [] -PKG_VERSION, EFUSE_BLK1, 128, 3, [] Package version -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -BLK_VERSION_MINOR, EFUSE_BLK2, 130, 3, [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 -BLK_VERSION_MAJOR, EFUSE_BLK2, 133, 2, [] BLK_VERSION_MAJOR of BLOCK2 -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK2, 135, 1, [] Disables check of blk version major -USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC -KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/esp-hal/devices/esp32p4/efuse.csv b/esp-hal/devices/esp32p4/efuse.csv deleted file mode 100644 index a18905df370..00000000000 --- a/esp-hal/devices/esp32p4/efuse.csv +++ /dev/null @@ -1,119 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 552d7a824581925566213ca4f4d488dc - -WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 -WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 -WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 -WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 -WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 -WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 -WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 -WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 -WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1 -WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 -WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 -WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 -WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 -RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 -RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 -RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 -RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 -RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 39, 1, [] Enable usb device exchange pins of D+ and D- -USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 40, 1, [] Enable usb otg11 exchange pins of D+ and D- -DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -POWERGLITCH_EN, EFUSE_BLK0, 42, 1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download -DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -USB_PHY_SEL, EFUSE_BLK0, 57, 1, [] TBD -KM_HUK_GEN_STATE_LOW, EFUSE_BLK0, 58, 6, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid -KM_HUK_GEN_STATE_HIGH, EFUSE_BLK0, 64, 3, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid -KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 67, 2, [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles -KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 69, 4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds -FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 73, 4, [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds -FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 77, 1, [] Set this bit to disable software written init key; and force use efuse_init_key -XTS_KEY_LENGTH_256, EFUSE_BLK0, 78, 1, [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key -SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key -SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5 -SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode -ECDSA_ENABLE_SOFT_K, EFUSE_BLK0, 114, 1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used -CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled -FLASH_TYPE, EFUSE_BLK0, 119, 1, [] The type of interfaced flash. 0: four data lines; 1: eight data lines -FLASH_PAGE_SIZE, EFUSE_BLK0, 120, 2, [] Set flash page size -FLASH_ECC_EN, EFUSE_BLK0, 122, 1, [] Set this bit to enable ecc for flash boot -DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 123, 1, [] Set this bit to disable download via USB-OTG -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] TBD -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled -UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing -FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced -SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled -DCDC_VSET, EFUSE_BLK0, 155, 5, [] Set the dcdc voltage default -PXA0_TIEH_SEL_0, EFUSE_BLK0, 160, 2, [] TBD -PXA0_TIEH_SEL_1, EFUSE_BLK0, 162, 2, [] TBD -PXA0_TIEH_SEL_2, EFUSE_BLK0, 164, 2, [] TBD -PXA0_TIEH_SEL_3, EFUSE_BLK0, 166, 2, [] TBD -KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 168, 4, [] TBD -HP_PWR_SRC_SEL, EFUSE_BLK0, 178, 1, [] HP system power source select. 0:LDO. 1: DCDC -DCDC_VSET_EN, EFUSE_BLK0, 179, 1, [] Select dcdc vset use efuse_dcdc_vset -DIS_WDT, EFUSE_BLK0, 180, 1, [] Set this bit to disable watch dog -DIS_SWD, EFUSE_BLK0, 181, 1, [] Set this bit to disable super-watchdog -MAC, EFUSE_BLK1, 0, 48, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 48, 16, [] Stores the extended bits of MAC address [0] -BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [SYS_DATA_PART1] System data part 1 -USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO, not defined yet) -KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/esp-hal/devices/esp32s2/efuse.csv b/esp-hal/devices/esp32s2/efuse.csv deleted file mode 100644 index 44b85cc9df5..00000000000 --- a/esp-hal/devices/esp32s2/efuse.csv +++ /dev/null @@ -1,207 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 888a61f6f500d9c7ee0aa32016b0bee7 - -WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE -WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE -WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.DIS_USB, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI -WR_DIS.DIS_BOOT_REMAP, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_BOOT_REMAP -WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of SOFT_DIS_JTAG -WR_DIS.HARD_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of HARD_DIS_JTAG -WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT -WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD -WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH -WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE -WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 -WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 -WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 -WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 -WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 -WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 -WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 -WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW -WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE -WR_DIS.DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_LEGACY_SPI_BOOT -WR_DIS.UART_PRINT_CHANNEL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CHANNEL -WR_DIS.DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_DOWNLOAD_MODE -WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD -WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL -WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION -WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE -WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 -WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK -WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q -WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D -WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS -WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD -WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP -WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS -WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 -WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 -WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 -WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI -WR_DIS.FLASH_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VERSION -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.PSRAM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VERSION -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO -WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.ADC_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of ADC_CALIB -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.RTCCALIB_V1IDX_A10H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10H -WR_DIS.RTCCALIB_V1IDX_A11H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11H -WR_DIS.RTCCALIB_V1IDX_A12H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12H -WR_DIS.RTCCALIB_V1IDX_A13H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13H -WR_DIS.RTCCALIB_V1IDX_A20H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20H -WR_DIS.RTCCALIB_V1IDX_A21H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21H -WR_DIS.RTCCALIB_V1IDX_A22H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22H -WR_DIS.RTCCALIB_V1IDX_A23H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23H -WR_DIS.RTCCALIB_V1IDX_A10L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10L -WR_DIS.RTCCALIB_V1IDX_A11L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11L -WR_DIS.RTCCALIB_V1IDX_A12L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12L -WR_DIS.RTCCALIB_V1IDX_A13L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13L -WR_DIS.RTCCALIB_V1IDX_A20L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20L -WR_DIS.RTCCALIB_V1IDX_A21L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21L -WR_DIS.RTCCALIB_V1IDX_A22L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22L -WR_DIS.RTCCALIB_V1IDX_A23L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23L -WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 -WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 -WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 -WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS -WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE -WR_DIS.USB_FORCE_NOPERSIST, EFUSE_BLK0, 30, 1, [] wr_dis of USB_FORCE_NOPERSIST -WR_DIS.BLOCK0_VERSION, EFUSE_BLK0, 30, 1, [] wr_dis of BLOCK0_VERSION -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 -RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 -RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 -RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 -RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 -RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache -DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache -DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Disables Icache when SoC is in Download mode -DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Disables Dcache when SoC is in Download mode -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode -DIS_USB, EFUSE_BLK0, 45, 1, [] Set this bit to disable USB OTG function -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable the TWAI Controller function -DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, [] Disables capability to Remap RAM to ROM address space -SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral -HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, [] Hardware disables JTAG permanently -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, [] Disables flash encryption when in download boot modes -USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, [] Set this bit to exchange USB D+ and D- pins -USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, [EXT_PHY_ENABLE] Set this bit to enable external USB PHY -USB_FORCE_NOPERSIST, EFUSE_BLK0, 58, 1, [] If set; forces USB BVALID to 1 -BLOCK0_VERSION, EFUSE_BLK0, 59, 2, [] BLOCK0 efuse version -VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on -VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} -VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key -SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key -SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of KEY0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of KEY1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of KEY2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of KEY3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of KEY4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of KEY5 -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable aggressive secure boot key revocation mode -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable all download boot modes -DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, [] Set this bit to disable Legacy SPI boot mode -UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"} -DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Set this bit to disable use of USB OTG in UART download boot mode -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode (read/write flash only) -UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} -PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} -FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} -FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, [] If set; forces ROM code to send an SPI flash resume command during SPI boot -SECURE_VERSION, EFUSE_BLK0, 139, 16, [] Secure version (used by ESP-IDF anti-rollback feature) -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major -MAC_FACTORY, EFUSE_BLK1, 0, 48, [MAC_FACTORY] MAC address -SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK -SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1) -SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0) -SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS -SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3) -SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2) -SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS -SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4 -SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5 -SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6 -SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7 -WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, [] WAFER_VERSION_MAJOR -WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 116, 1, [] WAFER_VERSION_MINOR most significant bit -FLASH_VERSION, EFUSE_BLK1, 117, 4, [] Flash version -BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, [] BLK_VERSION_MAJOR -PSRAM_VERSION, EFUSE_BLK1, 124, 4, [] PSRAM version -PKG_VERSION, EFUSE_BLK1, 128, 4, [] Package version -WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 132, 3, [] WAFER_VERSION_MINOR least significant bits -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -ADC_CALIB, EFUSE_BLK2, 128, 4, [] 4 bit of ADC calibration -BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"} -TEMP_CALIB, EFUSE_BLK2, 135, 9, [] Temperature calibration data -RTCCALIB_V1IDX_A10H, EFUSE_BLK2, 144, 8, [] -RTCCALIB_V1IDX_A11H, EFUSE_BLK2, 152, 8, [] -RTCCALIB_V1IDX_A12H, EFUSE_BLK2, 160, 8, [] -RTCCALIB_V1IDX_A13H, EFUSE_BLK2, 168, 8, [] -RTCCALIB_V1IDX_A20H, EFUSE_BLK2, 176, 8, [] -RTCCALIB_V1IDX_A21H, EFUSE_BLK2, 184, 8, [] -RTCCALIB_V1IDX_A22H, EFUSE_BLK2, 192, 8, [] -RTCCALIB_V1IDX_A23H, EFUSE_BLK2, 200, 8, [] -RTCCALIB_V1IDX_A10L, EFUSE_BLK2, 208, 6, [] -RTCCALIB_V1IDX_A11L, EFUSE_BLK2, 214, 6, [] -RTCCALIB_V1IDX_A12L, EFUSE_BLK2, 220, 6, [] -RTCCALIB_V1IDX_A13L, EFUSE_BLK2, 226, 6, [] -RTCCALIB_V1IDX_A20L, EFUSE_BLK2, 232, 6, [] -RTCCALIB_V1IDX_A21L, EFUSE_BLK2, 238, 6, [] -RTCCALIB_V1IDX_A22L, EFUSE_BLK2, 244, 6, [] -RTCCALIB_V1IDX_A23L, EFUSE_BLK2, 250, 6, [] -USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC -KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/esp-hal/devices/esp32s3/efuse.csv b/esp-hal/devices/esp32s3/efuse.csv deleted file mode 100644 index e23191cb5ea..00000000000 --- a/esp-hal/devices/esp32s3/efuse.csv +++ /dev/null @@ -1,227 +0,0 @@ - -# field_name, | efuse_block, | bit_start, | bit_count, |comment # -# | (EFUSE_BLK0 | (0..255) | (1-256) | # -# | EFUSE_BLK1 | | | # -# | ...) | | | # -########################################################################## -# !!!!!!!!!!! # -# After editing this file, run the command manually "idf.py efuse-common-table" -# this will generate new source files, next rebuild all the sources. -# !!!!!!!!!!! # - -# This file was generated by regtools.py based on the efuses.yaml file with the version: 6925129eca795b8b087d31be539740ec - -WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses -WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE -WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE -WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.DIS_USB_OTG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI -WR_DIS.DIS_APP_CPU, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_APP_CPU -WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG -WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT -WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG -WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG -WR_DIS.STRAP_JTAG_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of STRAP_JTAG_SEL -WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of USB_PHY_SEL -WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD -WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH -WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE -WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL -WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT -WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 -WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 -WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 -WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 -WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 -WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 -WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 -WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 -WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN -WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE -WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW -WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE -WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT -WR_DIS.FLASH_ECC_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_MODE -WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE -WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD -WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL -WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION -WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE -WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE -WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN -WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME -WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION -WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 19, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR -WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 -WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK -WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q -WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D -WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS -WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD -WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP -WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS -WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4 -WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5 -WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6 -WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7 -WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO -WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO -WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20 -WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20 -WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT -WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.ADC2_CAL_VOL_ATTEN3, EFUSE_BLK0, 20, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN3 -WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE -WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 -WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 -WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 -WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 -WR_DIS.ADC2_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN0 -WR_DIS.ADC2_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN1 -WR_DIS.ADC2_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN2 -WR_DIS.ADC2_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN3 -WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 -WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 -WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 -WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 -WR_DIS.ADC2_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN0 -WR_DIS.ADC2_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN1 -WR_DIS.ADC2_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN2 -WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA -WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC -WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 -WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 -WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 -WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 -WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 -WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 -WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 -WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS -WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE -WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 -RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 -RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 -RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 -RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 -RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 -RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 -RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache -DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache -DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7) -DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7) -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode -DIS_USB_OTG, EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function -DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes -USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins -USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, [EXT_PHY_ENABLE] Set this bit to enable external PHY -VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] SPI regulator power up signal -VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} -VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"} -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} -SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key -SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key -SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key -KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0 -KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1 -KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2 -KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3 -KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4 -KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5 -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot -DIS_USB_JTAG, EFUSE_BLK0, 118, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device -DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, [DIS_USB_DEVICE] Set this bit to disable usb device -STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0 -USB_PHY_SEL, EFUSE_BLK0, 121, 1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"} -FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7) -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"} -FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"} -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode -UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} -PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} -FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"} -FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, [] Set Flash page size -FLASH_ECC_EN, EFUSE_BLK0, 140, 1, [] Set 1 to enable ECC for flash boot -FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot -SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature) -DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, [] Set this bit to disable download through USB-OTG -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major -MAC_FACTORY, EFUSE_BLK1, 0, 48, [MAC_FACTORY] MAC address -SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK -SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1) -SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0) -SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS -SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3) -SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2) -SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS -SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4 -SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5 -SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6 -SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7 -WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits -PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version -BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR -K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO -K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO -V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20 -V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, [] BLOCK1 voltage of digital dbias20 -DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, [] BLOCK1 digital dbias when hvt -WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit -WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR -ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3 -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"} -TEMP_CALIB, EFUSE_BLK2, 132, 9, [] Temperature calibration data -OCODE, EFUSE_BLK2, 141, 8, [] ADC OCode -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1 -ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3 -ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0 -ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1 -ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2 -ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, [] ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, [] ADC1 calibration voltage at atten1 -ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, [] ADC1 calibration voltage at atten2 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, [] ADC1 calibration voltage at atten3 -ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, [] ADC2 calibration voltage at atten0 -ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, [] ADC2 calibration voltage at atten1 -ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, [] ADC2 calibration voltage at atten2 -USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data -USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC -KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data -KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data -KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data -KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data -KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data -SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/esp-hal/src/soc/efuse_field.rs b/esp-hal/src/soc/efuse_field.rs index 8da31abf633..d0de7a46a8f 100644 --- a/esp-hal/src/soc/efuse_field.rs +++ b/esp-hal/src/soc/efuse_field.rs @@ -1,7 +1,5 @@ use crate::soc::efuse::{Efuse, EfuseBlock}; -include!(concat!(env!("OUT_DIR"), "/efuse_fields.rs")); - /// The bit field for get access to efuse data #[derive(Clone, Copy)] pub struct EfuseField { diff --git a/esp-hal/src/soc/esp32/efuse/fields.rs b/esp-hal/src/soc/esp32/efuse/fields.rs new file mode 100644 index 00000000000..b1fb8798a78 --- /dev/null +++ b/esp-hal/src/soc/esp32/efuse/fields.rs @@ -0,0 +1,225 @@ +//! eFuse fields for the ESP32. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Efuse write disable mask +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 16); +/// `[WR_DIS.EFUSE_RD_DISABLE]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of WR_DIS +pub const WR_DIS_WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 1, 1); +/// `[]` wr_dis of FLASH_CRYPT_CNT +pub const WR_DIS_FLASH_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of UART_DOWNLOAD_DIS +pub const WR_DIS_UART_DOWNLOAD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[WR_DIS.MAC_FACTORY_CRC]` wr_dis of MAC_CRC +pub const WR_DIS_MAC_CRC: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[WR_DIS.CHIP_VER_DIS_APP_CPU]` wr_dis of DISABLE_APP_CPU +pub const WR_DIS_DISABLE_APP_CPU: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[WR_DIS.CHIP_VER_DIS_BT]` wr_dis of DISABLE_BT +pub const WR_DIS_DISABLE_BT: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[WR_DIS.CHIP_VER_DIS_CACHE]` wr_dis of DIS_CACHE +pub const WR_DIS_DIS_CACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of VOL_LEVEL_HP_INV +pub const WR_DIS_VOL_LEVEL_HP_INV: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[WR_DIS.CK8M_FREQ]` wr_dis of CLK8M_FREQ +pub const WR_DIS_CLK8M_FREQ: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of ADC_VREF +pub const WR_DIS_ADC_VREF: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of XPD_SDIO_REG +pub const WR_DIS_XPD_SDIO_REG: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[WR_DIS.SDIO_TIEH]` wr_dis of XPD_SDIO_TIEH +pub const WR_DIS_XPD_SDIO_TIEH: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[WR_DIS.SDIO_FORCE]` wr_dis of XPD_SDIO_FORCE +pub const WR_DIS_XPD_SDIO_FORCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CLK +pub const WR_DIS_SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_Q +pub const WR_DIS_SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D +pub const WR_DIS_SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CS0 +pub const WR_DIS_SPI_PAD_CONFIG_CS0: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1]` wr_dis of BLOCK1 +pub const WR_DIS_BLOCK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2]` wr_dis of BLOCK2 +pub const WR_DIS_BLOCK2: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.BLK3]` wr_dis of BLOCK3 +pub const WR_DIS_BLOCK3: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.MAC_CUSTOM_CRC]` wr_dis of CUSTOM_MAC_CRC +pub const WR_DIS_CUSTOM_MAC_CRC: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[]` wr_dis of ADC1_TP_LOW +pub const WR_DIS_ADC1_TP_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[]` wr_dis of ADC1_TP_HIGH +pub const WR_DIS_ADC1_TP_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[]` wr_dis of ADC2_TP_LOW +pub const WR_DIS_ADC2_TP_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[]` wr_dis of ADC2_TP_HIGH +pub const WR_DIS_ADC2_TP_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.MAC_CUSTOM_VER]` wr_dis of MAC_VERSION +pub const WR_DIS_MAC_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[]` wr_dis of BLK3_PART_RESERVE +pub const WR_DIS_BLK3_PART_RESERVE: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.ENCRYPT_CONFIG]` wr_dis of FLASH_CRYPT_CONFIG +pub const WR_DIS_FLASH_CRYPT_CONFIG: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[]` wr_dis of CODING_SCHEME +pub const WR_DIS_CODING_SCHEME: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[]` wr_dis of KEY_STATUS +pub const WR_DIS_KEY_STATUS: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[]` wr_dis of ABS_DONE_0 +pub const WR_DIS_ABS_DONE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[]` wr_dis of ABS_DONE_1 +pub const WR_DIS_ABS_DONE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[WR_DIS.DISABLE_JTAG]` wr_dis of JTAG_DISABLE +pub const WR_DIS_JTAG_DISABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 14, 1); +/// `[]` wr_dis of CONSOLE_DEBUG_DISABLE +pub const WR_DIS_CONSOLE_DEBUG_DISABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of DISABLE_DL_ENCRYPT +pub const WR_DIS_DISABLE_DL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of DISABLE_DL_DECRYPT +pub const WR_DIS_DISABLE_DL_DECRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of DISABLE_DL_CACHE +pub const WR_DIS_DISABLE_DL_CACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` Disable reading from BlOCK1-3 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 16, 4); +/// `[RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1]` rd_dis of BLOCK1 +pub const RD_DIS_BLOCK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 16, 1); +/// `[RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2]` rd_dis of BLOCK2 +pub const RD_DIS_BLOCK2: EfuseField = EfuseField::new(EfuseBlock::Block0, 17, 1); +/// `[RD_DIS.BLK3]` rd_dis of BLOCK3 +pub const RD_DIS_BLOCK3: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[RD_DIS.MAC_CUSTOM_CRC]` rd_dis of CUSTOM_MAC_CRC +pub const RD_DIS_CUSTOM_MAC_CRC: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[RD_DIS.MAC_CUSTOM]` rd_dis of CUSTOM_MAC +pub const RD_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` rd_dis of ADC1_TP_LOW +pub const RD_DIS_ADC1_TP_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` rd_dis of ADC1_TP_HIGH +pub const RD_DIS_ADC1_TP_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` rd_dis of ADC2_TP_LOW +pub const RD_DIS_ADC2_TP_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` rd_dis of ADC2_TP_HIGH +pub const RD_DIS_ADC2_TP_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` rd_dis of SECURE_VERSION +pub const RD_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[RD_DIS.MAC_CUSTOM_VER]` rd_dis of MAC_VERSION +pub const RD_DIS_MAC_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` rd_dis of BLK3_PART_RESERVE +pub const RD_DIS_BLK3_PART_RESERVE: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[RD_DIS.ENCRYPT_CONFIG]` rd_dis of FLASH_CRYPT_CONFIG +pub const RD_DIS_FLASH_CRYPT_CONFIG: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` rd_dis of CODING_SCHEME +pub const RD_DIS_CODING_SCHEME: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` rd_dis of KEY_STATUS +pub const RD_DIS_KEY_STATUS: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` Flash encryption is enabled if this field has an odd number of bits set +pub const FLASH_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 7); +/// `[]` Disable UART download mode. Valid for ESP32 V3 and newer; only +pub const UART_DOWNLOAD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 48); +/// `[MAC_FACTORY_CRC]` CRC8 for MAC address +pub const MAC_CRC: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 8); +/// `[CHIP_VER_DIS_APP_CPU]` Disables APP CPU +pub const DISABLE_APP_CPU: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 1); +/// `[CHIP_VER_DIS_BT]` Disables Bluetooth +pub const DISABLE_BT: EfuseField = EfuseField::new(EfuseBlock::Block0, 97, 1); +/// `[CHIP_VER_PKG_4BIT]` Chip package identifier +pub const CHIP_PACKAGE_4BIT: EfuseField = EfuseField::new(EfuseBlock::Block0, 98, 1); +/// `[CHIP_VER_DIS_CACHE]` Disables cache +pub const DIS_CACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 99, 1); +/// `[]` read for SPI_pad_config_hd +pub const SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 5); +/// `[CHIP_VER_PKG]` Chip package identifier +pub const CHIP_PACKAGE: EfuseField = EfuseField::new(EfuseBlock::Block0, 105, 3); +/// `[]` If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU +/// frequency is rated for 160MHz. 240MHz otherwise +pub const CHIP_CPU_FREQ_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 1); +/// `[]` If set; the ESP32's maximum CPU frequency has been rated +pub const CHIP_CPU_FREQ_RATED: EfuseField = EfuseField::new(EfuseBlock::Block0, 109, 1); +/// `[]` BLOCK3 partially served for ADC calibration data +pub const BLK3_PART_RESERVE: EfuseField = EfuseField::new(EfuseBlock::Block0, 110, 1); +/// `[]` bit is set to 1 for rev1 silicon +pub const CHIP_VER_REV1: EfuseField = EfuseField::new(EfuseBlock::Block0, 111, 1); +/// `[CK8M_FREQ]` 8MHz clock freq override +pub const CLK8M_FREQ: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 8); +/// `[]` True ADC reference voltage +pub const ADC_VREF: EfuseField = EfuseField::new(EfuseBlock::Block0, 136, 5); +/// `[]` read for XPD_SDIO_REG +pub const XPD_SDIO_REG: EfuseField = EfuseField::new(EfuseBlock::Block0, 142, 1); +/// `[SDIO_TIEH]` If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"} +pub const XPD_SDIO_TIEH: EfuseField = EfuseField::new(EfuseBlock::Block0, 143, 1); +/// `[SDIO_FORCE]` Ignore MTDI pin (GPIO12) for VDD_SDIO on reset +pub const XPD_SDIO_FORCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 144, 1); +/// `[]` Override SD_CLK pad (GPIO6/SPICLK) +pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 5); +/// `[]` Override SD_DATA_0 pad (GPIO7/SPIQ) +pub const SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block0, 165, 5); +/// `[]` Override SD_DATA_1 pad (GPIO8/SPID) +pub const SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block0, 170, 5); +/// `[]` Override SD_CMD pad (GPIO11/SPICS0) +pub const SPI_PAD_CONFIG_CS0: EfuseField = EfuseField::new(EfuseBlock::Block0, 175, 5); +/// `[]` +pub const CHIP_VER_REV2: EfuseField = EfuseField::new(EfuseBlock::Block0, 180, 1); +/// `[]` This field stores the voltage level for CPU to run at 240 MHz; or for +/// flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: +/// level 4. (RO) +pub const VOL_LEVEL_HP_INV: EfuseField = EfuseField::new(EfuseBlock::Block0, 182, 2); +/// `[]` +pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 184, 2); +/// `[ENCRYPT_CONFIG]` Flash encryption config (key tweak bits) +pub const FLASH_CRYPT_CONFIG: EfuseField = EfuseField::new(EfuseBlock::Block0, 188, 4); +/// `[]` Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: +/// "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not +/// supported"; 3: "NONE (BLK1-3 len=256 bits)"} +pub const CODING_SCHEME: EfuseField = EfuseField::new(EfuseBlock::Block0, 192, 2); +/// `[]` Disable ROM BASIC interpreter fallback +pub const CONSOLE_DEBUG_DISABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 194, 1); +/// `[]` +pub const DISABLE_SDIO_HOST: EfuseField = EfuseField::new(EfuseBlock::Block0, 195, 1); +/// `[]` Secure boot V1 is enabled for bootloader image +pub const ABS_DONE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 196, 1); +/// `[]` Secure boot V2 is enabled for bootloader image +pub const ABS_DONE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 197, 1); +/// `[DISABLE_JTAG]` Disable JTAG +pub const JTAG_DISABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 198, 1); +/// `[]` Disable flash encryption in UART bootloader +pub const DISABLE_DL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 199, 1); +/// `[]` Disable flash decryption in UART bootloader +pub const DISABLE_DL_DECRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 200, 1); +/// `[]` Disable flash cache in UART bootloader +pub const DISABLE_DL_CACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 201, 1); +/// `[]` Usage of efuse block 3 (reserved) +pub const KEY_STATUS: EfuseField = EfuseField::new(EfuseBlock::Block0, 202, 1); +/// `[MAC_CUSTOM_CRC]` CRC8 for custom MAC address +pub const CUSTOM_MAC_CRC: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 8); +/// `[MAC_CUSTOM]` Custom MAC address +pub const MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 8, 48); +/// `[]` ADC1 Two Point calibration low point. Only valid if +/// EFUSE_RD_BLK3_PART_RESERVE +pub const ADC1_TP_LOW: EfuseField = EfuseField::new(EfuseBlock::Block3, 96, 7); +/// `[]` ADC1 Two Point calibration high point. Only valid if +/// EFUSE_RD_BLK3_PART_RESERVE +pub const ADC1_TP_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block3, 103, 9); +/// `[]` ADC2 Two Point calibration low point. Only valid if +/// EFUSE_RD_BLK3_PART_RESERVE +pub const ADC2_TP_LOW: EfuseField = EfuseField::new(EfuseBlock::Block3, 112, 7); +/// `[]` ADC2 Two Point calibration high point. Only valid if +/// EFUSE_RD_BLK3_PART_RESERVE +pub const ADC2_TP_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block3, 119, 9); +/// `[]` Secure version for anti-rollback +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block3, 128, 32); +/// `[MAC_CUSTOM_VER]` Version of the MAC field {1: "Custom MAC in BLOCK3"} +pub const MAC_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block3, 184, 8); diff --git a/esp-hal/src/soc/esp32/efuse.rs b/esp-hal/src/soc/esp32/efuse/mod.rs similarity index 98% rename from esp-hal/src/soc/esp32/efuse.rs rename to esp-hal/src/soc/esp32/efuse/mod.rs index e1849bb2011..09e9f3e84a3 100644 --- a/esp-hal/src/soc/esp32/efuse.rs +++ b/esp-hal/src/soc/esp32/efuse/mod.rs @@ -35,8 +35,10 @@ use fugit::{HertzU32, RateExtU32}; +pub use self::fields::*; use crate::peripherals::EFUSE; -pub use crate::soc::efuse_field::*; + +mod fields; pub struct Efuse; diff --git a/esp-hal/src/soc/esp32c2/efuse/fields.rs b/esp-hal/src/soc/esp32c2/efuse/fields.rs new file mode 100644 index 00000000000..7897616a5c4 --- /dev/null +++ b/esp-hal/src/soc/esp32c2/efuse/fields.rs @@ -0,0 +1,207 @@ +//! eFuse fields for the ESP32-C2. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 8); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of WDT_DELAY_SEL +pub const WR_DIS_WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 1, 1); +/// `[]` wr_dis of DIS_PAD_JTAG +pub const WR_DIS_DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 1, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_ICACHE +pub const WR_DIS_DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 1, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +pub const WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of XTS_KEY_LENGTH_256 +pub const WR_DIS_XTS_KEY_LENGTH_256: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of UART_PRINT_CONTROL +pub const WR_DIS_UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of FORCE_SEND_RESUME +pub const WR_DIS_FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MODE +pub const WR_DIS_DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of DIS_DIRECT_BOOT +pub const WR_DIS_DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of ENABLE_SECURITY_DOWNLOAD +pub const WR_DIS_ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of FLASH_TPUW +pub const WR_DIS_FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[WR_DIS.ENABLE_CUSTOM_MAC]` wr_dis of CUSTOM_MAC_USED +pub const WR_DIS_CUSTOM_MAC_USED: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR +pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField = + EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR +pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR +pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of OCODE +pub const WR_DIS_OCODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of TEMP_CALIB +pub const WR_DIS_TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN3 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN0 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN3 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of DIG_DBIAS_HVT +pub const WR_DIS_DIG_DBIAS_HVT: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of DIG_LDO_SLP_DBIAS2 +pub const WR_DIS_DIG_LDO_SLP_DBIAS2: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of DIG_LDO_SLP_DBIAS26 +pub const WR_DIS_DIG_LDO_SLP_DBIAS26: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of DIG_LDO_ACT_DBIAS26 +pub const WR_DIS_DIG_LDO_ACT_DBIAS26: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of DIG_LDO_ACT_STEPD10 +pub const WR_DIS_DIG_LDO_ACT_STEPD10: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of RTC_LDO_SLP_DBIAS13 +pub const WR_DIS_RTC_LDO_SLP_DBIAS13: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of RTC_LDO_SLP_DBIAS29 +pub const WR_DIS_RTC_LDO_SLP_DBIAS29: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of RTC_LDO_SLP_DBIAS31 +pub const WR_DIS_RTC_LDO_SLP_DBIAS31: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of RTC_LDO_ACT_DBIAS31 +pub const WR_DIS_RTC_LDO_ACT_DBIAS31: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of RTC_LDO_ACT_DBIAS13 +pub const WR_DIS_RTC_LDO_ACT_DBIAS13: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of ADC_CALIBRATION_3 +pub const WR_DIS_ADC_CALIBRATION_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[]` Disable reading from BlOCK3 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 2); +/// `[]` Read protection for EFUSE_BLK3. KEY0 +pub const RD_DIS_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 2); +/// `[]` Read protection for EFUSE_BLK3. KEY0 lower 128-bit key +pub const RD_DIS_KEY0_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[]` Read protection for EFUSE_BLK3. KEY0 higher 128-bit key +pub const RD_DIS_KEY0_HI: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[]` RTC watchdog timeout threshold; in unit of slow clock cycle {0: +/// "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 2); +/// `[]` Set this bit to disable pad jtag +pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[]` The bit be set to disable icache in download mode +pub const DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[]` The bit be set to disable manual encryption +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disables +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 39, 3); +/// `[]` Flash encryption key length {0: "128 bits key"; 1: "256 bits key"} +pub const XTS_KEY_LENGTH_256: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[]` Set the default UARTboot message output mode {0: "Enable"; 1: "Enable +/// when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: +/// "Disable"} +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 43, 2); +/// `[]` Set this bit to force ROM code to send a resume command during SPI boot +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1); +/// `[]` Set this bit to disable download mode (boot_mode`[3:0]` = 0; 1; 2; 4; +/// 5; 6; 7) +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` This bit set means disable direct_boot mode +pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Set this bit to enable secure UART download mode +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 1); +/// `[]` Configures flash waiting time after power-up; in unit of ms. If the +/// value is less than 15; the waiting time is the configurable value. +/// Otherwise; the waiting time is twice the configurable value +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 49, 4); +/// `[]` The bit be set to enable secure boot +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 53, 1); +/// `[]` Secure version for anti-rollback +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 54, 4); +/// `[ENABLE_CUSTOM_MAC]` True if MAC_CUSTOM is burned +pub const CUSTOM_MAC_USED: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 1); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 59, 1); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 60, 1); +/// `[]` User data block +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 88); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC address +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 48); +/// `[]` WAFER_VERSION_MINOR +pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 48, 4); +/// `[]` WAFER_VERSION_MAJOR +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 52, 2); +/// `[]` EFUSE_PKG_VERSION +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block2, 54, 3); +/// `[]` Minor version of BLOCK2 {0: "No calib"; 1: "With calib"} +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 57, 3); +/// `[]` Major version of BLOCK2 +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 60, 2); +/// `[]` OCode +pub const OCODE: EfuseField = EfuseField::new(EfuseBlock::Block2, 62, 7); +/// `[]` Temperature calibration data +pub const TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 69, 9); +/// `[]` ADC1 init code at atten0 +pub const ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 78, 8); +/// `[]` ADC1 init code at atten3 +pub const ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 86, 5); +/// `[]` ADC1 calibration voltage at atten0 +pub const ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 91, 8); +/// `[]` ADC1 calibration voltage at atten3 +pub const ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 99, 6); +/// `[]` BLOCK2 digital dbias when hvt +pub const DIG_DBIAS_HVT: EfuseField = EfuseField::new(EfuseBlock::Block2, 105, 5); +/// `[]` BLOCK2 DIG_LDO_DBG0_DBIAS2 +pub const DIG_LDO_SLP_DBIAS2: EfuseField = EfuseField::new(EfuseBlock::Block2, 110, 7); +/// `[]` BLOCK2 DIG_LDO_DBG0_DBIAS26 +pub const DIG_LDO_SLP_DBIAS26: EfuseField = EfuseField::new(EfuseBlock::Block2, 117, 8); +/// `[]` BLOCK2 DIG_LDO_ACT_DBIAS26 +pub const DIG_LDO_ACT_DBIAS26: EfuseField = EfuseField::new(EfuseBlock::Block2, 125, 6); +/// `[]` BLOCK2 DIG_LDO_ACT_STEPD10 +pub const DIG_LDO_ACT_STEPD10: EfuseField = EfuseField::new(EfuseBlock::Block2, 131, 4); +/// `[]` BLOCK2 DIG_LDO_SLP_DBIAS13 +pub const RTC_LDO_SLP_DBIAS13: EfuseField = EfuseField::new(EfuseBlock::Block2, 135, 7); +/// `[]` BLOCK2 DIG_LDO_SLP_DBIAS29 +pub const RTC_LDO_SLP_DBIAS29: EfuseField = EfuseField::new(EfuseBlock::Block2, 142, 9); +/// `[]` BLOCK2 DIG_LDO_SLP_DBIAS31 +pub const RTC_LDO_SLP_DBIAS31: EfuseField = EfuseField::new(EfuseBlock::Block2, 151, 6); +/// `[]` BLOCK2 DIG_LDO_ACT_DBIAS31 +pub const RTC_LDO_ACT_DBIAS31: EfuseField = EfuseField::new(EfuseBlock::Block2, 157, 6); +/// `[]` BLOCK2 DIG_LDO_ACT_DBIAS13 +pub const RTC_LDO_ACT_DBIAS13: EfuseField = EfuseField::new(EfuseBlock::Block2, 163, 8); +/// `[]` Store the bit `[86:96]` of ADC calibration data +pub const ADC_CALIBRATION_3: EfuseField = EfuseField::new(EfuseBlock::Block2, 192, 11); +/// `[BLOCK_KEY0]` BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[]` 256bit FE key +pub const KEY0_FE_256BIT: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[]` 128bit FE key +pub const KEY0_FE_128BIT: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 128); +/// `[]` 128bit SB key +pub const KEY0_SB_128BIT: EfuseField = EfuseField::new(EfuseBlock::Block3, 128, 128); diff --git a/esp-hal/src/soc/esp32c2/efuse.rs b/esp-hal/src/soc/esp32c2/efuse/mod.rs similarity index 99% rename from esp-hal/src/soc/esp32c2/efuse.rs rename to esp-hal/src/soc/esp32c2/efuse/mod.rs index 925423b5781..cdf25cfa140 100644 --- a/esp-hal/src/soc/esp32c2/efuse.rs +++ b/esp-hal/src/soc/esp32c2/efuse/mod.rs @@ -33,9 +33,11 @@ //! ); //! ``` -pub use crate::soc::efuse_field::*; +pub use self::fields::*; use crate::{adc::Attenuation, peripherals::EFUSE}; +mod fields; + pub struct Efuse; impl Efuse { diff --git a/esp-hal/src/soc/esp32c3/efuse/fields.rs b/esp-hal/src/soc/esp32c3/efuse/fields.rs new file mode 100644 index 00000000000..5d749271b18 --- /dev/null +++ b/esp-hal/src/soc/esp32c3/efuse/fields.rs @@ -0,0 +1,380 @@ +//! eFuse fields for the ESP32-C3. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of DIS_ICACHE +pub const WR_DIS_DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_USB_JTAG +pub const WR_DIS_DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_ICACHE +pub const WR_DIS_DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_USB_DEVICE]` wr_dis of DIS_USB_SERIAL_JTAG +pub const WR_DIS_DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_FORCE_DOWNLOAD +pub const WR_DIS_DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_CAN]` wr_dis of DIS_TWAI +pub const WR_DIS_DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of JTAG_SEL_ENABLE +pub const WR_DIS_JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_PAD_JTAG +pub const WR_DIS_DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +pub const WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of WDT_DELAY_SEL +pub const WR_DIS_WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0 +pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1 +pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2 +pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3 +pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1); +/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4 +pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5 +pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +pub const WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 16, 1); +/// `[]` wr_dis of FLASH_TPUW +pub const WR_DIS_FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MODE +pub const WR_DIS_DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.DIS_LEGACY_SPI_BOOT]` wr_dis of DIS_DIRECT_BOOT +pub const WR_DIS_DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.UART_PRINT_CHANNEL]` wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +pub const WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.DIS_USB_DOWNLOAD_MODE]` wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +pub const WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of ENABLE_SECURITY_DOWNLOAD +pub const WR_DIS_ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of UART_PRINT_CONTROL +pub const WR_DIS_UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FORCE_SEND_RESUME +pub const WR_DIS_FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of ERR_RST_ENABLE +pub const WR_DIS_ERR_RST_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR +pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField = + EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR +pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of BLOCK1 +pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CLK +pub const WR_DIS_SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_Q +pub const WR_DIS_SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D +pub const WR_DIS_SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CS +pub const WR_DIS_SPI_PAD_CONFIG_CS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_HD +pub const WR_DIS_SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_WP +pub const WR_DIS_SPI_PAD_CONFIG_WP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_DQS +pub const WR_DIS_SPI_PAD_CONFIG_DQS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D4 +pub const WR_DIS_SPI_PAD_CONFIG_D4: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D5 +pub const WR_DIS_SPI_PAD_CONFIG_D5: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D6 +pub const WR_DIS_SPI_PAD_CONFIG_D6: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D7 +pub const WR_DIS_SPI_PAD_CONFIG_D7: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR_LO +pub const WR_DIS_WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of K_RTC_LDO +pub const WR_DIS_K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of K_DIG_LDO +pub const WR_DIS_K_DIG_LDO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of V_RTC_DBIAS20 +pub const WR_DIS_V_RTC_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of V_DIG_DBIAS20 +pub const WR_DIS_V_DIG_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DIG_DBIAS_HVT +pub const WR_DIS_DIG_DBIAS_HVT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of THRES_HVT +pub const WR_DIS_THRES_HVT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR_HI +pub const WR_DIS_WAFER_VERSION_MINOR_HI: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLOCK2 +pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OPTIONAL_UNIQUE_ID +pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of TEMP_CALIB +pub const WR_DIS_TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OCODE +pub const WR_DIS_OCODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN1 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN2 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN3 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN0 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN1 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN2 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN3 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA +pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); +/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 +pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1); +/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2 +pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1); +/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3 +pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1); +/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4 +pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5 +pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1); +/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2 +pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1); +/// `[]` wr_dis of USB_EXCHG_PINS +pub const WR_DIS_USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of VDD_SPI_AS_GPIO +pub const WR_DIS_VDD_SPI_AS_GPIO: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of SOFT_DIS_JTAG +pub const WR_DIS_SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 31, 1); +/// `[]` Disable reading from BlOCK4-10 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7); +/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0 +pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1 +pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2 +pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1); +/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3 +pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1); +/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4 +pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5 +pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2 +pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Set this bit to disable Icache +pub const DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1); +/// `[]` Set this bit to disable function of usb switch to jtag in module of usb +/// device +pub const DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1); +/// `[]` Set this bit to disable Icache in download mode (boot_mode`[3:0]` is 0; +/// 1; 2; 3; 6; 7) +pub const DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[DIS_USB_DEVICE]` USB-Serial-JTAG {0: "Enable"; 1: "Disable"} +pub const DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 43, 1); +/// `[]` Set this bit to disable the function that forces chip into download +/// mode +pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1); +/// `[DIS_CAN]` Set this bit to disable CAN function +pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` Set this bit to enable selection between usb_to_jtag and pad_to_jtag +/// through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are +/// equal to 0 +pub const JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Set these bits to disable JTAG in the soft way (odd number 1 means +/// disable ). JTAG can be enabled in HMAC module +pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 3); +/// `[]` Set this bit to disable JTAG in the hard way. JTAG is disabled +/// permanently +pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1); +/// `[]` Set this bit to disable flash encryption when in download boot modes +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 52, 1); +/// `[]` Set this bit to exchange USB D+ and D- pins +pub const USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); +/// `[]` Set this bit to vdd spi pin function as gpio +pub const VDD_SPI_AS_GPIO: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 1); +/// `[]` RTC watchdog timeout threshold; in unit of slow clock cycle {0: +/// "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disables +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3); +/// `[]` Revoke 1st secure boot key +pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1); +/// `[]` Revoke 2nd secure boot key +pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1); +/// `[]` Revoke 3rd secure boot key +pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1); +/// `[KEY0_PURPOSE]` Purpose of Key0 +pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4); +/// `[KEY1_PURPOSE]` Purpose of Key1 +pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4); +/// `[KEY2_PURPOSE]` Purpose of Key2 +pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4); +/// `[KEY3_PURPOSE]` Purpose of Key3 +pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4); +/// `[KEY4_PURPOSE]` Purpose of Key4 +pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4); +/// `[KEY5_PURPOSE]` Purpose of Key5 +pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4); +/// `[]` Set this bit to enable secure boot +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1); +/// `[]` Set this bit to enable revoking aggressive secure boot +pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1); +/// `[]` Configures flash waiting time after power-up; in unit of ms. If the +/// value is less than 15; the waiting time is the configurable value; +/// Otherwise; the waiting time is twice the configurable value +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4); +/// `[]` Set this bit to disable download mode (boot_mode`[3:0]` = 0; 1; 2; 3; +/// 6; 7) +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1); +/// `[DIS_LEGACY_SPI_BOOT]` Disable direct boot mode +pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1); +/// `[UART_PRINT_CHANNEL]` USB printing {0: "Enable"; 1: "Disable"} +pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1); +/// `[DIS_USB_DOWNLOAD_MODE]` Disable UART download mode through USB-Serial-JTAG +pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 132, 1); +/// `[]` Set this bit to enable secure UART download mode +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1); +/// `[]` Set the default UARTboot message output mode {0: "Enable"; 1: "Enable +/// when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: +/// "Disable"} +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2); +/// `[]` Set this bit to force ROM code to send a resume command during SPI boot +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 141, 1); +/// `[]` Secure version (used by ESP-IDF anti-rollback feature) +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 142, 16); +/// `[]` Use BLOCK0 to check error record registers {0: "without check"; 1: +/// "with check"} +pub const ERR_RST_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 159, 1); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 1); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[]` SPI PAD CLK +pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 6); +/// `[]` SPI PAD Q(D1) +pub const SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block1, 54, 6); +/// `[]` SPI PAD D(D0) +pub const SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block1, 60, 6); +/// `[]` SPI PAD CS +pub const SPI_PAD_CONFIG_CS: EfuseField = EfuseField::new(EfuseBlock::Block1, 66, 6); +/// `[]` SPI PAD HD(D3) +pub const SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block1, 72, 6); +/// `[]` SPI PAD WP(D2) +pub const SPI_PAD_CONFIG_WP: EfuseField = EfuseField::new(EfuseBlock::Block1, 78, 6); +/// `[]` SPI PAD DQS +pub const SPI_PAD_CONFIG_DQS: EfuseField = EfuseField::new(EfuseBlock::Block1, 84, 6); +/// `[]` SPI PAD D4 +pub const SPI_PAD_CONFIG_D4: EfuseField = EfuseField::new(EfuseBlock::Block1, 90, 6); +/// `[]` SPI PAD D5 +pub const SPI_PAD_CONFIG_D5: EfuseField = EfuseField::new(EfuseBlock::Block1, 96, 6); +/// `[]` SPI PAD D6 +pub const SPI_PAD_CONFIG_D6: EfuseField = EfuseField::new(EfuseBlock::Block1, 102, 6); +/// `[]` SPI PAD D7 +pub const SPI_PAD_CONFIG_D7: EfuseField = EfuseField::new(EfuseBlock::Block1, 108, 6); +/// `[]` WAFER_VERSION_MINOR least significant bits +pub const WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 3); +/// `[]` Package version +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 3); +/// `[]` BLK_VERSION_MINOR +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); +/// `[]` BLOCK1 K_RTC_LDO +pub const K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block1, 135, 7); +/// `[]` BLOCK1 K_DIG_LDO +pub const K_DIG_LDO: EfuseField = EfuseField::new(EfuseBlock::Block1, 142, 7); +/// `[]` BLOCK1 voltage of rtc dbias20 +pub const V_RTC_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block1, 149, 8); +/// `[]` BLOCK1 voltage of digital dbias20 +pub const V_DIG_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block1, 157, 8); +/// `[]` BLOCK1 digital dbias when hvt +pub const DIG_DBIAS_HVT: EfuseField = EfuseField::new(EfuseBlock::Block1, 165, 5); +/// `[]` BLOCK1 pvt threshold when hvt +pub const THRES_HVT: EfuseField = EfuseField::new(EfuseBlock::Block1, 170, 10); +/// `[]` WAFER_VERSION_MINOR most significant bit +pub const WAFER_VERSION_MINOR_HI: EfuseField = EfuseField::new(EfuseBlock::Block1, 183, 1); +/// `[]` WAFER_VERSION_MAJOR +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 184, 2); +/// `[]` Optional unique 128-bit ID +pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128); +/// `[]` BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With +/// calibration"} +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 128, 2); +/// `[]` Temperature calibration data +pub const TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 131, 9); +/// `[]` ADC OCode +pub const OCODE: EfuseField = EfuseField::new(EfuseBlock::Block2, 140, 8); +/// `[]` ADC1 init code at atten0 +pub const ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 148, 10); +/// `[]` ADC1 init code at atten1 +pub const ADC1_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 158, 10); +/// `[]` ADC1 init code at atten2 +pub const ADC1_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 168, 10); +/// `[]` ADC1 init code at atten3 +pub const ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 178, 10); +/// `[]` ADC1 calibration voltage at atten0 +pub const ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 188, 10); +/// `[]` ADC1 calibration voltage at atten1 +pub const ADC1_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 198, 10); +/// `[]` ADC1 calibration voltage at atten2 +pub const ADC1_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 208, 10); +/// `[]` ADC1 calibration voltage at atten3 +pub const ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 218, 10); +/// `[BLOCK_USR_DATA]` User data +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC address +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); +/// `[BLOCK_KEY0]` Key0 or user data +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); +/// `[BLOCK_KEY1]` Key1 or user data +pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256); +/// `[BLOCK_KEY2]` Key2 or user data +pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256); +/// `[BLOCK_KEY3]` Key3 or user data +pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256); +/// `[BLOCK_KEY4]` Key4 or user data +pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256); +/// `[BLOCK_KEY5]` Key5 or user data +pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256); +/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved) +pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256); diff --git a/esp-hal/src/soc/esp32c3/efuse.rs b/esp-hal/src/soc/esp32c3/efuse/mod.rs similarity index 99% rename from esp-hal/src/soc/esp32c3/efuse.rs rename to esp-hal/src/soc/esp32c3/efuse/mod.rs index 759c5be1857..8a6a1fabfc7 100644 --- a/esp-hal/src/soc/esp32c3/efuse.rs +++ b/esp-hal/src/soc/esp32c3/efuse/mod.rs @@ -33,9 +33,11 @@ //! ); //! ``` -pub use crate::soc::efuse_field::*; +pub use self::fields::*; use crate::{adc::Attenuation, peripherals::EFUSE}; +mod fields; + pub struct Efuse; impl Efuse { diff --git a/esp-hal/src/soc/esp32c6/efuse/fields.rs b/esp-hal/src/soc/esp32c6/efuse/fields.rs new file mode 100644 index 00000000000..79658ebf6e0 --- /dev/null +++ b/esp-hal/src/soc/esp32c6/efuse/fields.rs @@ -0,0 +1,384 @@ +//! eFuse fields for the ESP32-C6. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of CRYPT_DPA_ENABLE +pub const WR_DIS_CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 1, 1); +/// `[]` wr_dis of SWAP_UART_SDIO_EN +pub const WR_DIS_SWAP_UART_SDIO_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_ICACHE +pub const WR_DIS_DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_USB_JTAG +pub const WR_DIS_DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_ICACHE +pub const WR_DIS_DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_USB_SERIAL_JTAG +pub const WR_DIS_DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_FORCE_DOWNLOAD +pub const WR_DIS_DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_CAN]` wr_dis of DIS_TWAI +pub const WR_DIS_DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of JTAG_SEL_ENABLE +pub const WR_DIS_JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_PAD_JTAG +pub const WR_DIS_DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +pub const WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of WDT_DELAY_SEL +pub const WR_DIS_WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0 +pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1 +pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2 +pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3 +pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1); +/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4 +pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5 +pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[WR_DIS.DPA_SEC_LEVEL]` wr_dis of SEC_DPA_LEVEL +pub const WR_DIS_SEC_DPA_LEVEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 14, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +pub const WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 16, 1); +/// `[]` wr_dis of SPI_DOWNLOAD_MSPI_DIS +pub const WR_DIS_SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 17, 1); +/// `[]` wr_dis of FLASH_TPUW +pub const WR_DIS_FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MODE +pub const WR_DIS_DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DIRECT_BOOT +pub const WR_DIS_DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.DIS_USB_PRINT]` wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +pub const WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +pub const WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of ENABLE_SECURITY_DOWNLOAD +pub const WR_DIS_ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of UART_PRINT_CONTROL +pub const WR_DIS_UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FORCE_SEND_RESUME +pub const WR_DIS_FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +pub const WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR +pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField = + EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR +pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of BLOCK1 +pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of MAC_EXT +pub const WR_DIS_MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR +pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_CAP +pub const WR_DIS_FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_TEMP +pub const WR_DIS_FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_VENDOR +pub const WR_DIS_FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLOCK2 +pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OPTIONAL_UNIQUE_ID +pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of TEMP_CALIB +pub const WR_DIS_TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OCODE +pub const WR_DIS_OCODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN1 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN2 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN3 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN0 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN1 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN2 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN3 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA +pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); +/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 +pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1); +/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2 +pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1); +/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3 +pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1); +/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4 +pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5 +pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1); +/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2 +pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1); +/// `[]` wr_dis of USB_EXCHG_PINS +pub const WR_DIS_USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of VDD_SPI_AS_GPIO +pub const WR_DIS_VDD_SPI_AS_GPIO: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of SOFT_DIS_JTAG +pub const WR_DIS_SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 31, 1); +/// `[]` Disable reading from BlOCK4-10 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7); +/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0 +pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1 +pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2 +pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1); +/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3 +pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1); +/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4 +pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5 +pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2 +pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Represents whether pad of uart and sdio is swapped or not. 1: swapped. +/// 0: not swapped +pub const SWAP_UART_SDIO_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 39, 1); +/// `[]` Represents whether icache is disabled or enabled. 1: disabled. 0: +/// enabled +pub const DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1); +/// `[]` Represents whether the function of usb switch to jtag is disabled or +/// enabled. 1: disabled. 0: enabled +pub const DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1); +/// `[]` Represents whether icache is disabled or enabled in Download mode. 1: +/// disabled. 0: enabled +pub const DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[]` Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. +/// 0: enabled +pub const DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 43, 1); +/// `[]` Represents whether the function that forces chip into download mode is +/// disabled or enabled. 1: disabled. 0: enabled +pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1); +/// `[]` Represents whether SPI0 controller during boot_mode_download is +/// disabled or enabled. 1: disabled. 0: enabled +pub const SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1); +/// `[DIS_CAN]` Represents whether TWAI function is disabled or enabled. 1: +/// disabled. 0: enabled +pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` Represents whether the selection between usb_to_jtag and pad_to_jtag +/// through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG +/// are equal to 0 is enabled or disabled. 1: enabled. 0: disabled +pub const JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Represents whether JTAG is disabled in soft way. Odd number: disabled. +/// Even number: enabled +pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 3); +/// `[]` Represents whether JTAG is disabled in the hard way(permanently). 1: +/// disabled. 0: enabled +pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1); +/// `[]` Represents whether flash encrypt function is disabled or enabled(except +/// in SPI boot mode). 1: disabled. 0: enabled +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 52, 1); +/// `[]` Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: +/// not exchanged +pub const USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); +/// `[]` Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: +/// not functioned +pub const VDD_SPI_AS_GPIO: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 1); +/// `[]` Represents whether RTC watchdog timeout threshold is selected at +/// startup. 1: selected. 0: not selected +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disables +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3); +/// `[]` Revoke 1st secure boot key +pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1); +/// `[]` Revoke 2nd secure boot key +pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1); +/// `[]` Revoke 3rd secure boot key +pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1); +/// `[KEY0_PURPOSE]` Represents the purpose of Key0 +pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4); +/// `[KEY1_PURPOSE]` Represents the purpose of Key1 +pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4); +/// `[KEY2_PURPOSE]` Represents the purpose of Key2 +pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4); +/// `[KEY3_PURPOSE]` Represents the purpose of Key3 +pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4); +/// `[KEY4_PURPOSE]` Represents the purpose of Key4 +pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4); +/// `[KEY5_PURPOSE]` Represents the purpose of Key5 +pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4); +/// `[DPA_SEC_LEVEL]` Represents the spa secure level by configuring the clock +/// random divide mode +pub const SEC_DPA_LEVEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 112, 2); +/// `[]` Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled +pub const CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 114, 1); +/// `[]` Represents whether secure boot is enabled or disabled. 1: enabled. 0: +/// disabled +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1); +/// `[]` Represents whether revoking aggressive secure boot is enabled or +/// disabled. 1: enabled. 0: disabled +pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1); +/// `[]` Represents the flash waiting time after power-up; in unit of ms. When +/// the value less than 15; the waiting time is the programmed value. Otherwise; +/// the waiting time is 2 times the programmed value +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4); +/// `[]` Represents whether Download mode is disabled or enabled. 1: disabled. +/// 0: enabled +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1); +/// `[]` Represents whether direct boot mode is disabled or enabled. 1: +/// disabled. 0: enabled +pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1); +/// `[DIS_USB_PRINT]` Represents whether print from USB-Serial-JTAG is disabled +/// or enabled. 1: disabled. 0: enabled +pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1); +/// `[]` Represents whether the USB-Serial-JTAG download function is disabled or +/// enabled. 1: disabled. 0: enabled +pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 132, 1); +/// `[]` Represents whether security download is enabled or disabled. 1: +/// enabled. 0: disabled +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1); +/// `[]` Set the default UARTboot message output mode {0: "Enable"; 1: "Enable +/// when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: +/// "Disable"} +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2); +/// `[]` Represents whether ROM code is forced to send a resume command during +/// SPI boot. 1: forced. 0:not forced +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 141, 1); +/// `[]` Represents the version used by ESP-IDF anti-rollback feature +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 142, 16); +/// `[]` Represents whether FAST VERIFY ON WAKE is disabled or enabled when +/// Secure Boot is enabled. 1: disabled. 0: enabled +pub const SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 158, 1); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 1); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[]` Stores the extended bits of MAC address +pub const MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 16); +/// `[]` +pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 4); +/// `[]` +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 118, 2); +/// `[]` Package version +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); +/// `[]` BLK_VERSION_MINOR of BLOCK2 +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 123, 3); +/// `[]` BLK_VERSION_MAJOR of BLOCK2 +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 126, 2); +/// `[]` +pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 128, 3); +/// `[]` +pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 131, 2); +/// `[]` +pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 133, 3); +/// `[]` Optional unique 128-bit ID +pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128); +/// `[]` Temperature calibration data +pub const TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 128, 9); +/// `[]` ADC OCode +pub const OCODE: EfuseField = EfuseField::new(EfuseBlock::Block2, 137, 8); +/// `[]` ADC1 init code at atten0 +pub const ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 145, 10); +/// `[]` ADC1 init code at atten1 +pub const ADC1_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 155, 10); +/// `[]` ADC1 init code at atten2 +pub const ADC1_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 165, 10); +/// `[]` ADC1 init code at atten3 +pub const ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 175, 10); +/// `[]` ADC1 calibration voltage at atten0 +pub const ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 185, 10); +/// `[]` ADC1 calibration voltage at atten1 +pub const ADC1_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 195, 10); +/// `[]` ADC1 calibration voltage at atten2 +pub const ADC1_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 205, 10); +/// `[]` ADC1 calibration voltage at atten3 +pub const ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 215, 10); +/// `[]` ADC1 init code at atten0 ch0 +pub const ADC1_INIT_CODE_ATTEN0_CH0: EfuseField = EfuseField::new(EfuseBlock::Block2, 225, 4); +/// `[]` ADC1 init code at atten0 ch1 +pub const ADC1_INIT_CODE_ATTEN0_CH1: EfuseField = EfuseField::new(EfuseBlock::Block2, 229, 4); +/// `[]` ADC1 init code at atten0 ch2 +pub const ADC1_INIT_CODE_ATTEN0_CH2: EfuseField = EfuseField::new(EfuseBlock::Block2, 233, 4); +/// `[]` ADC1 init code at atten0 ch3 +pub const ADC1_INIT_CODE_ATTEN0_CH3: EfuseField = EfuseField::new(EfuseBlock::Block2, 237, 4); +/// `[]` ADC1 init code at atten0 ch4 +pub const ADC1_INIT_CODE_ATTEN0_CH4: EfuseField = EfuseField::new(EfuseBlock::Block2, 241, 4); +/// `[]` ADC1 init code at atten0 ch5 +pub const ADC1_INIT_CODE_ATTEN0_CH5: EfuseField = EfuseField::new(EfuseBlock::Block2, 245, 4); +/// `[]` ADC1 init code at atten0 ch6 +pub const ADC1_INIT_CODE_ATTEN0_CH6: EfuseField = EfuseField::new(EfuseBlock::Block2, 249, 4); +/// `[BLOCK_USR_DATA]` User data +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); +/// `[BLOCK_KEY0]` Key0 or user data +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); +/// `[BLOCK_KEY1]` Key1 or user data +pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256); +/// `[BLOCK_KEY2]` Key2 or user data +pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256); +/// `[BLOCK_KEY3]` Key3 or user data +pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256); +/// `[BLOCK_KEY4]` Key4 or user data +pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256); +/// `[BLOCK_KEY5]` Key5 or user data +pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256); +/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved) +pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256); diff --git a/esp-hal/src/soc/esp32c6/efuse.rs b/esp-hal/src/soc/esp32c6/efuse/mod.rs similarity index 99% rename from esp-hal/src/soc/esp32c6/efuse.rs rename to esp-hal/src/soc/esp32c6/efuse/mod.rs index 6ef039fda8c..b4246ce47ac 100644 --- a/esp-hal/src/soc/esp32c6/efuse.rs +++ b/esp-hal/src/soc/esp32c6/efuse/mod.rs @@ -33,9 +33,11 @@ //! ); //! ``` -pub use crate::soc::efuse_field::*; +pub use self::fields::*; use crate::{adc::Attenuation, peripherals::EFUSE}; +mod fields; + pub struct Efuse; impl Efuse { diff --git a/esp-hal/src/soc/esp32h2/efuse/fields.rs b/esp-hal/src/soc/esp32h2/efuse/fields.rs new file mode 100644 index 00000000000..b3a29b39142 --- /dev/null +++ b/esp-hal/src/soc/esp32h2/efuse/fields.rs @@ -0,0 +1,332 @@ +//! eFuse fields for the ESP32-H2. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of DIS_ICACHE +pub const WR_DIS_DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_USB_JTAG +pub const WR_DIS_DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of POWERGLITCH_EN +pub const WR_DIS_POWERGLITCH_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_FORCE_DOWNLOAD +pub const WR_DIS_DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of SPI_DOWNLOAD_MSPI_DIS +pub const WR_DIS_SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_CAN]` wr_dis of DIS_TWAI +pub const WR_DIS_DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of JTAG_SEL_ENABLE +pub const WR_DIS_JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_PAD_JTAG +pub const WR_DIS_DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +pub const WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of WDT_DELAY_SEL +pub const WR_DIS_WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0 +pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1 +pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2 +pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3 +pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1); +/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4 +pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5 +pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[]` wr_dis of SEC_DPA_LEVEL +pub const WR_DIS_SEC_DPA_LEVEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 14, 1); +/// `[]` wr_dis of CRYPT_DPA_ENABLE +pub const WR_DIS_CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 14, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +pub const WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 16, 1); +/// `[]` wr_dis of ECDSA_FORCE_USE_HARDWARE_K +pub const WR_DIS_ECDSA_FORCE_USE_HARDWARE_K: EfuseField = + EfuseField::new(EfuseBlock::Block0, 17, 1); +/// `[]` wr_dis of FLASH_TPUW +pub const WR_DIS_FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MODE +pub const WR_DIS_DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DIRECT_BOOT +pub const WR_DIS_DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.DIS_USB_PRINT]` wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +pub const WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +pub const WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of ENABLE_SECURITY_DOWNLOAD +pub const WR_DIS_ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of UART_PRINT_CONTROL +pub const WR_DIS_UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FORCE_SEND_RESUME +pub const WR_DIS_FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +pub const WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of HYS_EN_PAD0 +pub const WR_DIS_HYS_EN_PAD0: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of HYS_EN_PAD1 +pub const WR_DIS_HYS_EN_PAD1: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of BLOCK1 +pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of MAC_EXT +pub const WR_DIS_MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of RXIQ_VERSION +pub const WR_DIS_RXIQ_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of RXIQ_0 +pub const WR_DIS_RXIQ_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of RXIQ_1 +pub const WR_DIS_RXIQ_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR +pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR +pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField = + EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_CAP +pub const WR_DIS_FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_TEMP +pub const WR_DIS_FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_VENDOR +pub const WR_DIS_FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLOCK2 +pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OPTIONAL_UNIQUE_ID +pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR +pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA +pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); +/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 +pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1); +/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2 +pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1); +/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3 +pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1); +/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4 +pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5 +pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1); +/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2 +pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1); +/// `[]` wr_dis of USB_EXCHG_PINS +pub const WR_DIS_USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of VDD_SPI_AS_GPIO +pub const WR_DIS_VDD_SPI_AS_GPIO: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of SOFT_DIS_JTAG +pub const WR_DIS_SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 31, 1); +/// `[]` Disable reading from BlOCK4-10 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7); +/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0 +pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1 +pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2 +pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1); +/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3 +pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1); +/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4 +pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5 +pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2 +pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Represents whether icache is disabled or enabled. 1: disabled. 0: +/// enabled +pub const DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1); +/// `[]` Represents whether the function of usb switch to jtag is disabled or +/// enabled. 1: disabled. 0: enabled +pub const DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1); +/// `[]` Represents whether power glitch function is enabled. 1: enabled. 0: +/// disabled +pub const POWERGLITCH_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[]` Represents whether the function that forces chip into download mode is +/// disabled or enabled. 1: disabled. 0: enabled +pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1); +/// `[]` Represents whether SPI0 controller during boot_mode_download is +/// disabled or enabled. 1: disabled. 0: enabled +pub const SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1); +/// `[DIS_CAN]` Represents whether TWAI function is disabled or enabled. 1: +/// disabled. 0: enabled +pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` Set this bit to enable selection between usb_to_jtag and pad_to_jtag +/// through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG +/// are equal to 0 +pub const JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Represents whether JTAG is disabled in soft way. Odd number: disabled. +/// Even number: enabled +pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 3); +/// `[]` Represents whether JTAG is disabled in the hard way(permanently). 1: +/// disabled. 0: enabled +pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1); +/// `[]` Represents whether flash encrypt function is disabled or enabled(except +/// in SPI boot mode). 1: disabled. 0: enabled +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 52, 1); +/// `[]` Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: +/// not exchanged +pub const USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); +/// `[]` Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: +/// not functioned +pub const VDD_SPI_AS_GPIO: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 1); +/// `[]` Represents whether RTC watchdog timeout threshold is selected at +/// startup. 1: selected. 0: not selected +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disables +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3); +/// `[]` Revoke 1st secure boot key +pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1); +/// `[]` Revoke 2nd secure boot key +pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1); +/// `[]` Revoke 3rd secure boot key +pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1); +/// `[KEY0_PURPOSE]` Represents the purpose of Key0 +pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4); +/// `[KEY1_PURPOSE]` Represents the purpose of Key1 +pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4); +/// `[KEY2_PURPOSE]` Represents the purpose of Key2 +pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4); +/// `[KEY3_PURPOSE]` Represents the purpose of Key3 +pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4); +/// `[KEY4_PURPOSE]` Represents the purpose of Key4 +pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4); +/// `[KEY5_PURPOSE]` Represents the purpose of Key5 +pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4); +/// `[]` Represents the spa secure level by configuring the clock random divide +/// mode +pub const SEC_DPA_LEVEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 112, 2); +/// `[]` Represents whether hardware random number k is forced used in ESDCA. 1: +/// force used. 0: not force used +pub const ECDSA_FORCE_USE_HARDWARE_K: EfuseField = EfuseField::new(EfuseBlock::Block0, 114, 1); +/// `[]` Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled +pub const CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 115, 1); +/// `[]` Represents whether secure boot is enabled or disabled. 1: enabled. 0: +/// disabled +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1); +/// `[]` Represents whether revoking aggressive secure boot is enabled or +/// disabled. 1: enabled. 0: disabled +pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1); +/// `[]` Represents the flash waiting time after power-up; in unit of ms. When +/// the value less than 15; the waiting time is the programmed value. Otherwise; +/// the waiting time is 2 times the programmed value +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4); +/// `[]` Represents whether Download mode is disabled or enabled. 1: disabled. +/// 0: enabled +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1); +/// `[]` Represents whether direct boot mode is disabled or enabled. 1: +/// disabled. 0: enabled +pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1); +/// `[DIS_USB_PRINT]` Set this bit to disable USB-Serial-JTAG print during rom +/// boot +pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1); +/// `[]` Represents whether the USB-Serial-JTAG download function is disabled or +/// enabled. 1: disabled. 0: enabled +pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 132, 1); +/// `[]` Represents whether security download is enabled or disabled. 1: +/// enabled. 0: disabled +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1); +/// `[]` Set the default UARTboot message output mode {0: "Enable"; 1: "Enable +/// when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: +/// "Disable"} +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2); +/// `[]` Represents whether ROM code is forced to send a resume command during +/// SPI boot. 1: forced. 0:not forced +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 136, 1); +/// `[]` Represents the version used by ESP-IDF anti-rollback feature +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 137, 16); +/// `[]` Represents whether FAST VERIFY ON WAKE is disabled or enabled when +/// Secure Boot is enabled. 1: disabled. 0: enabled +pub const SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 153, 1); +/// `[]` Set bits to enable hysteresis function of PAD0~5 +pub const HYS_EN_PAD0: EfuseField = EfuseField::new(EfuseBlock::Block0, 154, 6); +/// `[]` Set bits to enable hysteresis function of PAD6~27 +pub const HYS_EN_PAD1: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 22); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[]` Stores the extended bits of MAC address +pub const MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 16); +/// `[]` RF Calibration data. RXIQ version +pub const RXIQ_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 64, 3); +/// `[]` RF Calibration data. RXIQ data 0 +pub const RXIQ_0: EfuseField = EfuseField::new(EfuseBlock::Block1, 67, 7); +/// `[]` RF Calibration data. RXIQ data 1 +pub const RXIQ_1: EfuseField = EfuseField::new(EfuseBlock::Block1, 74, 7); +/// `[]` +pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 3); +/// `[]` +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 2); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 119, 1); +/// `[]` +pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); +/// `[]` +pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 123, 2); +/// `[]` +pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 125, 3); +/// `[]` Package version +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 128, 3); +/// `[]` Optional unique 128-bit ID +pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128); +/// `[]` BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 130, 3); +/// `[]` BLK_VERSION_MAJOR of BLOCK2 +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 133, 2); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 135, 1); +/// `[BLOCK_USR_DATA]` User data +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); +/// `[BLOCK_KEY0]` Key0 or user data +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); +/// `[BLOCK_KEY1]` Key1 or user data +pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256); +/// `[BLOCK_KEY2]` Key2 or user data +pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256); +/// `[BLOCK_KEY3]` Key3 or user data +pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256); +/// `[BLOCK_KEY4]` Key4 or user data +pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256); +/// `[BLOCK_KEY5]` Key5 or user data +pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256); +/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved) +pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256); diff --git a/esp-hal/src/soc/esp32h2/efuse.rs b/esp-hal/src/soc/esp32h2/efuse/mod.rs similarity index 98% rename from esp-hal/src/soc/esp32h2/efuse.rs rename to esp-hal/src/soc/esp32h2/efuse/mod.rs index da13b4b6c25..5c31e4eceb2 100644 --- a/esp-hal/src/soc/esp32h2/efuse.rs +++ b/esp-hal/src/soc/esp32h2/efuse/mod.rs @@ -33,8 +33,10 @@ //! ); //! ``` +pub use self::fields::*; use crate::peripherals::EFUSE; -pub use crate::soc::efuse_field::*; + +mod fields; pub struct Efuse; diff --git a/esp-hal/src/soc/esp32p4/efuse/fields.rs b/esp-hal/src/soc/esp32p4/efuse/fields.rs new file mode 100644 index 00000000000..07d3e8a94b4 --- /dev/null +++ b/esp-hal/src/soc/esp32p4/efuse/fields.rs @@ -0,0 +1,259 @@ +//! eFuse fields for the ESP32-P4. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0 +pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1 +pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2 +pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3 +pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1); +/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4 +pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5 +pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of BLOCK1 +pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of MAC_EXT +pub const WR_DIS_MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.SYS_DATA_PART1]` wr_dis of BLOCK_SYS_DATA1 +pub const WR_DIS_BLOCK_SYS_DATA1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA +pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); +/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 +pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1); +/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2 +pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1); +/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3 +pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1); +/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4 +pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5 +pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1); +/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2 +pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1); +/// `[]` Disable reading from BlOCK4-10 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7); +/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0 +pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1 +pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2 +pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1); +/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3 +pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1); +/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4 +pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5 +pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2 +pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Enable usb device exchange pins of D+ and D- +pub const USB_DEVICE_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 39, 1); +/// `[]` Enable usb otg11 exchange pins of D+ and D- +pub const USB_OTG11_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1); +/// `[]` Represents whether the function of usb switch to jtag is disabled or +/// enabled. 1: disabled. 0: enabled +pub const DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1); +/// `[]` Represents whether power glitch function is enabled. 1: enabled. 0: +/// disabled +pub const POWERGLITCH_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[]` Represents whether the function that forces chip into download mode is +/// disabled or enabled. 1: disabled. 0: enabled +pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1); +/// `[]` Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix +/// during boot_mode_download +pub const SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1); +/// `[]` Represents whether TWAI function is disabled or enabled. 1: disabled. +/// 0: enabled +pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` Represents whether the selection between usb_to_jtag and pad_to_jtag +/// through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG +/// are equal to 0 is enabled or disabled. 1: enabled. 0: disabled +pub const JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Represents whether JTAG is disabled in soft way. Odd number: disabled. +/// Even number: enabled +pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 3); +/// `[]` Represents whether JTAG is disabled in the hard way(permanently). 1: +/// disabled. 0: enabled +pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1); +/// `[]` Represents whether flash encrypt function is disabled or enabled(except +/// in SPI boot mode). 1: disabled. 0: enabled +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 52, 1); +/// `[]` TBD +pub const USB_PHY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); +/// `[]` Set this bit to control validation of HUK generate mode. Odd of 1 is +/// invalid; even of 1 is valid +pub const KM_HUK_GEN_STATE_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 6); +/// `[]` Set this bit to control validation of HUK generate mode. Odd of 1 is +/// invalid; even of 1 is valid +pub const KM_HUK_GEN_STATE_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block0, 64, 3); +/// `[]` Set bits to control key manager random number switch cycle. 0: control +/// by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles +pub const KM_RND_SWITCH_CYCLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 67, 2); +/// `[]` Set each bit to control whether corresponding key can only be deployed +/// once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds +pub const KM_DEPLOY_ONLY_ONCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 69, 4); +/// `[]` Set each bit to control whether corresponding key must come from key +/// manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: +/// ds +pub const FORCE_USE_KEY_MANAGER_KEY: EfuseField = EfuseField::new(EfuseBlock::Block0, 73, 4); +/// `[]` Set this bit to disable software written init key; and force use +/// efuse_init_key +pub const FORCE_DISABLE_SW_INIT_KEY: EfuseField = EfuseField::new(EfuseBlock::Block0, 77, 1); +/// `[]` Set this bit to configure flash encryption use xts-128 key; else use +/// xts-256 key +pub const XTS_KEY_LENGTH_256: EfuseField = EfuseField::new(EfuseBlock::Block0, 78, 1); +/// `[]` Represents whether RTC watchdog timeout threshold is selected at +/// startup. 1: selected. 0: not selected +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disables +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3); +/// `[]` Revoke 1st secure boot key +pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1); +/// `[]` Revoke 2nd secure boot key +pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1); +/// `[]` Revoke 3rd secure boot key +pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1); +/// `[KEY0_PURPOSE]` Represents the purpose of Key0 +pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4); +/// `[KEY1_PURPOSE]` Represents the purpose of Key1 +pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4); +/// `[KEY2_PURPOSE]` Represents the purpose of Key2 +pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4); +/// `[KEY3_PURPOSE]` Represents the purpose of Key3 +pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4); +/// `[KEY4_PURPOSE]` Represents the purpose of Key4 +pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4); +/// `[KEY5_PURPOSE]` Represents the purpose of Key5 +pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4); +/// `[]` Represents the spa secure level by configuring the clock random divide +/// mode +pub const SEC_DPA_LEVEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 112, 2); +/// `[]` Represents whether hardware random number k is forced used in ESDCA. 1: +/// force used. 0: not force used +pub const ECDSA_ENABLE_SOFT_K: EfuseField = EfuseField::new(EfuseBlock::Block0, 114, 1); +/// `[]` Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled +pub const CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 115, 1); +/// `[]` Represents whether secure boot is enabled or disabled. 1: enabled. 0: +/// disabled +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1); +/// `[]` Represents whether revoking aggressive secure boot is enabled or +/// disabled. 1: enabled. 0: disabled +pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1); +/// `[]` The type of interfaced flash. 0: four data lines; 1: eight data lines +pub const FLASH_TYPE: EfuseField = EfuseField::new(EfuseBlock::Block0, 119, 1); +/// `[]` Set flash page size +pub const FLASH_PAGE_SIZE: EfuseField = EfuseField::new(EfuseBlock::Block0, 120, 2); +/// `[]` Set this bit to enable ecc for flash boot +pub const FLASH_ECC_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 122, 1); +/// `[]` Set this bit to disable download via USB-OTG +pub const DIS_USB_OTG_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 123, 1); +/// `[]` Represents the flash waiting time after power-up; in unit of ms. When +/// the value less than 15; the waiting time is the programmed value. Otherwise; +/// the waiting time is 2 times the programmed value +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4); +/// `[]` Represents whether Download mode is disabled or enabled. 1: disabled. +/// 0: enabled +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1); +/// `[]` Represents whether direct boot mode is disabled or enabled. 1: +/// disabled. 0: enabled +pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1); +/// `[]` Represents whether print from USB-Serial-JTAG is disabled or enabled. +/// 1: disabled. 0: enabled +pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1); +/// `[]` TBD +pub const LOCK_KM_KEY: EfuseField = EfuseField::new(EfuseBlock::Block0, 131, 1); +/// `[]` Represents whether the USB-Serial-JTAG download function is disabled or +/// enabled. 1: disabled. 0: enabled +pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 132, 1); +/// `[]` Represents whether security download is enabled or disabled. 1: +/// enabled. 0: disabled +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1); +/// `[]` Represents the type of UART printing. 00: force enable printing. 01: +/// enable printing when GPIO8 is reset at low level. 10: enable printing when +/// GPIO8 is reset at high level. 11: force disable printing +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2); +/// `[]` Represents whether ROM code is forced to send a resume command during +/// SPI boot. 1: forced. 0:not forced +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 136, 1); +/// `[]` Represents the version used by ESP-IDF anti-rollback feature +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 137, 16); +/// `[]` Represents whether FAST VERIFY ON WAKE is disabled or enabled when +/// Secure Boot is enabled. 1: disabled. 0: enabled +pub const SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 153, 1); +/// `[]` Represents whether the hysteresis function of corresponding PAD is +/// enabled. 1: enabled. 0:disabled +pub const HYS_EN_PAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 154, 1); +/// `[]` Set the dcdc voltage default +pub const DCDC_VSET: EfuseField = EfuseField::new(EfuseBlock::Block0, 155, 5); +/// `[]` TBD +pub const PXA0_TIEH_SEL_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 2); +/// `[]` TBD +pub const PXA0_TIEH_SEL_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 162, 2); +/// `[]` TBD +pub const PXA0_TIEH_SEL_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 164, 2); +/// `[]` TBD +pub const PXA0_TIEH_SEL_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 166, 2); +/// `[]` TBD +pub const KM_DISABLE_DEPLOY_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 168, 4); +/// `[]` HP system power source select. 0:LDO. 1: DCDC +pub const HP_PWR_SRC_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 178, 1); +/// `[]` Select dcdc vset use efuse_dcdc_vset +pub const DCDC_VSET_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 179, 1); +/// `[]` Set this bit to disable watch dog +pub const DIS_WDT: EfuseField = EfuseField::new(EfuseBlock::Block0, 180, 1); +/// `[]` Set this bit to disable super-watchdog +pub const DIS_SWD: EfuseField = EfuseField::new(EfuseBlock::Block0, 181, 1); +/// `[MAC_FACTORY]` MAC address +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[]` Stores the extended bits of MAC address `[0]` +pub const MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 16); +/// `[SYS_DATA_PART1]` System data part 1 +pub const BLOCK_SYS_DATA1: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 256); +/// `[BLOCK_USR_DATA]` User data +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC (TODO +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); +/// `[BLOCK_KEY0]` Key0 or user data +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); +/// `[BLOCK_KEY1]` Key1 or user data +pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256); +/// `[BLOCK_KEY2]` Key2 or user data +pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256); +/// `[BLOCK_KEY3]` Key3 or user data +pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256); +/// `[BLOCK_KEY4]` Key4 or user data +pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256); +/// `[BLOCK_KEY5]` Key5 or user data +pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256); +/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved) +pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256); diff --git a/esp-hal/src/soc/esp32p4/efuse.rs b/esp-hal/src/soc/esp32p4/efuse/mod.rs similarity index 97% rename from esp-hal/src/soc/esp32p4/efuse.rs rename to esp-hal/src/soc/esp32p4/efuse/mod.rs index 85e95e3451b..315ef157e2f 100644 --- a/esp-hal/src/soc/esp32p4/efuse.rs +++ b/esp-hal/src/soc/esp32p4/efuse/mod.rs @@ -1,7 +1,9 @@ //! # Reading of eFuses (ESP32-P4) +pub use self::fields::*; use crate::peripherals::EFUSE; -pub use crate::soc::efuse_field::*; + +mod fields; pub struct Efuse; diff --git a/esp-hal/src/soc/esp32s2/efuse/fields.rs b/esp-hal/src/soc/esp32s2/efuse/fields.rs new file mode 100644 index 00000000000..e9657663330 --- /dev/null +++ b/esp-hal/src/soc/esp32s2/efuse/fields.rs @@ -0,0 +1,413 @@ +//! eFuse fields for the ESP32-S2. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of DIS_ICACHE +pub const WR_DIS_DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DCACHE +pub const WR_DIS_DIS_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_ICACHE +pub const WR_DIS_DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_DCACHE +pub const WR_DIS_DIS_DOWNLOAD_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_FORCE_DOWNLOAD +pub const WR_DIS_DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_USB +pub const WR_DIS_DIS_USB: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_CAN]` wr_dis of DIS_TWAI +pub const WR_DIS_DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_BOOT_REMAP +pub const WR_DIS_DIS_BOOT_REMAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of SOFT_DIS_JTAG +pub const WR_DIS_SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of HARD_DIS_JTAG +pub const WR_DIS_HARD_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +pub const WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of VDD_SPI_XPD +pub const WR_DIS_VDD_SPI_XPD: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of VDD_SPI_TIEH +pub const WR_DIS_VDD_SPI_TIEH: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of VDD_SPI_FORCE +pub const WR_DIS_VDD_SPI_FORCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of WDT_DELAY_SEL +pub const WR_DIS_WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0 +pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1 +pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2 +pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3 +pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1); +/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4 +pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5 +pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +pub const WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 16, 1); +/// `[]` wr_dis of FLASH_TPUW +pub const WR_DIS_FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MODE +pub const WR_DIS_DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_LEGACY_SPI_BOOT +pub const WR_DIS_DIS_LEGACY_SPI_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of UART_PRINT_CHANNEL +pub const WR_DIS_UART_PRINT_CHANNEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_USB_DOWNLOAD_MODE +pub const WR_DIS_DIS_USB_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of ENABLE_SECURITY_DOWNLOAD +pub const WR_DIS_ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of UART_PRINT_CONTROL +pub const WR_DIS_UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of PIN_POWER_SELECTION +pub const WR_DIS_PIN_POWER_SELECTION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FLASH_TYPE +pub const WR_DIS_FLASH_TYPE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FORCE_SEND_RESUME +pub const WR_DIS_FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of BLOCK1 +pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CLK +pub const WR_DIS_SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_Q +pub const WR_DIS_SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D +pub const WR_DIS_SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CS +pub const WR_DIS_SPI_PAD_CONFIG_CS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_HD +pub const WR_DIS_SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_WP +pub const WR_DIS_SPI_PAD_CONFIG_WP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_DQS +pub const WR_DIS_SPI_PAD_CONFIG_DQS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D4 +pub const WR_DIS_SPI_PAD_CONFIG_D4: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D5 +pub const WR_DIS_SPI_PAD_CONFIG_D5: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D6 +pub const WR_DIS_SPI_PAD_CONFIG_D6: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D7 +pub const WR_DIS_SPI_PAD_CONFIG_D7: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR_HI +pub const WR_DIS_WAFER_VERSION_MINOR_HI: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_VERSION +pub const WR_DIS_FLASH_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_VERSION +pub const WR_DIS_PSRAM_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR_LO +pub const WR_DIS_WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLOCK2 +pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OPTIONAL_UNIQUE_ID +pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC_CALIB +pub const WR_DIS_ADC_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of TEMP_CALIB +pub const WR_DIS_TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A10H +pub const WR_DIS_RTCCALIB_V1IDX_A10H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A11H +pub const WR_DIS_RTCCALIB_V1IDX_A11H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A12H +pub const WR_DIS_RTCCALIB_V1IDX_A12H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A13H +pub const WR_DIS_RTCCALIB_V1IDX_A13H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A20H +pub const WR_DIS_RTCCALIB_V1IDX_A20H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A21H +pub const WR_DIS_RTCCALIB_V1IDX_A21H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A22H +pub const WR_DIS_RTCCALIB_V1IDX_A22H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A23H +pub const WR_DIS_RTCCALIB_V1IDX_A23H: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A10L +pub const WR_DIS_RTCCALIB_V1IDX_A10L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A11L +pub const WR_DIS_RTCCALIB_V1IDX_A11L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A12L +pub const WR_DIS_RTCCALIB_V1IDX_A12L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A13L +pub const WR_DIS_RTCCALIB_V1IDX_A13L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A20L +pub const WR_DIS_RTCCALIB_V1IDX_A20L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A21L +pub const WR_DIS_RTCCALIB_V1IDX_A21L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A22L +pub const WR_DIS_RTCCALIB_V1IDX_A22L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of RTCCALIB_V1IDX_A23L +pub const WR_DIS_RTCCALIB_V1IDX_A23L: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA +pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); +/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 +pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1); +/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2 +pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1); +/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3 +pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1); +/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4 +pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5 +pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1); +/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2 +pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1); +/// `[]` wr_dis of USB_EXCHG_PINS +pub const WR_DIS_USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[WR_DIS.EXT_PHY_ENABLE]` wr_dis of USB_EXT_PHY_ENABLE +pub const WR_DIS_USB_EXT_PHY_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of USB_FORCE_NOPERSIST +pub const WR_DIS_USB_FORCE_NOPERSIST: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of BLOCK0_VERSION +pub const WR_DIS_BLOCK0_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` Disable reading from BlOCK4-10 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7); +/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0 +pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1 +pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2 +pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1); +/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3 +pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1); +/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4 +pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5 +pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2 +pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Set this bit to disable Icache +pub const DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1); +/// `[]` Set this bit to disable Dcache +pub const DIS_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1); +/// `[]` Disables Icache when SoC is in Download mode +pub const DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[]` Disables Dcache when SoC is in Download mode +pub const DIS_DOWNLOAD_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 43, 1); +/// `[]` Set this bit to disable the function that forces chip into download +/// mode +pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1); +/// `[]` Set this bit to disable USB OTG function +pub const DIS_USB: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1); +/// `[DIS_CAN]` Set this bit to disable the TWAI Controller function +pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` Disables capability to Remap RAM to ROM address space +pub const DIS_BOOT_REMAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Software disables JTAG. When software disabled; JTAG can be activated +/// temporarily by HMAC peripheral +pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 49, 1); +/// `[]` Hardware disables JTAG permanently +pub const HARD_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 50, 1); +/// `[]` Disables flash encryption when in download boot modes +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1); +/// `[]` Set this bit to exchange USB D+ and D- pins +pub const USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 56, 1); +/// `[EXT_PHY_ENABLE]` Set this bit to enable external USB PHY +pub const USB_EXT_PHY_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); +/// `[]` If set; forces USB BVALID to 1 +pub const USB_FORCE_NOPERSIST: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 1); +/// `[]` BLOCK0 efuse version +pub const BLOCK0_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 59, 2); +/// `[]` If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator +/// is powered on +pub const VDD_SPI_XPD: EfuseField = EfuseField::new(EfuseBlock::Block0, 68, 1); +/// `[]` If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects +/// to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} +pub const VDD_SPI_TIEH: EfuseField = EfuseField::new(EfuseBlock::Block0, 69, 1); +/// `[]` Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure +/// VDD_SPI LDO +pub const VDD_SPI_FORCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 70, 1); +/// `[]` RTC watchdog timeout threshold; in unit of slow clock cycle {0: +/// "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disabled +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3); +/// `[]` Revoke 1st secure boot key +pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1); +/// `[]` Revoke 2nd secure boot key +pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1); +/// `[]` Revoke 3rd secure boot key +pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1); +/// `[KEY0_PURPOSE]` Purpose of KEY0 +pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4); +/// `[KEY1_PURPOSE]` Purpose of KEY1 +pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4); +/// `[KEY2_PURPOSE]` Purpose of KEY2 +pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4); +/// `[KEY3_PURPOSE]` Purpose of KEY3 +pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4); +/// `[KEY4_PURPOSE]` Purpose of KEY4 +pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4); +/// `[KEY5_PURPOSE]` Purpose of KEY5 +pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4); +/// `[]` Set this bit to enable secure boot +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1); +/// `[]` Set this bit to enable aggressive secure boot key revocation mode +pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1); +/// `[]` Configures flash startup delay after SoC power-up; in unit of (ms/2). +/// When the value is 15; delay is 7.5 ms +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4); +/// `[]` Set this bit to disable all download boot modes +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1); +/// `[]` Set this bit to disable Legacy SPI boot mode +pub const DIS_LEGACY_SPI_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1); +/// `[]` Selects the default UART for printing boot messages {0: "UART0"; 1: +/// "UART1"} +pub const UART_PRINT_CHANNEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1); +/// `[]` Set this bit to disable use of USB OTG in UART download boot mode +pub const DIS_USB_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 132, 1); +/// `[]` Set this bit to enable secure UART download mode (read/write flash +/// only) +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1); +/// `[]` Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2); +/// `[]` Set default power supply for GPIO33-GPIO37; set when SPI flash is +/// initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} +pub const PIN_POWER_SELECTION: EfuseField = EfuseField::new(EfuseBlock::Block0, 136, 1); +/// `[]` SPI flash type {0: "4 data lines"; 1: "8 data lines"} +pub const FLASH_TYPE: EfuseField = EfuseField::new(EfuseBlock::Block0, 137, 1); +/// `[]` If set; forces ROM code to send an SPI flash resume command during SPI +/// boot +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 138, 1); +/// `[]` Secure version (used by ESP-IDF anti-rollback feature) +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 139, 16); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 1); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[]` SPI_PAD_configure CLK +pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 6); +/// `[]` SPI_PAD_configure Q(D1) +pub const SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block1, 54, 6); +/// `[]` SPI_PAD_configure D(D0) +pub const SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block1, 60, 6); +/// `[]` SPI_PAD_configure CS +pub const SPI_PAD_CONFIG_CS: EfuseField = EfuseField::new(EfuseBlock::Block1, 66, 6); +/// `[]` SPI_PAD_configure HD(D3) +pub const SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block1, 72, 6); +/// `[]` SPI_PAD_configure WP(D2) +pub const SPI_PAD_CONFIG_WP: EfuseField = EfuseField::new(EfuseBlock::Block1, 78, 6); +/// `[]` SPI_PAD_configure DQS +pub const SPI_PAD_CONFIG_DQS: EfuseField = EfuseField::new(EfuseBlock::Block1, 84, 6); +/// `[]` SPI_PAD_configure D4 +pub const SPI_PAD_CONFIG_D4: EfuseField = EfuseField::new(EfuseBlock::Block1, 90, 6); +/// `[]` SPI_PAD_configure D5 +pub const SPI_PAD_CONFIG_D5: EfuseField = EfuseField::new(EfuseBlock::Block1, 96, 6); +/// `[]` SPI_PAD_configure D6 +pub const SPI_PAD_CONFIG_D6: EfuseField = EfuseField::new(EfuseBlock::Block1, 102, 6); +/// `[]` SPI_PAD_configure D7 +pub const SPI_PAD_CONFIG_D7: EfuseField = EfuseField::new(EfuseBlock::Block1, 108, 6); +/// `[]` WAFER_VERSION_MAJOR +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 2); +/// `[]` WAFER_VERSION_MINOR most significant bit +pub const WAFER_VERSION_MINOR_HI: EfuseField = EfuseField::new(EfuseBlock::Block1, 116, 1); +/// `[]` Flash version +pub const FLASH_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 4); +/// `[]` BLK_VERSION_MAJOR +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 121, 2); +/// `[]` PSRAM version +pub const PSRAM_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 124, 4); +/// `[]` Package version +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 128, 4); +/// `[]` WAFER_VERSION_MINOR least significant bits +pub const WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block1, 132, 3); +/// `[]` Optional unique 128-bit ID +pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128); +/// `[]` 4 bit of ADC calibration +pub const ADC_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 128, 4); +/// `[]` BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC +/// calib V2"} +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 132, 3); +/// `[]` Temperature calibration data +pub const TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 135, 9); +/// `[]` +pub const RTCCALIB_V1IDX_A10H: EfuseField = EfuseField::new(EfuseBlock::Block2, 144, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A11H: EfuseField = EfuseField::new(EfuseBlock::Block2, 152, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A12H: EfuseField = EfuseField::new(EfuseBlock::Block2, 160, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A13H: EfuseField = EfuseField::new(EfuseBlock::Block2, 168, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A20H: EfuseField = EfuseField::new(EfuseBlock::Block2, 176, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A21H: EfuseField = EfuseField::new(EfuseBlock::Block2, 184, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A22H: EfuseField = EfuseField::new(EfuseBlock::Block2, 192, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A23H: EfuseField = EfuseField::new(EfuseBlock::Block2, 200, 8); +/// `[]` +pub const RTCCALIB_V1IDX_A10L: EfuseField = EfuseField::new(EfuseBlock::Block2, 208, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A11L: EfuseField = EfuseField::new(EfuseBlock::Block2, 214, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A12L: EfuseField = EfuseField::new(EfuseBlock::Block2, 220, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A13L: EfuseField = EfuseField::new(EfuseBlock::Block2, 226, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A20L: EfuseField = EfuseField::new(EfuseBlock::Block2, 232, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A21L: EfuseField = EfuseField::new(EfuseBlock::Block2, 238, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A22L: EfuseField = EfuseField::new(EfuseBlock::Block2, 244, 6); +/// `[]` +pub const RTCCALIB_V1IDX_A23L: EfuseField = EfuseField::new(EfuseBlock::Block2, 250, 6); +/// `[BLOCK_USR_DATA]` User data +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); +/// `[BLOCK_KEY0]` Key0 or user data +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); +/// `[BLOCK_KEY1]` Key1 or user data +pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256); +/// `[BLOCK_KEY2]` Key2 or user data +pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256); +/// `[BLOCK_KEY3]` Key3 or user data +pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256); +/// `[BLOCK_KEY4]` Key4 or user data +pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256); +/// `[BLOCK_KEY5]` Key5 or user data +pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256); +/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved) +pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256); diff --git a/esp-hal/src/soc/esp32s2/efuse.rs b/esp-hal/src/soc/esp32s2/efuse/mod.rs similarity index 98% rename from esp-hal/src/soc/esp32s2/efuse.rs rename to esp-hal/src/soc/esp32s2/efuse/mod.rs index 7a746a4285d..55b3ec6c3e1 100644 --- a/esp-hal/src/soc/esp32s2/efuse.rs +++ b/esp-hal/src/soc/esp32s2/efuse/mod.rs @@ -33,8 +33,10 @@ //! ); //! ``` +pub use self::fields::*; use crate::peripherals::EFUSE; -pub use crate::soc::efuse_field::*; + +mod fields; pub struct Efuse; diff --git a/esp-hal/src/soc/esp32s3/efuse/fields.rs b/esp-hal/src/soc/esp32s3/efuse/fields.rs new file mode 100644 index 00000000000..9f9b5452a94 --- /dev/null +++ b/esp-hal/src/soc/esp32s3/efuse/fields.rs @@ -0,0 +1,464 @@ +//! eFuse fields for the ESP32-S3. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; + +/// `[]` Disable programming of individual eFuses +pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32); +/// `[]` wr_dis of RD_DIS +pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1); +/// `[]` wr_dis of DIS_ICACHE +pub const WR_DIS_DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DCACHE +pub const WR_DIS_DIS_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_ICACHE +pub const WR_DIS_DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_DCACHE +pub const WR_DIS_DIS_DOWNLOAD_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_FORCE_DOWNLOAD +pub const WR_DIS_DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_USB]` wr_dis of DIS_USB_OTG +pub const WR_DIS_DIS_USB_OTG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_CAN]` wr_dis of DIS_TWAI +pub const WR_DIS_DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_APP_CPU +pub const WR_DIS_DIS_APP_CPU: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.HARD_DIS_JTAG]` wr_dis of DIS_PAD_JTAG +pub const WR_DIS_DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +pub const WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of DIS_USB_JTAG +pub const WR_DIS_DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[WR_DIS.DIS_USB_DEVICE]` wr_dis of DIS_USB_SERIAL_JTAG +pub const WR_DIS_DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of STRAP_JTAG_SEL +pub const WR_DIS_STRAP_JTAG_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of USB_PHY_SEL +pub const WR_DIS_USB_PHY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 2, 1); +/// `[]` wr_dis of VDD_SPI_XPD +pub const WR_DIS_VDD_SPI_XPD: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of VDD_SPI_TIEH +pub const WR_DIS_VDD_SPI_TIEH: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of VDD_SPI_FORCE +pub const WR_DIS_VDD_SPI_FORCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of WDT_DELAY_SEL +pub const WR_DIS_WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 3, 1); +/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT +pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1); +/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2 +pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1); +/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0 +pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1); +/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1 +pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1); +/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2 +pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1); +/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3 +pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1); +/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4 +pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1); +/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5 +pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1); +/// `[]` wr_dis of SECURE_BOOT_EN +pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1); +/// `[]` wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +pub const WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 16, 1); +/// `[]` wr_dis of FLASH_TPUW +pub const WR_DIS_FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_DOWNLOAD_MODE +pub const WR_DIS_DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.DIS_LEGACY_SPI_BOOT]` wr_dis of DIS_DIRECT_BOOT +pub const WR_DIS_DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.UART_PRINT_CHANNEL]` wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +pub const WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FLASH_ECC_MODE +pub const WR_DIS_FLASH_ECC_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[WR_DIS.DIS_USB_DOWNLOAD_MODE]` wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +pub const WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of ENABLE_SECURITY_DOWNLOAD +pub const WR_DIS_ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of UART_PRINT_CONTROL +pub const WR_DIS_UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of PIN_POWER_SELECTION +pub const WR_DIS_PIN_POWER_SELECTION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FLASH_TYPE +pub const WR_DIS_FLASH_TYPE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FLASH_PAGE_SIZE +pub const WR_DIS_FLASH_PAGE_SIZE: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FLASH_ECC_EN +pub const WR_DIS_FLASH_ECC_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of FORCE_SEND_RESUME +pub const WR_DIS_FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of SECURE_VERSION +pub const WR_DIS_SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 18, 1); +/// `[]` wr_dis of DIS_USB_OTG_DOWNLOAD_MODE +pub const WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR +pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField = + EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR +pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 19, 1); +/// `[]` wr_dis of BLOCK1 +pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC +pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CLK +pub const WR_DIS_SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_Q +pub const WR_DIS_SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D +pub const WR_DIS_SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_CS +pub const WR_DIS_SPI_PAD_CONFIG_CS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_HD +pub const WR_DIS_SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_WP +pub const WR_DIS_SPI_PAD_CONFIG_WP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_DQS +pub const WR_DIS_SPI_PAD_CONFIG_DQS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D4 +pub const WR_DIS_SPI_PAD_CONFIG_D4: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D5 +pub const WR_DIS_SPI_PAD_CONFIG_D5: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D6 +pub const WR_DIS_SPI_PAD_CONFIG_D6: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of SPI_PAD_CONFIG_D7 +pub const WR_DIS_SPI_PAD_CONFIG_D7: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR_LO +pub const WR_DIS_WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of K_RTC_LDO +pub const WR_DIS_K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of K_DIG_LDO +pub const WR_DIS_K_DIG_LDO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of V_RTC_DBIAS20 +pub const WR_DIS_V_RTC_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of V_DIG_DBIAS20 +pub const WR_DIS_V_DIG_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DIG_DBIAS_HVT +pub const WR_DIS_DIG_DBIAS_HVT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR_HI +pub const WR_DIS_WAFER_VERSION_MINOR_HI: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of ADC2_CAL_VOL_ATTEN3 +pub const WR_DIS_ADC2_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLOCK2 +pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OPTIONAL_UNIQUE_ID +pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of TEMP_CALIB +pub const WR_DIS_TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OCODE +pub const WR_DIS_OCODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN0 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN1 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN2 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_INIT_CODE_ATTEN3 +pub const WR_DIS_ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_INIT_CODE_ATTEN0 +pub const WR_DIS_ADC2_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_INIT_CODE_ATTEN1 +pub const WR_DIS_ADC2_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_INIT_CODE_ATTEN2 +pub const WR_DIS_ADC2_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_INIT_CODE_ATTEN3 +pub const WR_DIS_ADC2_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN0 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN1 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN2 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CAL_VOL_ATTEN3 +pub const WR_DIS_ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_CAL_VOL_ATTEN0 +pub const WR_DIS_ADC2_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_CAL_VOL_ATTEN1 +pub const WR_DIS_ADC2_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC2_CAL_VOL_ATTEN2 +pub const WR_DIS_ADC2_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA +pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 +pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); +/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 +pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1); +/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2 +pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1); +/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3 +pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1); +/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4 +pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); +/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5 +pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1); +/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2 +pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1); +/// `[]` wr_dis of USB_EXCHG_PINS +pub const WR_DIS_USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[WR_DIS.EXT_PHY_ENABLE]` wr_dis of USB_EXT_PHY_ENABLE +pub const WR_DIS_USB_EXT_PHY_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 30, 1); +/// `[]` wr_dis of SOFT_DIS_JTAG +pub const WR_DIS_SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 31, 1); +/// `[]` Disable reading from BlOCK4-10 +pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7); +/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0 +pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1); +/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1 +pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1); +/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2 +pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1); +/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3 +pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1); +/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4 +pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1); +/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5 +pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1); +/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2 +pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1); +/// `[]` Set this bit to disable Icache +pub const DIS_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1); +/// `[]` Set this bit to disable Dcache +pub const DIS_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1); +/// `[]` Set this bit to disable Icache in download mode (boot_mode`[3:0]` is 0; +/// 1; 2; 3; 6; 7) +pub const DIS_DOWNLOAD_ICACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1); +/// `[]` Set this bit to disable Dcache in download mode ( boot_mode`[3:0]` is +/// 0; 1; 2; 3; 6; 7) +pub const DIS_DOWNLOAD_DCACHE: EfuseField = EfuseField::new(EfuseBlock::Block0, 43, 1); +/// `[]` Set this bit to disable the function that forces chip into download +/// mode +pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1); +/// `[DIS_USB]` Set this bit to disable USB function +pub const DIS_USB_OTG: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1); +/// `[DIS_CAN]` Set this bit to disable CAN function +pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1); +/// `[]` Disable app cpu +pub const DIS_APP_CPU: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1); +/// `[]` Set these bits to disable JTAG in the soft way (odd number 1 means +/// disable ). JTAG can be enabled in HMAC module +pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 3); +/// `[HARD_DIS_JTAG]` Set this bit to disable JTAG in the hard way. JTAG is +/// disabled permanently +pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1); +/// `[]` Set this bit to disable flash encryption when in download boot modes +pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 52, 1); +/// `[]` Set this bit to exchange USB D+ and D- pins +pub const USB_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); +/// `[EXT_PHY_ENABLE]` Set this bit to enable external PHY +pub const USB_EXT_PHY_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 1); +/// `[]` SPI regulator power up signal +pub const VDD_SPI_XPD: EfuseField = EfuseField::new(EfuseBlock::Block0, 68, 1); +/// `[]` If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects +/// to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"} +pub const VDD_SPI_TIEH: EfuseField = EfuseField::new(EfuseBlock::Block0, 69, 1); +/// `[]` Set this bit and force to use the configuration of eFuse to configure +/// VDD_SPI +pub const VDD_SPI_FORCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 70, 1); +/// `[]` RTC watchdog timeout threshold; in unit of slow clock cycle {0: +/// "40000"; 1: "80000"; 2: "160000"; 3: "320000"} +pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2); +/// `[]` Enables flash encryption when 1 or 3 bits are set and disabled +/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3); +/// `[]` Revoke 1st secure boot key +pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1); +/// `[]` Revoke 2nd secure boot key +pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1); +/// `[]` Revoke 3rd secure boot key +pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1); +/// `[KEY0_PURPOSE]` Purpose of Key0 +pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4); +/// `[KEY1_PURPOSE]` Purpose of Key1 +pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4); +/// `[KEY2_PURPOSE]` Purpose of Key2 +pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4); +/// `[KEY3_PURPOSE]` Purpose of Key3 +pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4); +/// `[KEY4_PURPOSE]` Purpose of Key4 +pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4); +/// `[KEY5_PURPOSE]` Purpose of Key5 +pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4); +/// `[]` Set this bit to enable secure boot +pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1); +/// `[]` Set this bit to enable revoking aggressive secure boot +pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1); +/// `[]` Set this bit to disable function of usb switch to jtag in module of usb +/// device +pub const DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 118, 1); +/// `[DIS_USB_DEVICE]` Set this bit to disable usb device +pub const DIS_USB_SERIAL_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 119, 1); +/// `[]` Set this bit to enable selection between usb_to_jtag and pad_to_jtag +/// through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are +/// equal to 0 +pub const STRAP_JTAG_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 120, 1); +/// `[]` This bit is used to switch internal PHY and external PHY for USB OTG +/// and USB Device {0: "internal PHY is assigned to USB Device while external +/// PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while +/// external PHY is assigned to USB Device"} +pub const USB_PHY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 121, 1); +/// `[]` Configures flash waiting time after power-up; in unit of ms. If the +/// value is less than 15; the waiting time is the configurable value. +/// Otherwise; the waiting time is twice the configurable value +pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4); +/// `[]` Set this bit to disable download mode (boot_mode`[3:0]` = 0; 1; 2; 3; +/// 6; 7) +pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1); +/// `[DIS_LEGACY_SPI_BOOT]` Disable direct boot mode +pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1); +/// `[UART_PRINT_CHANNEL]` USB printing {0: "Enable"; 1: "Disable"} +pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1); +/// `[]` Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"} +pub const FLASH_ECC_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 131, 1); +/// `[DIS_USB_DOWNLOAD_MODE]` Set this bit to disable UART download mode through +/// USB +pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField = + EfuseField::new(EfuseBlock::Block0, 132, 1); +/// `[]` Set this bit to enable secure UART download mode +pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1); +/// `[]` Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"} +pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2); +/// `[]` Set default power supply for GPIO33-GPIO37; set when SPI flash is +/// initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"} +pub const PIN_POWER_SELECTION: EfuseField = EfuseField::new(EfuseBlock::Block0, 136, 1); +/// `[]` SPI flash type {0: "4 data lines"; 1: "8 data lines"} +pub const FLASH_TYPE: EfuseField = EfuseField::new(EfuseBlock::Block0, 137, 1); +/// `[]` Set Flash page size +pub const FLASH_PAGE_SIZE: EfuseField = EfuseField::new(EfuseBlock::Block0, 138, 2); +/// `[]` Set 1 to enable ECC for flash boot +pub const FLASH_ECC_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 140, 1); +/// `[]` Set this bit to force ROM code to send a resume command during SPI boot +pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 141, 1); +/// `[]` Secure version (used by ESP-IDF anti-rollback feature) +pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 142, 16); +/// `[]` Set this bit to disable download through USB-OTG +pub const DIS_USB_OTG_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 159, 1); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 1); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); +/// `[MAC_FACTORY]` MAC address +pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +/// `[]` SPI_PAD_configure CLK +pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 6); +/// `[]` SPI_PAD_configure Q(D1) +pub const SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(EfuseBlock::Block1, 54, 6); +/// `[]` SPI_PAD_configure D(D0) +pub const SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(EfuseBlock::Block1, 60, 6); +/// `[]` SPI_PAD_configure CS +pub const SPI_PAD_CONFIG_CS: EfuseField = EfuseField::new(EfuseBlock::Block1, 66, 6); +/// `[]` SPI_PAD_configure HD(D3) +pub const SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(EfuseBlock::Block1, 72, 6); +/// `[]` SPI_PAD_configure WP(D2) +pub const SPI_PAD_CONFIG_WP: EfuseField = EfuseField::new(EfuseBlock::Block1, 78, 6); +/// `[]` SPI_PAD_configure DQS +pub const SPI_PAD_CONFIG_DQS: EfuseField = EfuseField::new(EfuseBlock::Block1, 84, 6); +/// `[]` SPI_PAD_configure D4 +pub const SPI_PAD_CONFIG_D4: EfuseField = EfuseField::new(EfuseBlock::Block1, 90, 6); +/// `[]` SPI_PAD_configure D5 +pub const SPI_PAD_CONFIG_D5: EfuseField = EfuseField::new(EfuseBlock::Block1, 96, 6); +/// `[]` SPI_PAD_configure D6 +pub const SPI_PAD_CONFIG_D6: EfuseField = EfuseField::new(EfuseBlock::Block1, 102, 6); +/// `[]` SPI_PAD_configure D7 +pub const SPI_PAD_CONFIG_D7: EfuseField = EfuseField::new(EfuseBlock::Block1, 108, 6); +/// `[]` WAFER_VERSION_MINOR least significant bits +pub const WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 3); +/// `[]` Package version +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 3); +/// `[]` BLK_VERSION_MINOR +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); +/// `[]` BLOCK1 K_RTC_LDO +pub const K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block1, 141, 7); +/// `[]` BLOCK1 K_DIG_LDO +pub const K_DIG_LDO: EfuseField = EfuseField::new(EfuseBlock::Block1, 148, 7); +/// `[]` BLOCK1 voltage of rtc dbias20 +pub const V_RTC_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block1, 155, 8); +/// `[]` BLOCK1 voltage of digital dbias20 +pub const V_DIG_DBIAS20: EfuseField = EfuseField::new(EfuseBlock::Block1, 163, 8); +/// `[]` BLOCK1 digital dbias when hvt +pub const DIG_DBIAS_HVT: EfuseField = EfuseField::new(EfuseBlock::Block1, 171, 5); +/// `[]` WAFER_VERSION_MINOR most significant bit +pub const WAFER_VERSION_MINOR_HI: EfuseField = EfuseField::new(EfuseBlock::Block1, 183, 1); +/// `[]` WAFER_VERSION_MAJOR +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 184, 2); +/// `[]` ADC2 calibration voltage at atten3 +pub const ADC2_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block1, 186, 6); +/// `[]` Optional unique 128-bit ID +pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128); +/// `[]` BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"} +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 128, 2); +/// `[]` Temperature calibration data +pub const TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 132, 9); +/// `[]` ADC OCode +pub const OCODE: EfuseField = EfuseField::new(EfuseBlock::Block2, 141, 8); +/// `[]` ADC1 init code at atten0 +pub const ADC1_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 149, 8); +/// `[]` ADC1 init code at atten1 +pub const ADC1_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 157, 6); +/// `[]` ADC1 init code at atten2 +pub const ADC1_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 163, 6); +/// `[]` ADC1 init code at atten3 +pub const ADC1_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 169, 6); +/// `[]` ADC2 init code at atten0 +pub const ADC2_INIT_CODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 175, 8); +/// `[]` ADC2 init code at atten1 +pub const ADC2_INIT_CODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 183, 6); +/// `[]` ADC2 init code at atten2 +pub const ADC2_INIT_CODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 189, 6); +/// `[]` ADC2 init code at atten3 +pub const ADC2_INIT_CODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 195, 6); +/// `[]` ADC1 calibration voltage at atten0 +pub const ADC1_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 201, 8); +/// `[]` ADC1 calibration voltage at atten1 +pub const ADC1_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 209, 8); +/// `[]` ADC1 calibration voltage at atten2 +pub const ADC1_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 217, 8); +/// `[]` ADC1 calibration voltage at atten3 +pub const ADC1_CAL_VOL_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 225, 8); +/// `[]` ADC2 calibration voltage at atten0 +pub const ADC2_CAL_VOL_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 233, 8); +/// `[]` ADC2 calibration voltage at atten1 +pub const ADC2_CAL_VOL_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 241, 7); +/// `[]` ADC2 calibration voltage at atten2 +pub const ADC2_CAL_VOL_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 248, 7); +/// `[BLOCK_USR_DATA]` User data +pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC +pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); +/// `[BLOCK_KEY0]` Key0 or user data +pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); +/// `[BLOCK_KEY1]` Key1 or user data +pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256); +/// `[BLOCK_KEY2]` Key2 or user data +pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256); +/// `[BLOCK_KEY3]` Key3 or user data +pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256); +/// `[BLOCK_KEY4]` Key4 or user data +pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256); +/// `[BLOCK_KEY5]` Key5 or user data +pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256); +/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved) +pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256); diff --git a/esp-hal/src/soc/esp32s3/efuse.rs b/esp-hal/src/soc/esp32s3/efuse/mod.rs similarity index 99% rename from esp-hal/src/soc/esp32s3/efuse.rs rename to esp-hal/src/soc/esp32s3/efuse/mod.rs index 5b51b7e9088..08b0f2fb9ce 100644 --- a/esp-hal/src/soc/esp32s3/efuse.rs +++ b/esp-hal/src/soc/esp32s3/efuse/mod.rs @@ -33,9 +33,11 @@ //! ); //! ``` -pub use crate::soc::efuse_field::*; +pub use self::fields::*; use crate::{analog::adc::Attenuation, peripherals::EFUSE}; +mod fields; + pub struct Efuse; impl Efuse { diff --git a/xtask/README.md b/xtask/README.md index e0d4bc3980c..0363456690e 100644 --- a/xtask/README.md +++ b/xtask/README.md @@ -8,11 +8,13 @@ Automation using [cargo-xtask](https://github.com/matklad/cargo-xtask). Usage: xtask Commands: - build-documentation Build documentation for the specified chip - build-examples Build all examples for the specified chip - build-package Build the specified package with the given options - bump-version Bump the version of the specified package(s) - help Print this message or the help of the given subcommand(s) + build-documentation Build documentation for the specified chip + build-examples Build all examples for the specified chip + build-package Build the specified package with the given options + bump-version Bump the version of the specified package(s) + generate-efuse-fields Generate the eFuse fields source file from a CSV + run-example Run the given example for the specified chip + help Print this message or the help of the given subcommand(s) Options: -h, --help Print help diff --git a/xtask/src/lib.rs b/xtask/src/lib.rs index 5083c1d0fce..92487f422a8 100644 --- a/xtask/src/lib.rs +++ b/xtask/src/lib.rs @@ -1,6 +1,7 @@ use std::{ collections::VecDeque, - fs, + fs::{self, File}, + io::{BufRead as _, BufReader, Write as _}, path::{Path, PathBuf}, }; @@ -10,7 +11,7 @@ use strum::{Display, EnumIter, IntoEnumIterator}; use self::cargo::CargoArgsBuilder; -mod cargo; +pub mod cargo; #[derive(Debug, Clone, Copy, PartialEq, Eq, Display, EnumIter, ValueEnum)] #[strum(serialize_all = "kebab-case")] @@ -65,6 +66,19 @@ impl Chip { _ => bail!("Chip does not contain an LP core: '{}'", self), } } + + pub fn pretty_name(&self) -> &str { + match self { + Chip::Esp32 => "ESP32", + Chip::Esp32c2 => "ESP32-C2", + Chip::Esp32c3 => "ESP32-C3", + Chip::Esp32c6 => "ESP32-C6", + Chip::Esp32h2 => "ESP32-H2", + Chip::Esp32p4 => "ESP32-P4", + Chip::Esp32s2 => "ESP32-S2", + Chip::Esp32s3 => "ESP32-S3", + } + } } #[derive(Debug, Default, Clone)] @@ -387,6 +401,100 @@ pub fn bump_version(workspace: &Path, package: Package, amount: Version) -> Resu Ok(()) } +// File header for the generated eFuse fields. +const EFUSE_FIELDS_RS_HEADER: &str = r#" +//! eFuse fields for the $CHIP. +//! +//! This file was automatically generated, please do not edit it manually! +//! +//! For information on how to regenerate these files, please refer to the +//! `xtask` package's `README.md` file. + +use super::EfuseBlock; +use crate::soc::efuse_field::EfuseField; +"#; + +/// Generate Rust constants for each eFuse field defined in the given CSV file. +pub fn generate_efuse_table( + chip: &Chip, + csv_path: impl AsRef, + out_path: impl AsRef, +) -> Result<()> { + let csv_path = csv_path.as_ref(); + let out_path = out_path.as_ref(); + + // Create the reader and writer from our source and destination file paths: + let mut reader = BufReader::new(File::open(csv_path)?); + let mut writer = File::create(out_path)?; + + // Write the header to the destination file: + writeln!( + writer, + "{}", + EFUSE_FIELDS_RS_HEADER + .trim_start() + .replace("$CHIP", chip.pretty_name()) + )?; + + // Generate constants from the CSV eFuse table, and write them out to + // the destination file: + let mut line = String::with_capacity(128); + while reader.read_line(&mut line)? > 0 { + line = line + .trim_end_matches('\n') + .trim_end_matches('\r') + .to_string(); + + // Drop comment and trim: + line.truncate( + if let Some((prefix, _comment)) = line.split_once('#') { + prefix + } else { + &line + } + .trim() + .len(), + ); + + // Skip empty lines (and in turn, comments): + if line.is_empty() { + continue; + } + + let mut fields = line.split(','); + + match ( + fields.next().map(|s| s.trim().replace('.', "_")), + fields + .next() + .map(|s| s.trim().replace(|c: char| !c.is_ascii_digit(), "")), + fields + .next() + .map(|s| s.trim()) + .and_then(|s| s.parse::().ok()), + fields + .next() + .map(|s| s.trim()) + .and_then(|s| s.parse::().ok()), + fields.next().map(|s| s.trim()), + ) { + (Some(name), Some(block), Some(bit_off), Some(bit_len), Some(desc)) => { + let desc = desc.replace('[', "`[").replace(']', "]`"); + writeln!(writer, "/// {desc}")?; + writeln!( + writer, + "pub const {name}: EfuseField = EfuseField::new(EfuseBlock::Block{block}, {bit_off}, {bit_len});" + )?; + } + other => eprintln!("Invalid data: {other:?}"), + } + + line.clear(); + } + + Ok(()) +} + /// Make the path "Windows"-safe pub fn windows_safe_path(path: &Path) -> PathBuf { PathBuf::from(path.to_str().unwrap().to_string().replace("\\\\?\\", "")) diff --git a/xtask/src/main.rs b/xtask/src/main.rs index c98d9e0c23b..b9464483981 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -19,10 +19,12 @@ enum Cli { BuildExamples(BuildExamplesArgs), /// Build the specified package with the given options. BuildPackage(BuildPackageArgs), + /// Bump the version of the specified package(s). + BumpVersion(BumpVersionArgs), + /// Generate the eFuse fields source file from a CSV. + GenerateEfuseFields(GenerateEfuseFieldsArgs), /// Run the given example for the specified chip. RunExample(RunExampleArgs), - /// Bump the version of the specified package(s) - BumpVersion(BumpVersionArgs), } #[derive(Debug, Args)] @@ -68,15 +70,12 @@ struct BuildPackageArgs { } #[derive(Debug, Args)] -struct RunExampleArgs { - /// Package to run example from. - #[arg(value_enum)] - package: Package, - /// Which chip to run the examples for. +struct GenerateEfuseFieldsArgs { + /// Chip to build eFuse fields table for. #[arg(value_enum)] chip: Chip, - /// Which example to run - example: String, + /// Path to the CSV file containing the eFuse fields. + csv: PathBuf, } #[derive(Debug, Args)] @@ -89,6 +88,18 @@ struct BumpVersionArgs { packages: Vec, } +#[derive(Debug, Args)] +struct RunExampleArgs { + /// Package to run example from. + #[arg(value_enum)] + package: Package, + /// Which chip to run the examples for. + #[arg(value_enum)] + chip: Chip, + /// Which example to run + example: String, +} + // ---------------------------------------------------------------------------- // Application @@ -104,8 +115,9 @@ fn main() -> Result<()> { Cli::BuildDocumentation(args) => build_documentation(&workspace, args), Cli::BuildExamples(args) => build_examples(&workspace, args), Cli::BuildPackage(args) => build_package(&workspace, args), - Cli::RunExample(args) => run_example(&workspace, args), Cli::BumpVersion(args) => bump_version(&workspace, args), + Cli::GenerateEfuseFields(args) => generate_efuse_src(&workspace, args), + Cli::RunExample(args) => run_example(&workspace, args), } } @@ -189,6 +201,38 @@ fn build_package(workspace: &Path, args: BuildPackageArgs) -> Result<()> { xtask::build_package(&package_path, args.features, args.toolchain, args.target) } +fn bump_version(workspace: &Path, args: BumpVersionArgs) -> Result<()> { + // Bump the version by the specified amount for each given package: + for package in args.packages { + xtask::bump_version(workspace, package, args.amount)?; + } + + Ok(()) +} + +fn generate_efuse_src(workspace: &Path, args: GenerateEfuseFieldsArgs) -> Result<()> { + // Read the CSV file containing the eFuse field definitions: + let csv_path = args.csv.canonicalize()?; + + // Build the path for the generated source file, for the specified chip: + let esp_hal = workspace.join("esp-hal"); + let out_path = esp_hal + .join("src") + .join("soc") + .join(args.chip.to_string()) + .join("efuse") + .join("fields.rs"); + + // Generate the Rust source file from the CSV file, and write it out to + // the appropriate path: + xtask::generate_efuse_table(&args.chip, &csv_path, out_path)?; + + // Format the generated code: + xtask::cargo::run(&["fmt".into()], &esp_hal)?; + + Ok(()) +} + fn run_example(workspace: &Path, mut args: RunExampleArgs) -> Result<()> { // Ensure that the package/chip combination provided are valid: validate_package_chip(&args.package, &args.chip)?; @@ -239,15 +283,6 @@ fn run_example(workspace: &Path, mut args: RunExampleArgs) -> Result<()> { Ok(()) } -fn bump_version(workspace: &Path, args: BumpVersionArgs) -> Result<()> { - // Bump the version by the specified amount for each given package: - for package in args.packages { - xtask::bump_version(workspace, package, args.amount)?; - } - - Ok(()) -} - // ---------------------------------------------------------------------------- // Helper Functions From cb82118ff22c2f75b365d202466a79f76128208d Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Fri, 8 Mar 2024 09:12:59 -0800 Subject: [PATCH 2/4] Rewrite the CSV parser so that it can handle the newer eFuse definitions --- xtask/Cargo.toml | 2 + xtask/src/lib.rs | 130 ++++++++++++++++++++++++++++++----------------- 2 files changed, 84 insertions(+), 48 deletions(-) diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml index cd4ea33e0c9..d0a81dd1978 100644 --- a/xtask/Cargo.toml +++ b/xtask/Cargo.toml @@ -7,8 +7,10 @@ publish = false [dependencies] anyhow = "1.0.79" clap = { version = "4.5.0", features = ["derive"] } +csv = "1.3.0" env_logger = "0.11.1" log = "0.4.20" semver = "1.0.21" +serde = { version = "1.0.197", features = ["derive"] } strum = { version = "0.26.1", features = ["derive"] } toml_edit = "0.22.5" diff --git a/xtask/src/lib.rs b/xtask/src/lib.rs index 92487f422a8..704618ef86e 100644 --- a/xtask/src/lib.rs +++ b/xtask/src/lib.rs @@ -1,13 +1,13 @@ use std::{ collections::VecDeque, fs::{self, File}, - io::{BufRead as _, BufReader, Write as _}, + io::Write as _, path::{Path, PathBuf}, }; use anyhow::{bail, Result}; use clap::ValueEnum; -use strum::{Display, EnumIter, IntoEnumIterator}; +use strum::{Display, EnumIter, IntoEnumIterator as _}; use self::cargo::CargoArgsBuilder; @@ -414,6 +414,15 @@ use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; "#; +#[derive(Debug, Clone, PartialEq, serde::Deserialize)] +struct EfuseField { + field_name: String, + efuse_block: String, + bit_start: u32, + bit_count: u32, + description: String, +} + /// Generate Rust constants for each eFuse field defined in the given CSV file. pub fn generate_efuse_table( chip: &Chip, @@ -424,7 +433,11 @@ pub fn generate_efuse_table( let out_path = out_path.as_ref(); // Create the reader and writer from our source and destination file paths: - let mut reader = BufReader::new(File::open(csv_path)?); + let mut reader = csv::ReaderBuilder::new() + .comment(Some(b'#')) + .has_headers(false) + .trim(csv::Trim::All) + .from_path(csv_path)?; let mut writer = File::create(out_path)?; // Write the header to the destination file: @@ -436,60 +449,81 @@ pub fn generate_efuse_table( .replace("$CHIP", chip.pretty_name()) )?; - // Generate constants from the CSV eFuse table, and write them out to - // the destination file: - let mut line = String::with_capacity(128); - while reader.read_line(&mut line)? > 0 { - line = line - .trim_end_matches('\n') - .trim_end_matches('\r') - .to_string(); - - // Drop comment and trim: - line.truncate( - if let Some((prefix, _comment)) = line.split_once('#') { + // Build a vector of parsed eFuse fields; we build this vector up first rather + // than writing directly to the destination file, as we need to do some + // pre-processing first: + let mut fields = VecDeque::new(); + for result in reader.deserialize() { + // We will print a warning and just ignore any fields which cannot be + // successfull parsed: + let mut efuse_field: EfuseField = match result { + Ok(field) => field, + Err(e) => { + log::warn!("{e}"); + continue; + } + }; + + // Remove any comments from the eFuse field descriptions: + efuse_field.description.truncate( + if let Some((prefix, _comment)) = efuse_field.description.split_once('#') { prefix } else { - &line + &efuse_field.description } - .trim() + .trim_end() .len(), ); - // Skip empty lines (and in turn, comments): - if line.is_empty() { - continue; - } + // Link to other eFuse fields in documentation, using code blocks: + efuse_field.description = efuse_field + .description + .replace('[', "`[") + .replace(']', "]`"); - let mut fields = line.split(','); - - match ( - fields.next().map(|s| s.trim().replace('.', "_")), - fields - .next() - .map(|s| s.trim().replace(|c: char| !c.is_ascii_digit(), "")), - fields - .next() - .map(|s| s.trim()) - .and_then(|s| s.parse::().ok()), - fields - .next() - .map(|s| s.trim()) - .and_then(|s| s.parse::().ok()), - fields.next().map(|s| s.trim()), - ) { - (Some(name), Some(block), Some(bit_off), Some(bit_len), Some(desc)) => { - let desc = desc.replace('[', "`[").replace(']', "]`"); - writeln!(writer, "/// {desc}")?; - writeln!( - writer, - "pub const {name}: EfuseField = EfuseField::new(EfuseBlock::Block{block}, {bit_off}, {bit_len});" - )?; - } - other => eprintln!("Invalid data: {other:?}"), + // Convert the eFuse field name into a valid Rust iddentifier: + efuse_field.field_name = efuse_field.field_name.replace('.', "_"); + + // Replace any non-digit characters in the eFuse block: + efuse_field.efuse_block = efuse_field + .efuse_block + .replace(|c: char| !c.is_ascii_digit(), ""); + + fields.push_back(efuse_field); + } + + // Now that we've parsed all eFuse field definitions, we can perform our + // pre-processing; right now, this just means handling any multi-world + // fields: + let mut i = 0; + while i < fields.len() { + let field = fields[i].clone(); + + if field.field_name.is_empty() { + let mut prev = fields[i - 1].clone(); + prev.bit_start = field.bit_start; + prev.bit_count += field.bit_count; + fields[i - 1] = prev; + + fields.retain(|x| *x != field); + } else { + i += 1; } + } - line.clear(); + // Finally, write out each eFuse field definition to the destination file: + while let Some(EfuseField { + field_name, + efuse_block, + bit_start, + bit_count, + description, + }) = fields.pop_front() + { + writeln!(writer, "/// {description}")?; + writeln!(writer, + "pub const {field_name}: EfuseField = EfuseField::new(EfuseBlock::Block{efuse_block}, {bit_start}, {bit_count});" + )?; } Ok(()) From 861b42ebbd2a5c66f1b237306c5ced1e614d9731 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Fri, 8 Mar 2024 09:14:30 -0800 Subject: [PATCH 3/4] Regenerate eFuse field definitions from latest ESP-IDF commit --- esp-hal/src/soc/esp32/efuse/fields.rs | 2 +- esp-hal/src/soc/esp32/efuse/mod.rs | 2 +- esp-hal/src/soc/esp32c2/efuse/fields.rs | 2 +- esp-hal/src/soc/esp32c2/efuse/mod.rs | 2 +- esp-hal/src/soc/esp32c3/efuse/fields.rs | 15 +++- esp-hal/src/soc/esp32c3/efuse/mod.rs | 2 +- esp-hal/src/soc/esp32c6/efuse/fields.rs | 30 +++++++- esp-hal/src/soc/esp32c6/efuse/mod.rs | 2 +- esp-hal/src/soc/esp32h2/efuse/fields.rs | 95 ++++++++++++++++++++++--- esp-hal/src/soc/esp32h2/efuse/mod.rs | 2 +- esp-hal/src/soc/esp32p4/efuse/fields.rs | 76 ++++++++++++++++---- esp-hal/src/soc/esp32s2/efuse/fields.rs | 2 +- esp-hal/src/soc/esp32s2/efuse/mod.rs | 2 +- esp-hal/src/soc/esp32s3/efuse/fields.rs | 26 ++++++- esp-hal/src/soc/esp32s3/efuse/mod.rs | 2 +- 15 files changed, 227 insertions(+), 35 deletions(-) diff --git a/esp-hal/src/soc/esp32/efuse/fields.rs b/esp-hal/src/soc/esp32/efuse/fields.rs index b1fb8798a78..2062355ce81 100644 --- a/esp-hal/src/soc/esp32/efuse/fields.rs +++ b/esp-hal/src/soc/esp32/efuse/fields.rs @@ -129,7 +129,7 @@ pub const FLASH_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, /// `[]` Disable UART download mode. Valid for ESP32 V3 and newer; only pub const UART_DOWNLOAD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 48); /// `[MAC_FACTORY_CRC]` CRC8 for MAC address pub const MAC_CRC: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 8); /// `[CHIP_VER_DIS_APP_CPU]` Disables APP CPU diff --git a/esp-hal/src/soc/esp32/efuse/mod.rs b/esp-hal/src/soc/esp32/efuse/mod.rs index 09e9f3e84a3..c60cf8fc962 100644 --- a/esp-hal/src/soc/esp32/efuse/mod.rs +++ b/esp-hal/src/soc/esp32/efuse/mod.rs @@ -54,7 +54,7 @@ pub enum ChipType { impl Efuse { pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Returns the number of CPUs available on the chip. diff --git a/esp-hal/src/soc/esp32c2/efuse/fields.rs b/esp-hal/src/soc/esp32c2/efuse/fields.rs index 7897616a5c4..bb712b489af 100644 --- a/esp-hal/src/soc/esp32c2/efuse/fields.rs +++ b/esp-hal/src/soc/esp32c2/efuse/fields.rs @@ -152,7 +152,7 @@ pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 88); /// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC address pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 48); /// `[]` WAFER_VERSION_MINOR pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 48, 4); /// `[]` WAFER_VERSION_MAJOR diff --git a/esp-hal/src/soc/esp32c2/efuse/mod.rs b/esp-hal/src/soc/esp32c2/efuse/mod.rs index cdf25cfa140..f738dc48aff 100644 --- a/esp-hal/src/soc/esp32c2/efuse/mod.rs +++ b/esp-hal/src/soc/esp32c2/efuse/mod.rs @@ -43,7 +43,7 @@ pub struct Efuse; impl Efuse { /// Reads chip's MAC address from the eFuse storage. pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Get status of SPI boot encryption. diff --git a/esp-hal/src/soc/esp32c3/efuse/fields.rs b/esp-hal/src/soc/esp32c3/efuse/fields.rs index 5d749271b18..5b0779a6c78 100644 --- a/esp-hal/src/soc/esp32c3/efuse/fields.rs +++ b/esp-hal/src/soc/esp32c3/efuse/fields.rs @@ -117,6 +117,12 @@ pub const WR_DIS_WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of BLK_VERSION_MINOR pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_CAP +pub const WR_DIS_FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_TEMP +pub const WR_DIS_FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_VENDOR +pub const WR_DIS_FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of K_RTC_LDO pub const WR_DIS_K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of K_DIG_LDO @@ -290,7 +296,7 @@ pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock:: /// `[]` Disables check of blk version major pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); /// `[]` SPI PAD CLK pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 6); /// `[]` SPI PAD Q(D1) @@ -319,6 +325,13 @@ pub const WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 3); /// `[]` BLK_VERSION_MINOR pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); +/// `[]` Flash capacity {0: "None"; 1: "4M"; 2: "2M"; 3: "1M"; 4: "8M"} +pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 123, 3); +/// `[]` Flash temperature {0: "None"; 1: "105C"; 2: "85C"} +pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 126, 2); +/// `[]` Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: +/// "ZBIT"} +pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 128, 3); /// `[]` BLOCK1 K_RTC_LDO pub const K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block1, 135, 7); /// `[]` BLOCK1 K_DIG_LDO diff --git a/esp-hal/src/soc/esp32c3/efuse/mod.rs b/esp-hal/src/soc/esp32c3/efuse/mod.rs index 8a6a1fabfc7..ba146ec131f 100644 --- a/esp-hal/src/soc/esp32c3/efuse/mod.rs +++ b/esp-hal/src/soc/esp32c3/efuse/mod.rs @@ -43,7 +43,7 @@ pub struct Efuse; impl Efuse { /// Reads chip's MAC address from the eFuse storage. pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Get status of SPI boot encryption. diff --git a/esp-hal/src/soc/esp32c6/efuse/fields.rs b/esp-hal/src/soc/esp32c6/efuse/fields.rs index 79658ebf6e0..a8c0df06650 100644 --- a/esp-hal/src/soc/esp32c6/efuse/fields.rs +++ b/esp-hal/src/soc/esp32c6/efuse/fields.rs @@ -100,6 +100,20 @@ pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of MAC_EXT pub const WR_DIS_MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of ACTIVE_HP_DBIAS +pub const WR_DIS_ACTIVE_HP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of ACTIVE_LP_DBIAS +pub const WR_DIS_ACTIVE_LP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of LSLP_HP_DBG +pub const WR_DIS_LSLP_HP_DBG: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of LSLP_HP_DBIAS +pub const WR_DIS_LSLP_HP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DSLP_LP_DBG +pub const WR_DIS_DSLP_LP_DBG: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DSLP_LP_DBIAS +pub const WR_DIS_DSLP_LP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DBIAS_VOL_GAP +pub const WR_DIS_DBIAS_VOL_GAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of WAFER_VERSION_MINOR pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of WAFER_VERSION_MAJOR @@ -309,9 +323,23 @@ pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock:: /// `[]` Disables check of blk version major pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); /// `[]` Stores the extended bits of MAC address pub const MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 16); +/// `[]` Stores the active hp dbias +pub const ACTIVE_HP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 64, 5); +/// `[]` Stores the active lp dbias +pub const ACTIVE_LP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 69, 5); +/// `[]` Stores the lslp hp dbg +pub const LSLP_HP_DBG: EfuseField = EfuseField::new(EfuseBlock::Block1, 74, 2); +/// `[]` Stores the lslp hp dbias +pub const LSLP_HP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 76, 4); +/// `[]` Stores the dslp lp dbg +pub const DSLP_LP_DBG: EfuseField = EfuseField::new(EfuseBlock::Block1, 80, 3); +/// `[]` Stores the dslp lp dbias +pub const DSLP_LP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 83, 4); +/// `[]` Stores the hp and lp dbias vol gap +pub const DBIAS_VOL_GAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 87, 5); /// `[]` pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 4); /// `[]` diff --git a/esp-hal/src/soc/esp32c6/efuse/mod.rs b/esp-hal/src/soc/esp32c6/efuse/mod.rs index b4246ce47ac..9789eaa8547 100644 --- a/esp-hal/src/soc/esp32c6/efuse/mod.rs +++ b/esp-hal/src/soc/esp32c6/efuse/mod.rs @@ -43,7 +43,7 @@ pub struct Efuse; impl Efuse { /// Reads chip's MAC address from the eFuse storage. pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Get status of SPI boot encryption. diff --git a/esp-hal/src/soc/esp32h2/efuse/fields.rs b/esp-hal/src/soc/esp32h2/efuse/fields.rs index b3a29b39142..06979adb902 100644 --- a/esp-hal/src/soc/esp32h2/efuse/fields.rs +++ b/esp-hal/src/soc/esp32h2/efuse/fields.rs @@ -104,6 +104,14 @@ pub const WR_DIS_RXIQ_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, pub const WR_DIS_RXIQ_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of RXIQ_1 pub const WR_DIS_RXIQ_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of ACTIVE_HP_DBIAS +pub const WR_DIS_ACTIVE_HP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of ACTIVE_LP_DBIAS +pub const WR_DIS_ACTIVE_LP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DSLP_DBIAS +pub const WR_DIS_DSLP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DBIAS_VOL_GAP +pub const WR_DIS_DBIAS_VOL_GAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of WAFER_VERSION_MINOR pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of WAFER_VERSION_MAJOR @@ -129,6 +137,39 @@ pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Blo pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); /// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of TEMP_CALIB +pub const WR_DIS_TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_AVE_INITCODE_ATTEN0 +pub const WR_DIS_ADC1_AVE_INITCODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_AVE_INITCODE_ATTEN1 +pub const WR_DIS_ADC1_AVE_INITCODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_AVE_INITCODE_ATTEN2 +pub const WR_DIS_ADC1_AVE_INITCODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_AVE_INITCODE_ATTEN3 +pub const WR_DIS_ADC1_AVE_INITCODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_HI_DOUT_ATTEN0 +pub const WR_DIS_ADC1_HI_DOUT_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_HI_DOUT_ATTEN1 +pub const WR_DIS_ADC1_HI_DOUT_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_HI_DOUT_ATTEN2 +pub const WR_DIS_ADC1_HI_DOUT_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_HI_DOUT_ATTEN3 +pub const WR_DIS_ADC1_HI_DOUT_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF +pub const WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF: EfuseField = + EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF +pub const WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF: EfuseField = + EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF +pub const WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF: EfuseField = + EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF +pub const WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF: EfuseField = + EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF +pub const WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF: EfuseField = + EfuseField::new(EfuseBlock::Block0, 21, 1); /// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); /// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC @@ -281,26 +322,34 @@ pub const HYS_EN_PAD0: EfuseField = EfuseField::new(EfuseBlock::Block0, 154, 6); /// `[]` Set bits to enable hysteresis function of PAD6~27 pub const HYS_EN_PAD1: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 22); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); /// `[]` Stores the extended bits of MAC address pub const MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 16); -/// `[]` RF Calibration data. RXIQ version +/// `[]` Stores RF Calibration data. RXIQ version pub const RXIQ_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 64, 3); -/// `[]` RF Calibration data. RXIQ data 0 +/// `[]` Stores RF Calibration data. RXIQ data 0 pub const RXIQ_0: EfuseField = EfuseField::new(EfuseBlock::Block1, 67, 7); -/// `[]` RF Calibration data. RXIQ data 1 +/// `[]` Stores RF Calibration data. RXIQ data 1 pub const RXIQ_1: EfuseField = EfuseField::new(EfuseBlock::Block1, 74, 7); -/// `[]` +/// `[]` Stores the PMU active hp dbias +pub const ACTIVE_HP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 81, 5); +/// `[]` Stores the PMU active lp dbias +pub const ACTIVE_LP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 86, 5); +/// `[]` Stores the PMU sleep dbias +pub const DSLP_DBIAS: EfuseField = EfuseField::new(EfuseBlock::Block1, 91, 4); +/// `[]` Stores the low 1 bit of dbias_vol_gap +pub const DBIAS_VOL_GAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 95, 5); +/// `[]` Stores the wafer version minor pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 114, 3); -/// `[]` +/// `[]` Stores the wafer version major pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 2); /// `[]` Disables check of wafer version major pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 119, 1); -/// `[]` +/// `[]` Stores the flash cap pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); -/// `[]` +/// `[]` Stores the flash temp pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 123, 2); -/// `[]` +/// `[]` Stores the flash vendor pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 125, 3); /// `[]` Package version pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 128, 3); @@ -312,6 +361,34 @@ pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 13 pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 133, 2); /// `[]` Disables check of blk version major pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block2, 135, 1); +/// `[]` Temperature calibration data +pub const TEMP_CALIB: EfuseField = EfuseField::new(EfuseBlock::Block2, 136, 9); +/// `[]` ADC1 calibration data +pub const ADC1_AVE_INITCODE_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 145, 10); +/// `[]` ADC1 calibration data +pub const ADC1_AVE_INITCODE_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 155, 10); +/// `[]` ADC1 calibration data +pub const ADC1_AVE_INITCODE_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 165, 10); +/// `[]` ADC1 calibration data +pub const ADC1_AVE_INITCODE_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 175, 10); +/// `[]` ADC1 calibration data +pub const ADC1_HI_DOUT_ATTEN0: EfuseField = EfuseField::new(EfuseBlock::Block2, 185, 10); +/// `[]` ADC1 calibration data +pub const ADC1_HI_DOUT_ATTEN1: EfuseField = EfuseField::new(EfuseBlock::Block2, 195, 10); +/// `[]` ADC1 calibration data +pub const ADC1_HI_DOUT_ATTEN2: EfuseField = EfuseField::new(EfuseBlock::Block2, 205, 10); +/// `[]` ADC1 calibration data +pub const ADC1_HI_DOUT_ATTEN3: EfuseField = EfuseField::new(EfuseBlock::Block2, 215, 10); +/// `[]` ADC1 calibration data +pub const ADC1_CH0_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(EfuseBlock::Block2, 225, 4); +/// `[]` ADC1 calibration data +pub const ADC1_CH1_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(EfuseBlock::Block2, 229, 4); +/// `[]` ADC1 calibration data +pub const ADC1_CH2_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(EfuseBlock::Block2, 233, 4); +/// `[]` ADC1 calibration data +pub const ADC1_CH3_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(EfuseBlock::Block2, 237, 4); +/// `[]` ADC1 calibration data +pub const ADC1_CH4_ATTEN0_INITCODE_DIFF: EfuseField = EfuseField::new(EfuseBlock::Block2, 241, 4); /// `[BLOCK_USR_DATA]` User data pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); /// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC diff --git a/esp-hal/src/soc/esp32h2/efuse/mod.rs b/esp-hal/src/soc/esp32h2/efuse/mod.rs index 5c31e4eceb2..1028514b368 100644 --- a/esp-hal/src/soc/esp32h2/efuse/mod.rs +++ b/esp-hal/src/soc/esp32h2/efuse/mod.rs @@ -43,7 +43,7 @@ pub struct Efuse; impl Efuse { /// Reads chip's MAC address from the eFuse storage. pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Get status of SPI boot encryption. diff --git a/esp-hal/src/soc/esp32p4/efuse/fields.rs b/esp-hal/src/soc/esp32p4/efuse/fields.rs index 07d3e8a94b4..d7f45dd3fa7 100644 --- a/esp-hal/src/soc/esp32p4/efuse/fields.rs +++ b/esp-hal/src/soc/esp32p4/efuse/fields.rs @@ -38,12 +38,41 @@ pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0 pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); -/// `[]` wr_dis of MAC_EXT -pub const WR_DIS_MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); -/// `[WR_DIS.SYS_DATA_PART1]` wr_dis of BLOCK_SYS_DATA1 -pub const WR_DIS_BLOCK_SYS_DATA1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of WAFER_VERSION_MINOR +pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of WAFER_VERSION_MAJOR +pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR +pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField = + EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR +pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MINOR +pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLK_VERSION_MAJOR +pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_CAP +pub const WR_DIS_FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_TEMP +pub const WR_DIS_FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_VENDOR +pub const WR_DIS_FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_CAP +pub const WR_DIS_PSRAM_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_TEMP +pub const WR_DIS_PSRAM_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_VENDOR +pub const WR_DIS_PSRAM_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PKG_VERSION +pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of BLOCK2 +pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); +/// `[]` wr_dis of OPTIONAL_UNIQUE_ID +pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1); /// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); +/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC +pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1); /// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0 pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1); /// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1 @@ -110,10 +139,7 @@ pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock:: pub const USB_PHY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1); /// `[]` Set this bit to control validation of HUK generate mode. Odd of 1 is /// invalid; even of 1 is valid -pub const KM_HUK_GEN_STATE_LOW: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 6); -/// `[]` Set this bit to control validation of HUK generate mode. Odd of 1 is -/// invalid; even of 1 is valid -pub const KM_HUK_GEN_STATE_HIGH: EfuseField = EfuseField::new(EfuseBlock::Block0, 64, 3); +pub const KM_HUK_GEN_STATE: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 9); /// `[]` Set bits to control key manager random number switch cycle. 0: control /// by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles pub const KM_RND_SWITCH_CYCLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 67, 2); @@ -235,13 +261,37 @@ pub const DIS_WDT: EfuseField = EfuseField::new(EfuseBlock::Block0, 180, 1); pub const DIS_SWD: EfuseField = EfuseField::new(EfuseBlock::Block0, 181, 1); /// `[MAC_FACTORY]` MAC address pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); -/// `[]` Stores the extended bits of MAC address `[0]` -pub const MAC_EXT: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 16); -/// `[SYS_DATA_PART1]` System data part 1 -pub const BLOCK_SYS_DATA1: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 256); +/// `[]` Minor chip version +pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 64, 4); +/// `[]` Major chip version +pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 68, 2); +/// `[]` Disables check of wafer version major +pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 70, 1); +/// `[]` Disables check of blk version major +pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 71, 1); +/// `[]` BLK_VERSION_MINOR of BLOCK2 +pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 72, 3); +/// `[]` BLK_VERSION_MAJOR of BLOCK2 +pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 75, 2); +/// `[]` Flash capacity +pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 77, 3); +/// `[]` Flash temperature +pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 80, 2); +/// `[]` Flash vendor +pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 82, 3); +/// `[]` PSRAM capacity +pub const PSRAM_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 85, 2); +/// `[]` PSRAM temperature +pub const PSRAM_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 87, 2); +/// `[]` PSRAM vendor +pub const PSRAM_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 89, 2); +/// `[]` Package version +pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 91, 3); +/// `[]` Optional unique 128-bit ID +pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128); /// `[BLOCK_USR_DATA]` User data pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256); -/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC (TODO +/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48); /// `[BLOCK_KEY0]` Key0 or user data pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256); diff --git a/esp-hal/src/soc/esp32s2/efuse/fields.rs b/esp-hal/src/soc/esp32s2/efuse/fields.rs index e9657663330..3afd12f3d93 100644 --- a/esp-hal/src/soc/esp32s2/efuse/fields.rs +++ b/esp-hal/src/soc/esp32s2/efuse/fields.rs @@ -315,7 +315,7 @@ pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock:: /// `[]` Disables check of blk version major pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); /// `[]` SPI_PAD_configure CLK pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 6); /// `[]` SPI_PAD_configure Q(D1) diff --git a/esp-hal/src/soc/esp32s2/efuse/mod.rs b/esp-hal/src/soc/esp32s2/efuse/mod.rs index 55b3ec6c3e1..eb013b2502a 100644 --- a/esp-hal/src/soc/esp32s2/efuse/mod.rs +++ b/esp-hal/src/soc/esp32s2/efuse/mod.rs @@ -59,7 +59,7 @@ impl Efuse { /// ); /// ``` pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Get status of SPI boot encryption. diff --git a/esp-hal/src/soc/esp32s3/efuse/fields.rs b/esp-hal/src/soc/esp32s3/efuse/fields.rs index 9f9b5452a94..0bf034071bb 100644 --- a/esp-hal/src/soc/esp32s3/efuse/fields.rs +++ b/esp-hal/src/soc/esp32s3/efuse/fields.rs @@ -143,6 +143,18 @@ pub const WR_DIS_WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of BLK_VERSION_MINOR pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_CAP +pub const WR_DIS_FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_TEMP +pub const WR_DIS_FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of FLASH_VENDOR +pub const WR_DIS_FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_CAP +pub const WR_DIS_PSRAM_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_TEMP +pub const WR_DIS_PSRAM_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); +/// `[]` wr_dis of PSRAM_VENDOR +pub const WR_DIS_PSRAM_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of K_RTC_LDO pub const WR_DIS_K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1); /// `[]` wr_dis of K_DIG_LDO @@ -361,7 +373,7 @@ pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock:: /// `[]` Disables check of blk version major pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 161, 1); /// `[MAC_FACTORY]` MAC address -pub const MAC_FACTORY: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); +pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48); /// `[]` SPI_PAD_configure CLK pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(EfuseBlock::Block1, 48, 6); /// `[]` SPI_PAD_configure Q(D1) @@ -390,6 +402,18 @@ pub const WAFER_VERSION_MINOR_LO: EfuseField = EfuseField::new(EfuseBlock::Block pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 117, 3); /// `[]` BLK_VERSION_MINOR pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 120, 3); +/// `[]` Flash capacity {0: "None"; 1: "8M"; 2: "4M"} +pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 123, 3); +/// `[]` Flash temperature {0: "None"; 1: "105C"; 2: "85C"} +pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 126, 2); +/// `[]` Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"} +pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 128, 3); +/// `[]` PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"} +pub const PSRAM_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 131, 2); +/// `[]` PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"} +pub const PSRAM_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 133, 2); +/// `[]` PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"} +pub const PSRAM_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 135, 2); /// `[]` BLOCK1 K_RTC_LDO pub const K_RTC_LDO: EfuseField = EfuseField::new(EfuseBlock::Block1, 141, 7); /// `[]` BLOCK1 K_DIG_LDO diff --git a/esp-hal/src/soc/esp32s3/efuse/mod.rs b/esp-hal/src/soc/esp32s3/efuse/mod.rs index 08b0f2fb9ce..be223fc2c6b 100644 --- a/esp-hal/src/soc/esp32s3/efuse/mod.rs +++ b/esp-hal/src/soc/esp32s3/efuse/mod.rs @@ -43,7 +43,7 @@ pub struct Efuse; impl Efuse { /// Reads chip's MAC address from the eFuse storage. pub fn read_base_mac_address() -> [u8; 6] { - Self::read_field_be(MAC_FACTORY) + Self::read_field_be(MAC) } /// Get status of SPI boot encryption. From 63aef84d205964573e815cf36dfa721f86014b4b Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Mon, 11 Mar 2024 07:16:57 -0700 Subject: [PATCH 4/4] Include generation date and ESP-IDF commit hash in file headers --- esp-hal/src/soc/esp32/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32c2/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32c3/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32c6/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32h2/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32p4/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32s2/efuse/fields.rs | 3 +++ esp-hal/src/soc/esp32s3/efuse/fields.rs | 3 +++ xtask/Cargo.toml | 1 + xtask/src/lib.rs | 28 +++++++++++++++++++++++-- xtask/src/main.rs | 9 ++++---- 11 files changed, 55 insertions(+), 7 deletions(-) diff --git a/esp-hal/src/soc/esp32/efuse/fields.rs b/esp-hal/src/soc/esp32/efuse/fields.rs index 2062355ce81..68ed77cec14 100644 --- a/esp-hal/src/soc/esp32/efuse/fields.rs +++ b/esp-hal/src/soc/esp32/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32c2/efuse/fields.rs b/esp-hal/src/soc/esp32c2/efuse/fields.rs index bb712b489af..393f873887b 100644 --- a/esp-hal/src/soc/esp32c2/efuse/fields.rs +++ b/esp-hal/src/soc/esp32c2/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32c3/efuse/fields.rs b/esp-hal/src/soc/esp32c3/efuse/fields.rs index 5b0779a6c78..29e2c2e86e3 100644 --- a/esp-hal/src/soc/esp32c3/efuse/fields.rs +++ b/esp-hal/src/soc/esp32c3/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32c6/efuse/fields.rs b/esp-hal/src/soc/esp32c6/efuse/fields.rs index a8c0df06650..c9867e0d251 100644 --- a/esp-hal/src/soc/esp32c6/efuse/fields.rs +++ b/esp-hal/src/soc/esp32c6/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32h2/efuse/fields.rs b/esp-hal/src/soc/esp32h2/efuse/fields.rs index 06979adb902..55d9dbea1a7 100644 --- a/esp-hal/src/soc/esp32h2/efuse/fields.rs +++ b/esp-hal/src/soc/esp32h2/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32p4/efuse/fields.rs b/esp-hal/src/soc/esp32p4/efuse/fields.rs index d7f45dd3fa7..6d47368e518 100644 --- a/esp-hal/src/soc/esp32p4/efuse/fields.rs +++ b/esp-hal/src/soc/esp32p4/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32s2/efuse/fields.rs b/esp-hal/src/soc/esp32s2/efuse/fields.rs index 3afd12f3d93..cf0d2e08fda 100644 --- a/esp-hal/src/soc/esp32s2/efuse/fields.rs +++ b/esp-hal/src/soc/esp32s2/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/esp-hal/src/soc/esp32s3/efuse/fields.rs b/esp-hal/src/soc/esp32s3/efuse/fields.rs index 0bf034071bb..8fa8e7bb81b 100644 --- a/esp-hal/src/soc/esp32s3/efuse/fields.rs +++ b/esp-hal/src/soc/esp32s3/efuse/fields.rs @@ -4,6 +4,9 @@ //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: 2024-03-11 +//! ESP-IDF Commit: 0de2912f use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml index d0a81dd1978..15da2723528 100644 --- a/xtask/Cargo.toml +++ b/xtask/Cargo.toml @@ -6,6 +6,7 @@ publish = false [dependencies] anyhow = "1.0.79" +chrono = "0.4.35" clap = { version = "4.5.0", features = ["derive"] } csv = "1.3.0" env_logger = "0.11.1" diff --git a/xtask/src/lib.rs b/xtask/src/lib.rs index 704618ef86e..e27cc95ac48 100644 --- a/xtask/src/lib.rs +++ b/xtask/src/lib.rs @@ -3,6 +3,7 @@ use std::{ fs::{self, File}, io::Write as _, path::{Path, PathBuf}, + process::Command, }; use anyhow::{bail, Result}; @@ -409,6 +410,9 @@ const EFUSE_FIELDS_RS_HEADER: &str = r#" //! //! For information on how to regenerate these files, please refer to the //! `xtask` package's `README.md` file. +//! +//! Generated on: $DATE +//! ESP-IDF Commit: $HASH use super::EfuseBlock; use crate::soc::efuse_field::EfuseField; @@ -426,12 +430,30 @@ struct EfuseField { /// Generate Rust constants for each eFuse field defined in the given CSV file. pub fn generate_efuse_table( chip: &Chip, - csv_path: impl AsRef, + idf_path: impl AsRef, out_path: impl AsRef, ) -> Result<()> { - let csv_path = csv_path.as_ref(); + let idf_path = idf_path.as_ref(); let out_path = out_path.as_ref(); + // We will put the date of generation in the file header: + let date = chrono::Utc::now().date_naive(); + + // Determine the commit (short) hash of the HEAD commit in the + // provided ESP-IDF repository: + let output = Command::new("git") + .args(&["rev-parse", "HEAD"]) + .current_dir(&idf_path) + .output()?; + let idf_hash = String::from_utf8_lossy(&output.stdout[0..=7]).to_string(); + + // Read the CSV file containing the eFuse field definitions: + let csv_path = idf_path + .join("components") + .join("efuse") + .join(chip.to_string()) + .join("esp_efuse_table.csv"); + // Create the reader and writer from our source and destination file paths: let mut reader = csv::ReaderBuilder::new() .comment(Some(b'#')) @@ -447,6 +469,8 @@ pub fn generate_efuse_table( EFUSE_FIELDS_RS_HEADER .trim_start() .replace("$CHIP", chip.pretty_name()) + .replace("$DATE", &date.to_string()) + .replace("$HASH", &idf_hash) )?; // Build a vector of parsed eFuse fields; we build this vector up first rather diff --git a/xtask/src/main.rs b/xtask/src/main.rs index b9464483981..4c813526e48 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -71,11 +71,11 @@ struct BuildPackageArgs { #[derive(Debug, Args)] struct GenerateEfuseFieldsArgs { + /// Path to the local ESP-IDF repository. + idf_path: PathBuf, /// Chip to build eFuse fields table for. #[arg(value_enum)] chip: Chip, - /// Path to the CSV file containing the eFuse fields. - csv: PathBuf, } #[derive(Debug, Args)] @@ -211,8 +211,7 @@ fn bump_version(workspace: &Path, args: BumpVersionArgs) -> Result<()> { } fn generate_efuse_src(workspace: &Path, args: GenerateEfuseFieldsArgs) -> Result<()> { - // Read the CSV file containing the eFuse field definitions: - let csv_path = args.csv.canonicalize()?; + let idf_path = args.idf_path.canonicalize()?; // Build the path for the generated source file, for the specified chip: let esp_hal = workspace.join("esp-hal"); @@ -225,7 +224,7 @@ fn generate_efuse_src(workspace: &Path, args: GenerateEfuseFieldsArgs) -> Result // Generate the Rust source file from the CSV file, and write it out to // the appropriate path: - xtask::generate_efuse_table(&args.chip, &csv_path, out_path)?; + xtask::generate_efuse_table(&args.chip, &idf_path, out_path)?; // Format the generated code: xtask::cargo::run(&["fmt".into()], &esp_hal)?;