From 81649e503cfbff1ff4b14b8b6c36dfc4f1bd7dac Mon Sep 17 00:00:00 2001 From: DMA Date: Sat, 20 Jul 2019 16:22:43 -0700 Subject: [PATCH] PSoC component update. --- BLE.cydsn/BLE.cycdx | 1612 +---- BLE.cydsn/BLE.cydwr | 5 +- BLE.cydsn/BLE.cyfit | Bin 143086 -> 140116 bytes BLE.cydsn/BLE.cyprj | 38 +- BLE.cydsn/BLE.rpt | 404 +- BLE.cydsn/BLE.svd | 5968 +---------------- BLE.cydsn/BLE_timing.html | 6 +- BLE.cydsn/Export/PSoCCreatorExportIDE.xml | 30 +- BLE.cydsn/Generated_Source/PSoC4/BLE.c | 8 +- BLE.cydsn/Generated_Source/PSoC4/BLE.h | 4 +- .../Generated_Source/PSoC4/BLE_HAL_INT.c | 4 +- .../Generated_Source/PSoC4/BLE_HAL_PVT.c | 27 +- .../Generated_Source/PSoC4/BLE_HAL_PVT.h | 10 +- .../Generated_Source/PSoC4/BLE_STACK_PVT.h | 15 +- BLE.cydsn/Generated_Source/PSoC4/BLE_Stack.h | 4 +- .../Generated_Source/PSoC4/BLE_StackGap.h | 24 +- .../Generated_Source/PSoC4/BLE_StackGatt.h | 4 +- .../PSoC4/BLE_StackGattClient.h | 4 +- .../Generated_Source/PSoC4/BLE_StackGattDb.h | 4 +- .../PSoC4/BLE_StackGattServer.h | 4 +- .../PSoC4/BLE_StackHostMain.h | 4 +- .../Generated_Source/PSoC4/BLE_StackL2cap.h | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_bas.c | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_bas.h | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_dis.c | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_dis.h | 4 +- .../Generated_Source/PSoC4/BLE_eventHandler.c | 86 +- .../Generated_Source/PSoC4/BLE_eventHandler.h | 103 +- BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.c | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.h | 20 +- BLE.cydsn/Generated_Source/PSoC4/BLE_hids.c | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_hids.h | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_scps.c | 4 +- BLE.cydsn/Generated_Source/PSoC4/BLE_scps.h | 4 +- BLE.cydsn/Generated_Source/PSoC4/Cm0Iar.icf | 8 +- .../Generated_Source/PSoC4/Cm0RealView.scat | 10 +- BLE.cydsn/Generated_Source/PSoC4/Cm0Start.c | 2 +- .../Generated_Source/PSoC4/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC4/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC4/CyBootAsmRv.s | 2 +- BLE.cydsn/Generated_Source/PSoC4/CyFlash.c | 2 +- BLE.cydsn/Generated_Source/PSoC4/CyFlash.h | 2 +- BLE.cydsn/Generated_Source/PSoC4/CyLib.c | 88 +- BLE.cydsn/Generated_Source/PSoC4/CyLib.h | 8 +- BLE.cydsn/Generated_Source/PSoC4/cm0gcc.ld | 6 +- .../Generated_Source/PSoC4/core_cm0_psoc4.h | 2 +- BLE.cydsn/Generated_Source/PSoC4/cyPm.c | 26 +- BLE.cydsn/Generated_Source/PSoC4/cyPm.h | 7 +- .../Generated_Source/PSoC4/cydevice_trm.h | 2978 +++----- .../PSoC4/cydevicegnu_trm.inc | 2978 +++----- .../PSoC4/cydeviceiar_trm.inc | 2978 +++----- .../Generated_Source/PSoC4/cydevicerv_trm.inc | 4984 +++----------- BLE.cydsn/Generated_Source/PSoC4/cyfitter.h | 355 +- .../Generated_Source/PSoC4/cyfitter_cfg.c | 16 +- .../Generated_Source/PSoC4/cyfittergnu.inc | 353 +- .../Generated_Source/PSoC4/cyfitteriar.inc | 353 +- .../Generated_Source/PSoC4/cyfitterrv.inc | 353 +- BLE.cydsn/Generated_Source/PSoC4/cymetadata.c | 2 +- BLE.cydsn/Generated_Source/PSoC4/cypins.h | 2 +- BLE.cydsn/Generated_Source/PSoC4/cytypes.h | 16 +- BLE.cydsn/Generated_Source/PSoC4/cyutils.c | 2 +- BLE.cydsn/Generated_Source/PSoC4/project.h | 7 - BLE.cydsn/TopDesign/TopDesign.cysch | Bin 203143 -> 198324 bytes BLE.cydsn/debug.c | 10 +- BLE.cydsn/main.c | 16 +- BLE01_USB.cydsn/BLE01_USB.cydwr | 4 +- .../Generated_Source/PSoC5/Cm3RealView.scat | 2 +- .../Generated_Source/PSoC5/Cm3Start.c | 2 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 2 +- .../Generated_Source/PSoC5/CyDmac.c | 2 +- .../Generated_Source/PSoC5/CyDmac.h | 2 +- .../Generated_Source/PSoC5/CyFlash.c | 2 +- .../Generated_Source/PSoC5/CyFlash.h | 2 +- .../Generated_Source/PSoC5/CyLib.c | 2 +- .../Generated_Source/PSoC5/CyLib.h | 2 +- .../Generated_Source/PSoC5/CySpc.c | 2 +- .../Generated_Source/PSoC5/CySpc.h | 2 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 2 +- BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.c | 2 +- BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.h | 2 +- .../Generated_Source/PSoC5/cypins.h | 2 +- .../Generated_Source/PSoC5/cytypes.h | 2 +- .../Generated_Source/PSoC5/cyutils.c | 2 +- Bootloader.cydsn/Bootloader.cydwr | 4 +- .../Generated_Source/PSoC5/Cm3RealView.scat | 2 +- .../Generated_Source/PSoC5/Cm3Start.c | 2 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 2 +- .../Generated_Source/PSoC5/CyDmac.c | 2 +- .../Generated_Source/PSoC5/CyDmac.h | 2 +- .../Generated_Source/PSoC5/CyFlash.c | 2 +- .../Generated_Source/PSoC5/CyFlash.h | 2 +- .../Generated_Source/PSoC5/CyLib.c | 2 +- .../Generated_Source/PSoC5/CyLib.h | 2 +- .../Generated_Source/PSoC5/CySpc.c | 2 +- .../Generated_Source/PSoC5/CySpc.h | 2 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 2 +- .../Generated_Source/PSoC5/cyPm.c | 2 +- .../Generated_Source/PSoC5/cyPm.h | 2 +- .../Generated_Source/PSoC5/cypins.h | 2 +- .../Generated_Source/PSoC5/cytypes.h | 2 +- .../Generated_Source/PSoC5/cyutils.c | 2 +- CSSK.cydsn/CSSK.cydwr | 4 +- .../Generated_Source/PSoC5/Cm3RealView.scat | 2 +- CSSK.cydsn/Generated_Source/PSoC5/Cm3Start.c | 2 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CyDmac.c | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CyDmac.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CyFlash.c | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CyFlash.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CyLib.c | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CyLib.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CySpc.c | 2 +- CSSK.cydsn/Generated_Source/PSoC5/CySpc.h | 2 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/cyPm.c | 2 +- CSSK.cydsn/Generated_Source/PSoC5/cyPm.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/cypins.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/cytypes.h | 2 +- CSSK.cydsn/Generated_Source/PSoC5/cyutils.c | 2 +- CommonSense.cywrk | 2 +- Firmware.cydsn/Firmware.cydwr | 4 +- .../Generated_Source/PSoC5/Cm3RealView.scat | 2 +- .../Generated_Source/PSoC5/Cm3Start.c | 2 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 2 +- .../Generated_Source/PSoC5/CyDmac.c | 2 +- .../Generated_Source/PSoC5/CyDmac.h | 2 +- .../Generated_Source/PSoC5/CyFlash.c | 2 +- .../Generated_Source/PSoC5/CyFlash.h | 2 +- Firmware.cydsn/Generated_Source/PSoC5/CyLib.c | 2 +- Firmware.cydsn/Generated_Source/PSoC5/CyLib.h | 2 +- Firmware.cydsn/Generated_Source/PSoC5/CySpc.c | 2 +- Firmware.cydsn/Generated_Source/PSoC5/CySpc.h | 2 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 2 +- Firmware.cydsn/Generated_Source/PSoC5/cyPm.c | 2 +- Firmware.cydsn/Generated_Source/PSoC5/cyPm.h | 2 +- .../Generated_Source/PSoC5/cypins.h | 2 +- .../Generated_Source/PSoC5/cytypes.h | 2 +- .../Generated_Source/PSoC5/cyutils.c | 2 +- .../Generated_Source/PSoC5/Cm3RealView.scat | 2 +- .../Generated_Source/PSoC5/Cm3Start.c | 2 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 2 +- .../Generated_Source/PSoC5/CyDmac.c | 2 +- .../Generated_Source/PSoC5/CyDmac.h | 2 +- .../Generated_Source/PSoC5/CyFlash.c | 2 +- .../Generated_Source/PSoC5/CyFlash.h | 2 +- .../Generated_Source/PSoC5/CyLib.c | 2 +- .../Generated_Source/PSoC5/CyLib.h | 2 +- .../Generated_Source/PSoC5/CySpc.c | 2 +- .../Generated_Source/PSoC5/CySpc.h | 2 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 2 +- .../Generated_Source/PSoC5/cyPm.c | 2 +- .../Generated_Source/PSoC5/cyPm.h | 2 +- .../Generated_Source/PSoC5/cypins.h | 2 +- .../Generated_Source/PSoC5/cytypes.h | 2 +- .../Generated_Source/PSoC5/cyutils.c | 2 +- KitProgConverter.cydsn/KitProgConverter.cydwr | 4 +- KitProgConverter.cydsn/KitProgConverter.cyfit | Bin 233647 -> 233647 bytes .../Generated_Source/PSoC5/Cm3RealView.scat | 2 +- XTant.cydsn/Generated_Source/PSoC5/Cm3Start.c | 2 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmIar.s | 2 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 2 +- XTant.cydsn/Generated_Source/PSoC5/CyDmac.c | 2 +- XTant.cydsn/Generated_Source/PSoC5/CyDmac.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/CyFlash.c | 2 +- XTant.cydsn/Generated_Source/PSoC5/CyFlash.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/CyLib.c | 2 +- XTant.cydsn/Generated_Source/PSoC5/CyLib.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/CySpc.c | 2 +- XTant.cydsn/Generated_Source/PSoC5/CySpc.h | 2 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/cyPm.c | 2 +- XTant.cydsn/Generated_Source/PSoC5/cyPm.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/cypins.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/cytypes.h | 2 +- XTant.cydsn/Generated_Source/PSoC5/cyutils.c | 2 +- XTant.cydsn/XTant.cydwr | 4 +- XTant.cydsn/XTant.cyprj | 7 + dma_core/globals.h | 5 + 189 files changed, 5346 insertions(+), 18918 deletions(-) diff --git a/BLE.cydsn/BLE.cycdx b/BLE.cydsn/BLE.cycdx index 52d1473..24d33eb 100644 --- a/BLE.cydsn/BLE.cycdx +++ b/BLE.cydsn/BLE.cycdx @@ -2,1405 +2,26 @@ \ No newline at end of file diff --git a/BLE.cydsn/BLE.cydwr b/BLE.cydsn/BLE.cydwr index 6810093..50d3fcc 100644 --- a/BLE.cydsn/BLE.cydwr +++ b/BLE.cydsn/BLE.cydwr @@ -2,11 +2,11 @@ - + - + @@ -1428,6 +1428,7 @@ + diff --git a/BLE.cydsn/BLE.cyfit b/BLE.cydsn/BLE.cyfit index a4ae63dddc79a35ae86812338ef48896687cf6b7..e311dc515b9ca9f38185b7754b4e5c348e0843a1 100644 GIT binary patch delta 99084 zcmZ6xQ*fY7)GZv_wmGq#Ol;dWCU)|~ww+9D+qP{xnP`%UlkkuGLC%GC@@t8;7-U-X>|PEi?X{hSAYQrT%wm0aqSXmIHwa_l z3YgF!5|}7|sNcjt2axyiL%qWpUj~uu&$AgAzkoHjeBfAt75O6J;<6pxd5`++zO(kP z(6>wO)wCk95BKr+jr@qAVz<{nMj;~q=(CNkdCOw3jdDykVXk*!m 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z#)D)k1A~Gl1A}u;esZ=;er{rBUNO1_2J0hEZee3!h_Xg^(RBj`hJegGbPfGlhc|Br zy4^&8fdObEvUO|Br^hQYiGp2psci2|exS4h5Cel633LE$a>+~&$Ve z$|#deMuy0_9B4sw0Ho2$1zE!xU{rh&m9Mm5WMEhX3|C;VB3mcAboxIy?;f!D(~)1tnnmic+8cMu|xt XBEqi>6gj9dU0az+nT=l?=r;xc5`Dc9 diff --git a/BLE.cydsn/BLE.cyprj b/BLE.cydsn/BLE.cyprj index 9645d6c..fe66105 100644 --- a/BLE.cydsn/BLE.cyprj +++ b/BLE.cydsn/BLE.cyprj @@ -635,34 +635,34 @@ - + - + - + - + - + @@ -675,34 +675,34 @@ - + - + - + - + - + @@ -715,34 +715,34 @@ - + - + - + - + - + @@ -1258,20 +1258,20 @@ - + - + - + @@ -1670,7 +1670,7 @@ - + diff --git a/BLE.cydsn/BLE.rpt b/BLE.cydsn/BLE.rpt index ad8129b..7c84d80 100644 --- a/BLE.cydsn/BLE.rpt +++ b/BLE.cydsn/BLE.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.130ms +Loading plugins phase: Elapsed time ==> 0s.144ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Projects\CommonSense\BLE.cydsn\BLE.cyprj -d CY8C4248LQI-BL583 -s C:\Projects\CommonSense\BLE.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Projects\CommonSense\BLE.cydsn\BLE.cyprj -d CYBLE-014008-00 -s C:\Projects\CommonSense\BLE.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 1s.710ms +Elaboration phase: Elapsed time ==> 2s.144ms -HDL generation phase: Elapsed time ==> 0s.043ms +HDL generation phase: Elapsed time ==> 0s.044ms | | | | | | | @@ -41,7 +41,7 @@ Options : -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -ya -.fftprj=C:\Projects\C ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Sat Aug 04 14:30:21 2018 +Sat Jul 20 16:19:12 2019 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 BLE.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Sat Aug 04 14:30:21 2018 +Sat Jul 20 16:19:12 2019 Flattening file 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v' Flattening file 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v' @@ -84,7 +84,7 @@ Options : -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -ya -.fftprj=C:\Projects\C ====================================================================== tovif V6.3 IR 41: High-level synthesis -Sat Aug 04 14:30:21 2018 +Sat Jul 20 16:19:12 2019 Linking 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -112,7 +112,7 @@ Options : -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -ya -.fftprj=C:\Projects\C ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Sat Aug 04 14:30:21 2018 +Sat Jul 20 16:19:12 2019 Linking 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -135,7 +135,7 @@ Linking 'C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp\lib\lcpsoc3\stdlog Detecting unused logic. ---------------------------------------------------------- User names - Net_54 + Net_56 \BLE:Net_55\ \SCB:Net_1257\ \SCB:uncfg_rx_irq\ @@ -188,9 +188,6 @@ Aliasing \UART_DEB:miso_m_wire\ to \SCB:select_s_wire\ Aliasing \UART_DEB:tmpOE__tx_net_0\ to \SCB:tmpOE__sda_net_0\ Aliasing \UART_DEB:tmpOE__rx_net_0\ to \SCB:tmpOE__sda_net_0\ Aliasing \UART_DEB:cts_wire\ to \SCB:select_s_wire\ -Aliasing tmpOE__LED_BLU_net_0 to \SCB:tmpOE__sda_net_0\ -Aliasing tmpOE__LED_RED_net_0 to \SCB:tmpOE__sda_net_0\ -Aliasing tmpOE__LED_GRN_net_0 to \SCB:tmpOE__sda_net_0\ Aliasing tmpOE__SW2_net_0 to \SCB:tmpOE__sda_net_0\ Removing Lhs of wire \SCB:rx_wire\[11] = \SCB:select_s_wire\[10] Removing Lhs of wire \SCB:Net_1170\[14] = \SCB:Net_847\[9] @@ -210,13 +207,10 @@ Removing Lhs of wire \UART_DEB:miso_m_wire\[70] = zero[20] Removing Lhs of wire \UART_DEB:tmpOE__tx_net_0\[72] = one[24] Removing Lhs of wire \UART_DEB:tmpOE__rx_net_0\[81] = one[24] Removing Lhs of wire \UART_DEB:cts_wire\[85] = zero[20] -Removing Lhs of wire tmpOE__LED_BLU_net_0[112] = one[24] -Removing Lhs of wire tmpOE__LED_RED_net_0[118] = one[24] -Removing Lhs of wire tmpOE__LED_GRN_net_0[124] = one[24] -Removing Lhs of wire tmpOE__SW2_net_0[132] = one[24] +Removing Lhs of wire tmpOE__SW2_net_0[114] = one[24] ------------------------------------------------------ -Aliased 0 equations, 22 wires. +Aliased 0 equations, 19 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -240,11 +234,11 @@ CYPRESS_DIR : C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp Warp Program : C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe Warp Arguments : -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -ya -.fftprj=C:\Projects\CommonSense\BLE.cydsn\BLE.cyprj -dcpsoc3 BLE.v -verilog -Warp synthesis phase: Elapsed time ==> 0s.313ms +Warp synthesis phase: Elapsed time ==> 0s.352ms -cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Saturday, 04 August 2018 14:30:22 -Options: -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -ya -.fftprj=C:\Projects\CommonSense\BLE.cydsn\BLE.cyprj -d CY8C4248LQI-BL583 BLE.v -verilog +cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Saturday, 20 July 2019 16:19:12 +Options: -yv2 -q10 -ygs -o2 -v11 -.fftcfgtype=LE -ya -.fftprj=C:\Projects\CommonSense\BLE.cydsn\BLE.cyprj -d CYBLE-014008-00 BLE.v -verilog Design parsing phase: Elapsed time ==> 0s.009ms @@ -258,6 +252,8 @@ Assigning clock BLE_LFCLK to clock LFClk because it is a pass-through +ADD: pft.M0040: information: The following 1 pin(s) will be assigned a location by the fitter: SW2(0) + Removing unused cells resulting from optimization Done removing unused cells. @@ -437,123 +433,6 @@ Design Equations { } - Pin : Name = LED_BLU(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO Multiplier Index: 0 - SIO RefSel: VCC_IO - Required Capabilities: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => LED_BLU(0)__PA , - pad => LED_BLU(0)_PAD ); - Properties: - { - } - - Pin : Name = LED_RED(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO Multiplier Index: 0 - SIO RefSel: VCC_IO - Required Capabilities: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => LED_RED(0)__PA , - pad => LED_RED(0)_PAD ); - Properties: - { - } - - Pin : Name = LED_GRN(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO Multiplier Index: 0 - SIO RefSel: VCC_IO - Required Capabilities: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => LED_GRN(0)__PA , - pad => LED_GRN(0)_PAD ); - Properties: - { - } - Pin : Name = SW2(0) Attributes: In Group/Port: True @@ -589,9 +468,6 @@ Design Equations PORT MAP ( pa_out => SW2(0)__PA , pad => SW2(0)_PAD ); - Properties: - { - } @@ -653,13 +529,12 @@ Resource Type : Used : Free : Max : % Used ============================================================ Digital Clocks : 0 : 4 : 4 : 0.00 % Interrupts : 3 : 29 : 32 : 9.38 % -IO : 12 : 26 : 38 : 31.58 % +IO : 7 : 20 : 27 : 25.93 % Segment LCD : 0 : 1 : 1 : 0.00 % CapSense : 0 : 1 : 1 : 0.00 % Die Temp : 0 : 1 : 1 : 0.00 % Serial Communication (SCB) : 2 : 0 : 2 : 100.00 % BLE : 1 : 0 : 1 : 100.00 % -DMA Channels : 0 : 8 : 8 : 0.00 % Timer/Counter/PWM : 0 : 4 : 4 : 0.00 % UDB : : : : Macrocells : 0 : 32 : 32 : 0.00 % @@ -669,14 +544,14 @@ UDB : : : : Status Cells : 0 : 4 : 4 : 0.00 % Control Cells : 0 : 4 : 4 : 0.00 % Comparator/Opamp : 0 : 4 : 4 : 0.00 % -LP Comparator : 0 : 2 : 2 : 0.00 % +LP Comparator : 0 : 1 : 1 : 0.00 % SAR ADC : 0 : 1 : 1 : 0.00 % DAC : : : : 7-bit IDAC : 0 : 1 : 1 : 0.00 % 8-bit IDAC : 0 : 1 : 1 : 0.00 % -Technology Mapping: Elapsed time ==> 0s.027ms -Tech Mapping phase: Elapsed time ==> 0s.046ms +Technology Mapping: Elapsed time ==> 0s.022ms +Tech Mapping phase: Elapsed time ==> 0s.043ms @@ -688,25 +563,22 @@ Cell : Block \SCB:scl(0)\ : [IOP=(3)][IoId=(5)] \UART_DEB:tx(0)\ : [IOP=(1)][IoId=(5)] \UART_DEB:rx(0)\ : [IOP=(1)][IoId=(4)] -LED_BLU(0) : [IOP=(3)][IoId=(7)] -LED_RED(0) : [IOP=(2)][IoId=(6)] -LED_GRN(0) : [IOP=(3)][IoId=(6)] -SW2(0) : [IOP=(2)][IoId=(7)] ClockGenBlock : CLK_GEN_[FFB(CLK_GEN,0)] \BLE:cy_m0s8_ble\ : BLE_[FFB(BLE,0)] \SCB:SCB\ : SCB_[FFB(SCB,1)] \UART_DEB:SCB\ : SCB_[FFB(SCB,0)] +SW2(0) : [IOP=(0)][IoId=(1)] -Elapsed time ==> 0.1437338s +Elapsed time ==> 0.1042345s -Analog Placement phase: Elapsed time ==> 0s.325ms +Analog Placement phase: Elapsed time ==> 0s.266ms -Route success=True, Iterations=1 Elapsed=0.0007094 secs +Route success=True, Iterations=1 Elapsed=0.0007472 secs Analog Routing phase: Elapsed time ==> 0s.000ms @@ -738,7 +610,7 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.008ms +Partitioning: Elapsed time ==> 0s.007ms @@ -760,7 +632,7 @@ UDB [UDB=(0,1)] is empty. UDB [UDB=(1,0)] is empty. UDB [UDB=(1,1)] is empty. Intr container @ [IntrContainer=(0)]: - Intr@ [IntrContainer=(0)][IntrId=(2)] + Intr@ [IntrContainer=(0)][IntrId=(0)] interrupt: Name =Wakeup_Interrupt PORT MAP ( interrupt => Net_27 ); @@ -787,92 +659,7 @@ Intr container @ [IntrContainer=(0)]: int_type = "10" is_nmi = 0 } -Drq container @ [DrqContainer=(0)]: empty -Port 0 contains the following IO cells: -Port 1 contains the following IO cells: -[IoId=4]: -Pin : Name = \UART_DEB:rx(0)\ - Attributes: - In Group/Port: True - In Sync Option: NOSYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: HI_Z_DIGITAL - VTrip: CMOS - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO Multiplier Index: 0 - SIO RefSel: VCC_IO - Required Capabilities: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => \UART_DEB:rx(0)\__PA , - fb => \UART_DEB:rx_wire\ , - pad => \UART_DEB:rx(0)_PAD\ ); - Properties: - { - } - -[IoId=5]: -Pin : Name = \UART_DEB:tx(0)\ - Attributes: - In Group/Port: True - In Sync Option: NOSYNC - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: CMOS - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO Multiplier Index: 0 - SIO RefSel: VCC_IO - Required Capabilities: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => \UART_DEB:tx(0)\__PA , - pin_input => \UART_DEB:tx_wire\ , - pad => \UART_DEB:tx(0)_PAD\ ); - Properties: - { - } - -Port 2 generates interrupt for logical port: +Port 0 generates interrupt for logical port: logicalport: Name =SW2 PORT MAP ( in_clock_en => one , @@ -939,47 +726,7 @@ Port 2 generates interrupt for logical port: width = 1 } and contains the following IO cells: -[IoId=6]: -Pin : Name = LED_RED(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO Multiplier Index: 0 - SIO RefSel: VCC_IO - Required Capabilities: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => LED_RED(0)__PA , - pad => LED_RED(0)_PAD ); - Properties: - { - } - -[IoId=7]: +[IoId=1]: Pin : Name = SW2(0) Attributes: In Group/Port: True @@ -1019,16 +766,16 @@ Pin : Name = SW2(0) { } -Port 3 contains the following IO cells: +Port 1 contains the following IO cells: [IoId=4]: -Pin : Name = \SCB:sda(0)\ +Pin : Name = \UART_DEB:rx(0)\ Attributes: In Group/Port: True In Sync Option: NOSYNC - Out Sync Option: NOSYNC + Out Sync Option: AUTO Interrupt generated: False Interrupt mode: NONE - Drive mode: OPEN_DRAIN_LO + Drive mode: HI_Z_DIGITAL VTrip: CMOS Slew: FAST Input Sync needed: False @@ -1051,25 +798,25 @@ Pin : Name = \SCB:sda(0)\ SIO Multiplier Index: 0 SIO RefSel: VCC_IO Required Capabilities: DIGITAL - Initial Value: 1 + Initial Value: 0 IO Voltage: 0 PORT MAP ( - pa_out => \SCB:sda(0)\__PA , - fb => Net_23 , - pad => \SCB:sda(0)_PAD\ ); + pa_out => \UART_DEB:rx(0)\__PA , + fb => \UART_DEB:rx_wire\ , + pad => \UART_DEB:rx(0)_PAD\ ); Properties: { } [IoId=5]: -Pin : Name = \SCB:scl(0)\ +Pin : Name = \UART_DEB:tx(0)\ Attributes: In Group/Port: True In Sync Option: NOSYNC Out Sync Option: NOSYNC Interrupt generated: False Interrupt mode: NONE - Drive mode: OPEN_DRAIN_LO + Drive mode: CMOS_OUT VTrip: CMOS Slew: FAST Input Sync needed: False @@ -1095,23 +842,25 @@ Pin : Name = \SCB:scl(0)\ Initial Value: 1 IO Voltage: 0 PORT MAP ( - pa_out => \SCB:scl(0)\__PA , - fb => Net_22 , - pad => \SCB:scl(0)_PAD\ ); + pa_out => \UART_DEB:tx(0)\__PA , + pin_input => \UART_DEB:tx_wire\ , + pad => \UART_DEB:tx(0)_PAD\ ); Properties: { } -[IoId=6]: -Pin : Name = LED_GRN(0) +Port 2 contains the following IO cells: +Port 3 contains the following IO cells: +[IoId=4]: +Pin : Name = \SCB:sda(0)\ Attributes: In Group/Port: True - In Sync Option: AUTO + In Sync Option: NOSYNC Out Sync Option: NOSYNC Interrupt generated: False Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER + Drive mode: OPEN_DRAIN_LO + VTrip: CMOS Slew: FAST Input Sync needed: False Output Sync needed: False @@ -1136,22 +885,23 @@ Pin : Name = LED_GRN(0) Initial Value: 1 IO Voltage: 0 PORT MAP ( - pa_out => LED_GRN(0)__PA , - pad => LED_GRN(0)_PAD ); + pa_out => \SCB:sda(0)\__PA , + fb => Net_23 , + pad => \SCB:sda(0)_PAD\ ); Properties: { } -[IoId=7]: -Pin : Name = LED_BLU(0) +[IoId=5]: +Pin : Name = \SCB:scl(0)\ Attributes: In Group/Port: True - In Sync Option: AUTO + In Sync Option: NOSYNC Out Sync Option: NOSYNC Interrupt generated: False Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER + Drive mode: OPEN_DRAIN_LO + VTrip: CMOS Slew: FAST Input Sync needed: False Output Sync needed: False @@ -1176,15 +926,14 @@ Pin : Name = LED_BLU(0) Initial Value: 1 IO Voltage: 0 PORT MAP ( - pa_out => LED_BLU(0)__PA , - pad => LED_BLU(0)_PAD ); + pa_out => \SCB:scl(0)\__PA , + fb => Net_22 , + pad => \SCB:scl(0)_PAD\ ); Properties: { } Port 4 contains the following IO cells: -Port 5 contains the following IO cells: -Port 6 contains the following IO cells: ARM group 0: empty Clock group 0: Clock Block @ F(Clock,0): @@ -1275,7 +1024,7 @@ BLE group 0: p4blecell: Name =\BLE:cy_m0s8_ble\ PORT MAP ( interrupt => \BLE:Net_15\ , - rfctrl_extpa_en => Net_55 ); + rfctrl_extpa_en => Net_57 ); Properties: { cy_registers = "" @@ -1293,48 +1042,45 @@ Port Configuration report ------------------------------------------------------------ | | | Interrupt | | | Port | Pin | Fixed | Type | Drive Mode | Name | Connections +-----+-----+-------+-----------+------------------+------------------+----------------------- + 0 | 1 | | FALLING | RES_PULL_UP | SW2(0) | -----+-----+-------+-----------+------------------+------------------+----------------------- 1 | 4 | * | NONE | HI_Z_DIGITAL | \UART_DEB:rx(0)\ | FB(\UART_DEB:rx_wire\) | 5 | * | NONE | CMOS_OUT | \UART_DEB:tx(0)\ | In(\UART_DEB:tx_wire\) ------+-----+-------+-----------+------------------+------------------+----------------------- - 2 | 6 | * | NONE | CMOS_OUT | LED_RED(0) | - | 7 | * | FALLING | RES_PULL_UP | SW2(0) | -----+-----+-------+-----------+------------------+------------------+----------------------- 3 | 4 | * | NONE | OPEN_DRAIN_LO | \SCB:sda(0)\ | FB(Net_23) | 5 | * | NONE | OPEN_DRAIN_LO | \SCB:scl(0)\ | FB(Net_22) - | 6 | * | NONE | CMOS_OUT | LED_GRN(0) | - | 7 | * | NONE | CMOS_OUT | LED_BLU(0) | --------------------------------------------------------------------------------------------- -Digital component placer commit/Report: Elapsed time ==> 0s.014ms -Digital Placement phase: Elapsed time ==> 0s.498ms +Digital component placer commit/Report: Elapsed time ==> 0s.020ms +Digital Placement phase: Elapsed time ==> 0s.440ms -"C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\dev\psoc4/3/256dma/route_arch-rrg.cydata" --vh2-path "BLE_r.vh2" --pcf-path "BLE.pco" --des-name "BLE" --dsf-path "BLE.dsf" --sdc-path "BLE.sdc" --lib-path "BLE_r.lib" +"C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\P\PSoC_Creator\PSoC Creator\4.2\PSoC Creator\dev\psoc4/3/128k/route_arch-rrg.cydata" --vh2-path "BLE_r.vh2" --pcf-path "BLE.pco" --des-name "BLE" --dsf-path "BLE.dsf" --sdc-path "BLE.sdc" --lib-path "BLE_r.lib" Routing successful. -Digital Routing phase: Elapsed time ==> 0s.538ms +Digital Routing phase: Elapsed time ==> 0s.534ms -Bitstream Generation phase: Elapsed time ==> 0s.196ms +Bitstream Generation phase: Elapsed time ==> 0s.199ms -Bitstream Verification phase: Elapsed time ==> 0s.018ms +Bitstream Verification phase: Elapsed time ==> 0s.019ms Timing report is in BLE_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.146ms +Static timing analysis phase: Elapsed time ==> 0s.132ms -Data reporting phase: Elapsed time ==> 0s.120ms +Data reporting phase: Elapsed time ==> 0s.128ms -Design database save phase: Elapsed time ==> 0s.145ms +Design database save phase: Elapsed time ==> 0s.149ms -cydsfit: Elapsed time ==> 2s.078ms +cydsfit: Elapsed time ==> 1s.958ms -Fitter phase: Elapsed time ==> 2s.079ms -API generation phase: Elapsed time ==> 1s.950ms -Dependency generation phase: Elapsed time ==> 0s.014ms +Fitter phase: Elapsed time ==> 1s.959ms +API generation phase: Elapsed time ==> 2s.067ms +Dependency generation phase: Elapsed time ==> 0s.010ms Cleanup phase: Elapsed time ==> 0s.000ms diff --git a/BLE.cydsn/BLE.svd b/BLE.cydsn/BLE.svd index d5e4737..ebe096b 100644 --- a/BLE.cydsn/BLE.svd +++ b/BLE.cydsn/BLE.svd @@ -1,5799 +1,13 @@ - CY8C4248LQI_BL583 + CYBLE_014008_00 0.1 PSoC 4200 BLE 8 32 - DMAC - DMAC Registers - 0x0 - - 0 - 0x0 - registers - - - - DMAC_CTL - DMA controller control register - 0x40101000 - 32 - read-write - 0 - 0 - - - ENABLED - Global DMAC enable - 31 - 31 - read-write - - - Disabled - DMA controller is disabled. - 0 - - - Enabled - DMA controller is enabled. - 1 - - - - - - - DMAC_STATUS - DMA controller status register - 0x40101010 - 32 - read-write - 0 - 0 - - - DATA_NR - Specifies the index of the currently active data transfer. This value increases from '0' to the DATA_NR field specified of the currently active descriptor control word. - 0 - 15 - read-only - - - CH_ADDR - Specifies the channel number of the currently active channel. For example, if channel 7 is active, DMAC_STATUS.ACTIVE is '1' and STATUS.CH_ADDR is '7'. - 16 - 20 - read-only - - - STATE - State of the data transfer engine. - 24 - 26 - read-only - - - IDLE - Idle state when the DMA is not active. - 0 - - - LOAD_DESCR - The DMA is loading the descriptor to the DMA transfer engine. - 1 - - - LOAD_SRC - The DMA is getting the value from the source location. - 2 - - - STORE_DST - The DMA is storing the value at the destination location. - 3 - - - STORE_DESCR - The DMA is updating the descriptors after completion of transfer. - 4 - - - WAIT_TRIG_DEACT - The DMA is waiting for the level sensitive trigger to deactivate. - 5 - - - STORE_ERROR - There was an error during the transaction and the DMA is writing the error code to the channel status register. - 6 - - - - - PRIO - Specifies the priority of the currently active channel. - 28 - 29 - read-only - - - PING_PONG - Specifies whether the PING descriptor ('0') or PONG descriptor ('1') of the channel is currently in use. - 31 - 31 - read-only - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - ACTIVE - Specifies if there is a currently active (pending) channel in the data transfer engine. - 31 - 31 - read-only - - - IDLE - No currently active channel. - 0 - - - ACTIVE - Currently active channel. - 1 - - - - - - - DMAC_STATUS_SRC_ADDR - Source address currently being used by the DMA controller - 0x40101014 - 32 - read-write - 0 - 0 - - - ADDR - The source address currently being used by the DMA transfer engine. This field is provided for debug purposes. Note while reading the DMAC_STATUS, DMAC_STATUS_SRC_ADDR and DMAC_STATUS_DST_ADDR registers, the transfer engine may have advanced after one or more of these reads. Meaning the register values may not be related to each other. - 0 - 31 - read-only - - - - - DMAC_STATUS_DST_ADDR - Destination address currently being used by the DMA controller - 0x40101018 - 32 - read-write - 0 - 0 - - - ADDR - The destination address currently being used by the DMA transfer engine. This field is provided for debug purposes. Note while reading the DMAC_STATUS, DMAC_STATUS_SRC_ADDR and DMAC_STATUS_DST_ADDR registers, the transfer engine may have advanced after one or more of these reads. Meaning the register values may not be related to each other. - 0 - 31 - read-only - - - - - DMAC_STATUS_CH_ACT - Channel activation status - 0x4010101C - 32 - read-write - 0 - 0 - - - CH - Channel activation status. Bit i is associated to channel i. Software reads this field to get information on all actively pending channels (either in pending or in the data transfer engine). - 0 - 31 - read-only - - - - - DMAC_CH_CTL0 - DMA channel 0 control register - 0x40101080 - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL1 - DMA channel 1 control register - 0x40101084 - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL2 - DMA channel 2 control register - 0x40101088 - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL3 - DMA channel 3 control register - 0x4010108C - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL4 - DMA channel 4 control register - 0x40101090 - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL5 - DMA channel 5 control register - 0x40101094 - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL6 - DMA channel 6 control register - 0x40101098 - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_CH_CTL7 - DMA channel 7 control register - 0x4010109C - 32 - read-write - 0 - 0 - - - ENABLED - Channel enable control. - 31 - 31 - read-write - - - Disabled - Channel is currently disabled. - 0 - - - Enabled - Channel is currently enabled. - 1 - - - - - PING_PONG - Identifies the descriptor structure that is currently in use by the DMA controller. - 30 - 30 - read-write - - - DESCR0 - Descriptor 0 (PING) is currently in use. - 0 - - - DESCR1 - Descriptor 1 (PONG) is currently in use. - 1 - - - - - PRIO - Channel priority. Priority can be 0,1,2 or 3. 0 is the highest. - 28 - 29 - read-write - - - - - DMAC_INTR - Interrupt register - 0x401017F0 - 32 - read-write - 0 - 0 - - - CH - Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. - 0 - 31 - read-write - - - - - DMAC_INTR_SET - Interrupt set register - 0x401017F4 - 32 - read-write - 0 - 0 - - - CH - Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). - 0 - 31 - read-write - - - - - DMAC_INTR_MASK - Interrupt mask register - 0x401017F8 - 32 - read-write - 0 - 0 - - - CH - Mask for corresponding field in INTR register. - 0 - 31 - read-write - - - - - DMAC_INTR_MASKED - Interrupt masked register - 0x401017FC - 32 - read-write - 0 - 0 - - - CH - Bitwise AND between the interrupt reguest (INTR) and mask (INTR_MASK) registers. - 0 - 31 - read-only - - - - - DMAC_DESCR0_PING_SRC - Descriptor 0 source address location for channel 0 - 0x40101800 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR0_PING_DST - Descriptor 0 destination address location for channel 0 - 0x40101804 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR0_PING_CTL - Descriptor 0 control register for channel 0 - 0x40101808 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR0_PING_STATUS - Descriptor 0 status register for channel 0 - 0x4010180C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR0_PONG_SRC - Descriptor 1 source address location for channel 0 - 0x40101810 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR0_PONG_DST - Descriptor 1 destination address location for channel 0 - 0x40101814 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR0_PONG_CTL - Descriptor 1 control register for channel 0 - 0x40101818 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR0_PONG_STATUS - Descriptor 1 status register for channel 0 - 0x4010181C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR1_PING_SRC - Descriptor 0 source address location for channel 1 - 0x40101820 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR1_PING_DST - Descriptor 0 destination address location for channel 1 - 0x40101824 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR1_PING_CTL - Descriptor 0 control register for channel 1 - 0x40101828 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR1_PING_STATUS - Descriptor 0 status register for channel 1 - 0x4010182C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR1_PONG_SRC - Descriptor 1 source address location for channel 1 - 0x40101830 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR1_PONG_DST - Descriptor 1 destination address location for channel 1 - 0x40101834 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR1_PONG_CTL - Descriptor 1 control register for channel 1 - 0x40101838 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR1_PONG_STATUS - Descriptor 1 status register for channel 1 - 0x4010183C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR2_PING_SRC - Descriptor 0 source address location for channel 2 - 0x40101840 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR2_PING_DST - Descriptor 0 destination address location for channel 2 - 0x40101844 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR2_PING_CTL - Descriptor 0 control register for channel 2 - 0x40101848 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR2_PING_STATUS - Descriptor 0 status register for channel 2 - 0x4010184C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR2_PONG_SRC - Descriptor 1 source address location for channel 2 - 0x40101850 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR2_PONG_DST - Descriptor 1 destination address location for channel 2 - 0x40101854 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR2_PONG_CTL - Descriptor 1 control register for channel 2 - 0x40101858 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR2_PONG_STATUS - Descriptor 1 status register for channel 2 - 0x4010185C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR3_PING_SRC - Descriptor 0 source address location for channel 3 - 0x40101860 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR3_PING_DST - Descriptor 0 destination address location for channel 3 - 0x40101864 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR3_PING_CTL - Descriptor 0 control register for channel 3 - 0x40101868 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR3_PING_STATUS - Descriptor 0 status register for channel 3 - 0x4010186C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR3_PONG_SRC - Descriptor 1 source address location for channel 3 - 0x40101870 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR3_PONG_DST - Descriptor 1 destination address location for channel 3 - 0x40101874 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR3_PONG_CTL - Descriptor 1 control register for channel 3 - 0x40101878 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR3_PONG_STATUS - Descriptor 1 status register for channel 3 - 0x4010187C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR4_PING_SRC - Descriptor 0 source address location for channel 4 - 0x40101880 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR4_PING_DST - Descriptor 0 destination address location for channel 4 - 0x40101884 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR4_PING_CTL - Descriptor 0 control register for channel 4 - 0x40101888 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR4_PING_STATUS - Descriptor 0 status register for channel 4 - 0x4010188C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR4_PONG_SRC - Descriptor 1 source address location for channel 4 - 0x40101890 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR4_PONG_DST - Descriptor 1 destination address location for channel 4 - 0x40101894 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR4_PONG_CTL - Descriptor 1 control register for channel 4 - 0x40101898 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR4_PONG_STATUS - Descriptor 1 status register for channel 4 - 0x4010189C - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR5_PING_SRC - Descriptor 0 source address location for channel 5 - 0x401018A0 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR5_PING_DST - Descriptor 0 destination address location for channel 5 - 0x401018A4 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR5_PING_CTL - Descriptor 0 control register for channel 5 - 0x401018A8 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR5_PING_STATUS - Descriptor 0 status register for channel 5 - 0x401018AC - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR5_PONG_SRC - Descriptor 1 source address location for channel 5 - 0x401018B0 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR5_PONG_DST - Descriptor 1 destination address location for channel 5 - 0x401018B4 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR5_PONG_CTL - Descriptor 1 control register for channel 5 - 0x401018B8 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR5_PONG_STATUS - Descriptor 1 status register for channel 5 - 0x401018BC - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR6_PING_SRC - Descriptor 0 source address location for channel 6 - 0x401018C0 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR6_PING_DST - Descriptor 0 destination address location for channel 6 - 0x401018C4 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR6_PING_CTL - Descriptor 0 control register for channel 6 - 0x401018C8 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR6_PING_STATUS - Descriptor 0 status register for channel 6 - 0x401018CC - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR6_PONG_SRC - Descriptor 1 source address location for channel 6 - 0x401018D0 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR6_PONG_DST - Descriptor 1 destination address location for channel 6 - 0x401018D4 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR6_PONG_CTL - Descriptor 1 control register for channel 6 - 0x401018D8 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR6_PONG_STATUS - Descriptor 1 status register for channel 6 - 0x401018DC - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR7_PING_SRC - Descriptor 0 source address location for channel 7 - 0x401018E0 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR7_PING_DST - Descriptor 0 destination address location for channel 7 - 0x401018E4 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR7_PING_CTL - Descriptor 0 control register for channel 7 - 0x401018E8 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR7_PING_STATUS - Descriptor 0 status register for channel 7 - 0x401018EC - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - DMAC_DESCR7_PONG_SRC - Descriptor 1 source address location for channel 7 - 0x401018F0 - 32 - read-write - 0 - 0 - - - SRC - Source address. - 0 - 31 - read-write - - - - - DMAC_DESCR7_PONG_DST - Descriptor 1 destination address location for channel 7 - 0x401018F4 - 32 - read-write - 0 - 0 - - - DST - Destination address. - 0 - 31 - read-write - - - - - DMAC_DESCR7_PONG_CTL - Descriptor 1 control register for channel 7 - 0x401018F8 - 32 - read-write - 0 - 0 - - - DATA_NR - Number of data elements this descriptor transfers. A value of N results in a transfer of N+1 data elements. - 0 - 15 - read-write - - - DATA_SIZE - Specifies the data element size. - 16 - 17 - read-write - - - BYTE - 1 byte. - 0 - - - HALFWORD - Halfword (2 bytes). - 1 - - - WORD - Word (4 bytes). - 2 - - - - - DST_TRANSFER_SIZE - Specifies the bus transfer size to the destination location. - 20 - 20 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - DST_ADDR_INCR - Specifies whether the destination address is incremented by the DST_TRANSFER_SIZE after the transfer of each data element. - 21 - 21 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_DST_ADDR - Increment the destination address. - 1 - - - - - SRC_TRANSFER_SIZE - Specifies the bus transfer size to the source location. - 22 - 22 - read-write - - - DATA_SIZE - As specified by DATA_SIZE field. - 0 - - - WORD - Word (4 bytes). - 1 - - - - - SRC_ADDR_INCR - Specifies whether the source address is incremented by the SRC_TRANSFER_SIZE after the transfer of each data element. - 23 - 23 - read-write - - - INC_NONE - No address increment. - 0 - - - INC_SRC_ADDR - Increment the source address. - 1 - - - - - WAIT_FOR_DEACT - Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. - 24 - 25 - read-write - - - PULSE - Do not wait for de-activation (for pulse sensitive triggers). - 0 - - - LEVEL_FOUR - Wait for up to 4 cycles. - 1 - - - LEVEL_EIGHT - Wait for up to 8 cycles. - 2 - - - LEVEL_UNKNOWN - Wait indefinitely. This option may result in DMA controller lockup if the system trigger is not de-activated by the source agent. - 3 - - - - - INV_DESCR - If set, the VALID bit of the descriptor's STATUS word is set to '0' on completion of the current descriptor structure. - 26 - 26 - read-write - - - SET_CAUSE - If set, the interrupt bit of the channel is set to '1' on completion of the current descriptor structure. - 27 - 27 - read-write - - - PREEMPTABLE - If set, the transfer is preemptable. Multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. - 28 - 28 - read-write - - - FLIPPING - If set, on completion of the current descriptor structure, the current descriptor identifier is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. - 29 - 29 - read-write - - - OPCODE - Specifies how the DMA reacts to a trigger event. - 30 - 31 - read-write - - - SINGLE_DATA_ELEMENT - A single trigger initiates a single data element transfer. This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). - 0 - - - ENTIRE_DESCRIPTOR - A single trigger initiates an entire descriptor transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. - 1 - - - ENTIRE_DESCRIPTOR_CHAIN - A single trigger initiates a descriptor list transfer. This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). - 2 - - - - - - - DMAC_DESCR7_PONG_STATUS - Descriptor 1 status register for channel 7 - 0x401018FC - 32 - read-write - 0 - 0 - - - VALID - Descriptor validity status. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. - 31 - 31 - read-write - - - INVALID - Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code and the interrupt cause bit is set to '1'. - 0 - - - VALID - Valid. - 1 - - - - - RESONSE - Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). - 16 - 18 - read-write - - - NO_ERROR - No error. Setting this response does NOT set the interrupt bit to '1'. STATUS.VALID is NOT affected. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. - 0 - - - DONE - Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHx_CTL.ENABLED is NOT affected. CHx_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. - 1 - - - SRC_BUS_ERROR - Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 2 - - - DST_BUS_ERROR - Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '1'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 3 - - - SRC_MISAL - Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 4 - - - DST_MISAL - Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 5 - - - INVALID - Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHx_CTL.ENABLED is set to '0'. CHx_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). - 6 - - - - - CURR_DATA_NR - Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: ? - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. ? - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. ? - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. ? HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. ? This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. - 0 - 15 - read-write - - - - - - - UART_DEB + SCB Serial Communication Block 0x0 @@ -5805,7 +19,7 @@ Cy_CTRL Generic control register - 0x40240000 + 0x40250000 32 read-write 0 @@ -5879,7 +93,7 @@ Cy_SPI_CTRL SPI control register - 0x40240020 + 0x40250020 32 read-write 0 @@ -5988,7 +202,7 @@ Cy_SPI_STATUS SPI status register - 0x40240024 + 0x40250024 32 read-write 0 @@ -6006,7 +220,7 @@ Cy_UART_CTRL UART control register - 0x40240040 + 0x40250040 32 read-write 0 @@ -6031,7 +245,7 @@ Cy_UART_TX_CTRL UART transmitter control register - 0x40240044 + 0x40250044 32 read-write 0 @@ -6070,7 +284,7 @@ Cy_UART_RX_CTRL UART receiver control register - 0x40240048 + 0x40250048 32 read-write 0 @@ -6151,7 +365,7 @@ Cy_UART_FLOW_CTRL UART flow control register - 0x40240050 + 0x40250050 32 read-write 0 @@ -6190,7 +404,7 @@ Cy_I2C_CTRL I2C control register - 0x40240060 + 0x40250060 32 read-write 0 @@ -6285,7 +499,7 @@ Cy_I2C_STATUS I2C status register - 0x40240064 + 0x40250064 32 read-write 0 @@ -6317,7 +531,7 @@ Cy_I2C_M_CMD I2C master command register - 0x40240068 + 0x40250068 32 read-write 0 @@ -6363,7 +577,7 @@ Cy_I2C_S_CMD I2C slave command register - 0x4024006C + 0x4025006C 32 read-write 0 @@ -6388,7 +602,7 @@ Cy_I2C_CFG I2C fitler trimm register - 0x40240070 + 0x40250070 32 read-write 0 @@ -6455,7 +669,7 @@ Cy_TX_CTRL Transmitter control register - 0x40240200 + 0x40250200 32 read-write 0 @@ -6480,7 +694,7 @@ Cy_TX_FIFO_CTRL Transmitter FIFO control register - 0x40240204 + 0x40250204 32 read-write 0 @@ -6512,7 +726,7 @@ Cy_TX_FIFO_STATUS Transmitter FIFO status register - 0x40240208 + 0x40250208 32 read-write 0 @@ -6551,7 +765,7 @@ Cy_TX_FIFO_WR Transmitter FIFO write register - 0x40240240 + 0x40250240 32 read-write 0 @@ -6569,7 +783,7 @@ Cy_RX_CTRL Receiver control register - 0x40240300 + 0x40250300 32 read-write 0 @@ -6601,7 +815,7 @@ Cy_RX_FIFO_CTRL Receiver FIFO control register - 0x40240304 + 0x40250304 32 read-write 0 @@ -6633,7 +847,7 @@ Cy_RX_FIFO_STATUS Receiver FIFO status registerS - 0x40240308 + 0x40250308 32 read-write 0 @@ -6672,7 +886,7 @@ Cy_RX_MATCH Slave address and mask register - 0x40240310 + 0x40250310 32 read-write 0 @@ -6697,7 +911,7 @@ Cy_RX_FIFO_RD Receiver FIFO read register - 0x40240340 + 0x40250340 32 read-write 0 @@ -6715,7 +929,7 @@ Cy_INTR_CAUSE Interrupt cause register - 0x40240E00 + 0x40250E00 32 read-write 0 @@ -6768,7 +982,7 @@ Cy_INTR_I2C_EC Externally clocked I2C interrupt request register - 0x40240E80 + 0x40250E80 32 read-write 0 @@ -6786,7 +1000,7 @@ Cy_INTR_I2C_EC_MASK Externally clocked I2C interrupt mask register - 0x40240E88 + 0x40250E88 32 read-write 0 @@ -6804,7 +1018,7 @@ Cy_INTR_I2C_EC_MASKED Externally clocked SPI interrupt masked register - 0x40240E8C + 0x40250E8C 32 read-write 0 @@ -6822,7 +1036,7 @@ Cy_INTR_INTR_SPI_EC Externally clocked SPI interrupt request register - 0x40240EC0 + 0x40250EC0 32 read-write 0 @@ -6840,7 +1054,7 @@ Cy_INTR_INTR_SPI_EC_MASK Externally clocked SPI interrupt mask register - 0x40240EC8 + 0x40250EC8 32 read-write 0 @@ -6858,7 +1072,7 @@ Cy_INTR_INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked register - 0x40240ECC + 0x40250ECC 32 read-write 0 @@ -6876,7 +1090,7 @@ Cy_INTR_M Master interrupt request register. - 0x40240F00 + 0x40250F00 32 read-write 0 @@ -6929,7 +1143,7 @@ Cy_INTR_M_SET Master interrupt set request register - 0x40240F04 + 0x40250F04 32 read-write 0 @@ -6982,7 +1196,7 @@ Cy_INTR_M_MASK Master interrupt mask register - 0x40240F08 + 0x40250F08 32 read-write 0 @@ -7035,7 +1249,7 @@ Cy_INTR_M_MASKED Master interrupt masked request register - 0x40240F0C + 0x40250F0C 32 read-write 0 @@ -7088,7 +1302,7 @@ Cy_INTR_S Slave interrupt request register - 0x40240F40 + 0x40250F40 32 read-write 0 @@ -7169,7 +1383,7 @@ Cy_INTR_S_SET Slave interrupt set request register - 0x40240F44 + 0x40250F44 32 read-write 0 @@ -7250,7 +1464,7 @@ Cy_INTR_S_MASK Slave interrupt mask register - 0x40240F48 + 0x40250F48 32 read-write 0 @@ -7331,7 +1545,7 @@ Cy_INTR_S_MASKED Slave interrupt masked register - 0x40240F4C + 0x40250F4C 32 read-write 0 @@ -7405,7 +1619,7 @@ Cy_INTR_TX Transmitter interrupt request register - 0x40240F80 + 0x40250F80 32 read-write 0 @@ -7472,7 +1686,7 @@ Cy_INTR_TX_SET Transmitter interrupt set request register - 0x40240F84 + 0x40250F84 32 read-write 0 @@ -7539,7 +1753,7 @@ Cy_INTR_TX_MASK Transmitter interrupt mask request register - 0x40240F88 + 0x40250F88 32 read-write 0 @@ -7606,7 +1820,7 @@ Cy_INTR_TX_MASKED Transmitter interrupt masked request register - 0x40240F8C + 0x40250F8C 32 read-write 0 @@ -7673,7 +1887,7 @@ Cy_INTR_RX Receiver interrupt request register - 0x40240FC0 + 0x40250FC0 32 read-write 0 @@ -7747,7 +1961,7 @@ Cy_INTR_RX_SET Receiver interrupt set request register - 0x40240FC4 + 0x40250FC4 32 read-write 0 @@ -7821,7 +2035,7 @@ Cy_INTR_RX_MASK Receiver interrupt mask register - 0x40240FC8 + 0x40250FC8 32 read-write 0 @@ -7895,7 +2109,7 @@ Cy_INTR_RX_MASKED Receiver interrupt masked register - 0x40240FCC + 0x40250FCC 32 read-write 0 @@ -7969,7 +2183,7 @@ - SCB + UART_DEB Serial Communication Block 0x0 @@ -7981,7 +2195,7 @@ Cy_CTRL Generic control register - 0x40250000 + 0x40240000 32 read-write 0 @@ -8055,7 +2269,7 @@ Cy_SPI_CTRL SPI control register - 0x40250020 + 0x40240020 32 read-write 0 @@ -8164,7 +2378,7 @@ Cy_SPI_STATUS SPI status register - 0x40250024 + 0x40240024 32 read-write 0 @@ -8182,7 +2396,7 @@ Cy_UART_CTRL UART control register - 0x40250040 + 0x40240040 32 read-write 0 @@ -8207,7 +2421,7 @@ Cy_UART_TX_CTRL UART transmitter control register - 0x40250044 + 0x40240044 32 read-write 0 @@ -8246,7 +2460,7 @@ Cy_UART_RX_CTRL UART receiver control register - 0x40250048 + 0x40240048 32 read-write 0 @@ -8327,7 +2541,7 @@ Cy_UART_FLOW_CTRL UART flow control register - 0x40250050 + 0x40240050 32 read-write 0 @@ -8366,7 +2580,7 @@ Cy_I2C_CTRL I2C control register - 0x40250060 + 0x40240060 32 read-write 0 @@ -8461,7 +2675,7 @@ Cy_I2C_STATUS I2C status register - 0x40250064 + 0x40240064 32 read-write 0 @@ -8493,7 +2707,7 @@ Cy_I2C_M_CMD I2C master command register - 0x40250068 + 0x40240068 32 read-write 0 @@ -8539,7 +2753,7 @@ Cy_I2C_S_CMD I2C slave command register - 0x4025006C + 0x4024006C 32 read-write 0 @@ -8564,7 +2778,7 @@ Cy_I2C_CFG I2C fitler trimm register - 0x40250070 + 0x40240070 32 read-write 0 @@ -8631,7 +2845,7 @@ Cy_TX_CTRL Transmitter control register - 0x40250200 + 0x40240200 32 read-write 0 @@ -8656,7 +2870,7 @@ Cy_TX_FIFO_CTRL Transmitter FIFO control register - 0x40250204 + 0x40240204 32 read-write 0 @@ -8688,7 +2902,7 @@ Cy_TX_FIFO_STATUS Transmitter FIFO status register - 0x40250208 + 0x40240208 32 read-write 0 @@ -8727,7 +2941,7 @@ Cy_TX_FIFO_WR Transmitter FIFO write register - 0x40250240 + 0x40240240 32 read-write 0 @@ -8745,7 +2959,7 @@ Cy_RX_CTRL Receiver control register - 0x40250300 + 0x40240300 32 read-write 0 @@ -8777,7 +2991,7 @@ Cy_RX_FIFO_CTRL Receiver FIFO control register - 0x40250304 + 0x40240304 32 read-write 0 @@ -8809,7 +3023,7 @@ Cy_RX_FIFO_STATUS Receiver FIFO status registerS - 0x40250308 + 0x40240308 32 read-write 0 @@ -8848,7 +3062,7 @@ Cy_RX_MATCH Slave address and mask register - 0x40250310 + 0x40240310 32 read-write 0 @@ -8873,7 +3087,7 @@ Cy_RX_FIFO_RD Receiver FIFO read register - 0x40250340 + 0x40240340 32 read-write 0 @@ -8891,7 +3105,7 @@ Cy_INTR_CAUSE Interrupt cause register - 0x40250E00 + 0x40240E00 32 read-write 0 @@ -8944,7 +3158,7 @@ Cy_INTR_I2C_EC Externally clocked I2C interrupt request register - 0x40250E80 + 0x40240E80 32 read-write 0 @@ -8962,7 +3176,7 @@ Cy_INTR_I2C_EC_MASK Externally clocked I2C interrupt mask register - 0x40250E88 + 0x40240E88 32 read-write 0 @@ -8980,7 +3194,7 @@ Cy_INTR_I2C_EC_MASKED Externally clocked SPI interrupt masked register - 0x40250E8C + 0x40240E8C 32 read-write 0 @@ -8998,7 +3212,7 @@ Cy_INTR_INTR_SPI_EC Externally clocked SPI interrupt request register - 0x40250EC0 + 0x40240EC0 32 read-write 0 @@ -9016,7 +3230,7 @@ Cy_INTR_INTR_SPI_EC_MASK Externally clocked SPI interrupt mask register - 0x40250EC8 + 0x40240EC8 32 read-write 0 @@ -9034,7 +3248,7 @@ Cy_INTR_INTR_SPI_EC_MASKED Externally clocked SPI interrupt masked register - 0x40250ECC + 0x40240ECC 32 read-write 0 @@ -9052,7 +3266,7 @@ Cy_INTR_M Master interrupt request register. - 0x40250F00 + 0x40240F00 32 read-write 0 @@ -9105,7 +3319,7 @@ Cy_INTR_M_SET Master interrupt set request register - 0x40250F04 + 0x40240F04 32 read-write 0 @@ -9158,7 +3372,7 @@ Cy_INTR_M_MASK Master interrupt mask register - 0x40250F08 + 0x40240F08 32 read-write 0 @@ -9211,7 +3425,7 @@ Cy_INTR_M_MASKED Master interrupt masked request register - 0x40250F0C + 0x40240F0C 32 read-write 0 @@ -9264,7 +3478,7 @@ Cy_INTR_S Slave interrupt request register - 0x40250F40 + 0x40240F40 32 read-write 0 @@ -9345,7 +3559,7 @@ Cy_INTR_S_SET Slave interrupt set request register - 0x40250F44 + 0x40240F44 32 read-write 0 @@ -9426,7 +3640,7 @@ Cy_INTR_S_MASK Slave interrupt mask register - 0x40250F48 + 0x40240F48 32 read-write 0 @@ -9507,7 +3721,7 @@ Cy_INTR_S_MASKED Slave interrupt masked register - 0x40250F4C + 0x40240F4C 32 read-write 0 @@ -9581,7 +3795,7 @@ Cy_INTR_TX Transmitter interrupt request register - 0x40250F80 + 0x40240F80 32 read-write 0 @@ -9648,7 +3862,7 @@ Cy_INTR_TX_SET Transmitter interrupt set request register - 0x40250F84 + 0x40240F84 32 read-write 0 @@ -9715,7 +3929,7 @@ Cy_INTR_TX_MASK Transmitter interrupt mask request register - 0x40250F88 + 0x40240F88 32 read-write 0 @@ -9782,7 +3996,7 @@ Cy_INTR_TX_MASKED Transmitter interrupt masked request register - 0x40250F8C + 0x40240F8C 32 read-write 0 @@ -9849,7 +4063,7 @@ Cy_INTR_RX Receiver interrupt request register - 0x40250FC0 + 0x40240FC0 32 read-write 0 @@ -9923,7 +4137,7 @@ Cy_INTR_RX_SET Receiver interrupt set request register - 0x40250FC4 + 0x40240FC4 32 read-write 0 @@ -9997,7 +4211,7 @@ Cy_INTR_RX_MASK Receiver interrupt mask register - 0x40250FC8 + 0x40240FC8 32 read-write 0 @@ -10071,7 +4285,7 @@ Cy_INTR_RX_MASKED Receiver interrupt masked register - 0x40250FCC + 0x40240FCC 32 read-write 0 diff --git a/BLE.cydsn/BLE_timing.html b/BLE.cydsn/BLE_timing.html index a018dee..3b90d37 100644 --- a/BLE.cydsn/BLE_timing.html +++ b/BLE.cydsn/BLE_timing.html @@ -539,12 +539,12 @@

Static Timing Analysis

Project : BLE Build Time : - 08/04/18 14:30:23 + 07/20/19 16:19:14 Device : - CY8C4248LQI-BL583 + CYBLE-014008-00 Temperature : -40C - 85C - VDDA_1 : + VDDA : 3.30 VDDA_CTB : 3.30 diff --git a/BLE.cydsn/Export/PSoCCreatorExportIDE.xml b/BLE.cydsn/Export/PSoCCreatorExportIDE.xml index b8ed7e8..845ebe9 100644 --- a/BLE.cydsn/Export/PSoCCreatorExportIDE.xml +++ b/BLE.cydsn/Export/PSoCCreatorExportIDE.xml @@ -1,7 +1,7 @@  - + @@ -25,7 +25,7 @@ - + BLE.svd @@ -112,18 +112,6 @@ Generated_Source\PSoC4\UART_DEB_SPI_UART_PVT.h Generated_Source\PSoC4\UART_DEB_PVT.h Generated_Source\PSoC4\UART_DEB_BOOT.h - Generated_Source\PSoC4\LED_BLU.c - Generated_Source\PSoC4\LED_BLU.h - Generated_Source\PSoC4\LED_BLU_aliases.h - Generated_Source\PSoC4\LED_BLU_PM.c - Generated_Source\PSoC4\LED_RED.c - Generated_Source\PSoC4\LED_RED.h - Generated_Source\PSoC4\LED_RED_aliases.h - Generated_Source\PSoC4\LED_RED_PM.c - Generated_Source\PSoC4\LED_GRN.c - Generated_Source\PSoC4\LED_GRN.h - Generated_Source\PSoC4\LED_GRN_aliases.h - Generated_Source\PSoC4\LED_GRN_PM.c Generated_Source\PSoC4\Wakeup_Interrupt.c Generated_Source\PSoC4\Wakeup_Interrupt.h Generated_Source\PSoC4\SW2.c @@ -177,8 +165,6 @@ Generated_Source\PSoC4\cmsis_gcc.h Generated_Source\PSoC4\cmsis_compiler.h Generated_Source\PSoC4\CyBootAsmGnu.s - Generated_Source\PSoC4\CyDMA.h - Generated_Source\PSoC4\CyDMA.c Generated_Source\PSoC4\CyLFClk.c Generated_Source\PSoC4\CyLFClk.h Generated_Source\PSoC4\cy_em_eeprom.c @@ -189,19 +175,19 @@ Generated_Source\PSoC4\cycodeshareimport.scat - + - .\Export\ARM_GCC_Generic\BLE_v3_53\gccCyBLEStack_BLE_SOC_PERIPHERAL.a + .\Export\ARM_GCC_Generic\BLE_v3_61\gccCyBLEStack_BLE_SOC_PERIPHERAL.a - + - .\Export\ARM_MDK_Generic\BLE_v3_53\mdkCyBLEStack_BLE_SOC_PERIPHERAL.a + .\Export\ARM_MDK_Generic\BLE_v3_61\mdkCyBLEStack_BLE_SOC_PERIPHERAL.a - + - .\Export\ARM_IAR_Generic\BLE_v3_53\gccCyBLEStack_BLE_SOC_PERIPHERAL.a + .\Export\ARM_IAR_Generic\BLE_v3_61\gccCyBLEStack_BLE_SOC_PERIPHERAL.a diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE.c b/BLE.cydsn/Generated_Source/PSoC4/BLE.c index 241c387..a6ad577 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE.c -* \version 3.53 +* \version 3.61 * * \brief * This file contains the source code for the Common APIs of the BLE Component. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -308,6 +308,10 @@ void CyBle_ServiceInit(void) CyBle_NdcsInit(); #endif /* CYBLE_NDCS */ + #ifdef CYBLE_OTS + CyBle_OtsInit(); + #endif /* CYBLE_OTS */ + #ifdef CYBLE_PASS CyBle_PassInit(); #endif /* CYBLE_PASS */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE.h b/BLE.cydsn/Generated_Source/PSoC4/BLE.h index 702fb1e..ace9726 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants available to the BLE component. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_INT.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_INT.c index 5ca6503..2ab5ce7 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_INT.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_INT.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file BLE_HAL_INT.c -* \version 3.53 +* \version 3.61 * * \brief * This file contains the source code for the Interrupt Service Routine for the @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.c index 0c68513..069f77f 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_HAL_PVT.c -* \version 3.53 +* \version 3.61 * * \brief * This file contains the source code for the HAL section of the BLE component * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -560,14 +560,14 @@ uint32 CyBLE_GetIpBlockVersion(void) return (CYBLE_ERROR_OK); } - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_local_P256_public_key(uint8 param) + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_local_P256_public_key(uint8 param) { - return (CyBle_Hal_mapping_tbx_generate_local_P256_public_key(param)); + return (CyBle_Hal_mapping_generate_local_P256_public_key(param)); } - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_DHkey(void * param1, void * param2) + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_DHkey(void * param1, void * param2) { - return (CyBle_Hal_mapping_tbx_generate_DHkey(param1, param2)); + return (CyBle_Hal_mapping_generate_DHkey(param1, param2)); } void CyBle_Hal_smp_sc_cmac_complete(void) @@ -585,6 +585,12 @@ uint32 CyBLE_GetIpBlockVersion(void) CyBle_Hal_Mapping_EccPointMult(); } + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_validate_p256_pub_key_pair (void *param1) + { + return (CyBle_Hal_mapping_validate_p256_pub_key_pair(param1)); + } + + #else /* If feature is not required, return error. */ CYBLE_API_RESULT_T CyBle_Hal_pairing_local_public_key_handler(void *param CYBLE_UNUSED_ATTR) @@ -637,12 +643,12 @@ uint32 CyBLE_GetIpBlockVersion(void) return (CYBLE_ERROR_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE); } - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_local_P256_public_key(uint8 param CYBLE_UNUSED_ATTR) + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_local_P256_public_key(uint8 param CYBLE_UNUSED_ATTR) { return (CYBLE_ERROR_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE); } - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_DHkey(void * param1 CYBLE_UNUSED_ATTR, + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_DHkey(void * param1 CYBLE_UNUSED_ATTR, void * param2 CYBLE_UNUSED_ATTR) { return (CYBLE_ERROR_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE); @@ -662,6 +668,11 @@ uint32 CyBLE_GetIpBlockVersion(void) { } + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_validate_p256_pub_key_pair (void *param1 CYBLE_UNUSED_ATTR) + { + return (CYBLE_ERROR_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE); + } + #endif /* (CYBLE_SECURE_CONN_FEATURE_ENABLED) */ #endif /* CYBLE_MODE_PROFILE */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.h index a8bf0e6..a459f92 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_HAL_PVT.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CYBLE_HAL_PVT.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants for the HAL section @@ -10,7 +10,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -153,11 +153,13 @@ cystatus CyBLE_Nvram_Erase (const uint8 *varFlash, uint16 length); CYBLE_API_RESULT_T CyBle_Hal_mapping_pairing_lr_confirming_handler(void *param); void CyBle_Hal_mapping_tbx_dhkey_generate_complete(void *param); void CyBle_Hal_mapping_tbx_local_pubkey_generate_complete(void); - CYBLE_API_RESULT_T CyBle_Hal_mapping_tbx_generate_local_P256_public_key(uint8 param); - CYBLE_API_RESULT_T CyBle_Hal_mapping_tbx_generate_DHkey(void *param1, void *param2); + CYBLE_API_RESULT_T CyBle_Hal_mapping_generate_local_P256_public_key(uint8 param); + CYBLE_API_RESULT_T CyBle_Hal_mapping_generate_DHkey(void *param1, void *param2); void CyBle_Hal_Mapping_smp_sc_cmac_complete(void); CYBLE_API_RESULT_T CyBle_Hal_mapping_se_smp_sc_user_passkey_handler(void *param,void *param2); void CyBle_Hal_Mapping_EccPointMult(void); + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_validate_p256_pub_key_pair (void *param1); + #endif /* (CYBLE_SECURE_CONN_FEATURE_ENABLED) && (CYBLE_MODE_PROFILE) */ #if(CYBLE_SECURE_CONN_FEATURE_ENABLED) diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_STACK_PVT.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_STACK_PVT.h index a2d81c4..f95217b 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_STACK_PVT.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_STACK_PVT.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CYBLE_STACK_PVT.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants for the HAL section @@ -10,7 +10,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -62,9 +62,10 @@ void CyBLE_BlessDeviceConfig(void); CYBLE_API_RESULT_T CyBle_Hal_pairing_lr_confirming_handler(void *param); CYBLE_API_RESULT_T CyBle_Hal_pairing_lr_confirming_handler(void *param); CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_dhkey_generate_complete(void* param); - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_local_P256_public_key(uint8 param); - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_DHkey(void * param1, void * param2); + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_local_P256_public_key(uint8 param); + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_DHkey(void * param1, void * param2); CYBLE_API_RESULT_T CyBle_Hal_se_smp_sc_user_passkey_handler(void *param1, void *param2); + CYBLE_API_RESULT_T CyBle_Hal_mapping_validate_p256_pub_key_pair(void *param1); #else CYBLE_API_RESULT_T CyBle_Hal_pairing_local_public_key_handler(void *param CYBLE_UNUSED_ATTR); CYBLE_API_RESULT_T CyBle_Hal_pairing_remote_key_handler(void *param CYBLE_UNUSED_ATTR); @@ -75,11 +76,13 @@ void CyBLE_BlessDeviceConfig(void); CYBLE_API_RESULT_T CyBle_Hal_pairing_confirm_handler(void *param CYBLE_UNUSED_ATTR); CYBLE_API_RESULT_T CyBle_Hal_pairing_lr_confirming_handler(void *param CYBLE_UNUSED_ATTR); CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_dhkey_generate_complete(void* param CYBLE_UNUSED_ATTR); - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_local_P256_public_key(uint8 param CYBLE_UNUSED_ATTR); - CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_tbx_generate_DHkey(void * param1 CYBLE_UNUSED_ATTR, + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_local_P256_public_key(uint8 param CYBLE_UNUSED_ATTR); + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_generate_DHkey(void * param1 CYBLE_UNUSED_ATTR, void * param2 CYBLE_UNUSED_ATTR); CYBLE_API_RESULT_T CyBle_Hal_se_smp_sc_user_passkey_handler(void *param1 CYBLE_UNUSED_ATTR, void *param2 CYBLE_UNUSED_ATTR); + CYBLE_API_RESULT_T CyBle_Hal_pairing_sc_validate_p256_pub_key_pair (void *param1 CYBLE_UNUSED_ATTR); + #endif /* (CYBLE_SECURE_CONN_FEATURE_ENABLED) */ #endif /* CYBLE_MODE_PROFILE */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_Stack.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_Stack.h index c6b06ae..1b0fcb3 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_Stack.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_Stack.h @@ -2,7 +2,7 @@ * \file CyBle.h * * \file CYBLE_Stack.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains declaration of public BLE APIs other than those covered by @@ -14,7 +14,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGap.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGap.h index 5620d57..cb4a1c8 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGap.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGap.h @@ -2,7 +2,7 @@ * \file CyBle_Gap.h * * \file CYBLE_StackGap.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the GAP APIs of the BLE Host Stack IP @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -2689,10 +2689,17 @@ CYBLE_API_RESULT_T CyBle_GapSetSecureConnectionsOnlyMode(uint8 state); * Function Name: CyBle_GapGenerateLocalP256Keys ***************************************************************************//** * -* This API function is used to generate P-256 Public-Private key pair to be used during LE Secure connection -* pairing procedure. Application may choose to generate P-256 public-private key pair before pairing -* process starts. If this API function is not called before pairing process starts, BLE Stack will use default -* public-private key pair. +* This API function is used to generate P-256 Public-Private key pair to be used +* during LE Secure connection pairing procedure. Application may choose to generate +* P-256 public-private key pair before pairing process starts. If this API function +* is not called before pairing process starts, BLE Stack will use default public-private +* key pair. +* +* For robust security Cypress recommends that, the application may change the local +* public-private key pair after every pairing (successful or failed) attempt. +* +* For details, refer to Bluetooth core specification 4.2, Volume 3, part H, section 2.3.6. +* * On the Completion of key generation, new keys will be set in the BLE Stack for SC pairing procedure * and application receives CYBLE_EVT_GAP_SMP_LOC_P256_KEYS_GEN_AND_SET_COMPLETE event. * @@ -2721,6 +2728,11 @@ CYBLE_API_RESULT_T CyBle_GapGenerateLocalP256Keys(void); * Application can generate P-256 Public-Private key pair using API function CyBle_GapGenerateLocalP256Keys() * and can set the generated key pair using this API function. * +* For robust security Cypress recommends that, the application may change the local +* public-private key pair after every pairing (successful or failed) attempt. +* +* For details, refer to Bluetooth core specification 4.2, Volume 3, part H, section 2.3.6. +* * \param localP256Keys: Pointer to structure CYBLE_GAP_SMP_LOCAL_P256_KEYS, that has * fields for local P-256 public-private key pair. * \param isValidateKeys: If it is set to 1 public key is validated, if it is set to 0 diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGatt.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGatt.h index 6844a32..a219841 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGatt.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGatt.h @@ -2,7 +2,7 @@ * \file CyBle_Gatt.h * * \file CYBLE_StackGatt.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the GATT APIs of the BLE Host Stack IP @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattClient.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattClient.h index 9494c58..31f3138 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattClient.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattClient.h @@ -2,7 +2,7 @@ * \file CyBle_GattClient.h * * \file CYBLE_StackGattClient.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the GATT Client routines @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattDb.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattDb.h index 2bd4b7c..131ad17 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattDb.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattDb.h @@ -2,7 +2,7 @@ * \file CyBle_GattDb.h * * \file CYBLE_StackGattDb.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the data structure for GATT Database @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattServer.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattServer.h index 98daabd..9c3da4a 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattServer.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackGattServer.h @@ -2,7 +2,7 @@ * \file CyBle_GattServer.h * * \file CYBLE_StackGattServer.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the GATT Server routines @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackHostMain.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackHostMain.h index 9bf0afb..21dcac9 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackHostMain.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackHostMain.h @@ -2,7 +2,7 @@ * \file CyBle_HostMain.h * * \file CYBLE_StackHostMain.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the constants of the BLE Host Stack IP @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackL2cap.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackL2cap.h index a3c40a3..0df60c3 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_StackL2cap.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_StackL2cap.h @@ -2,7 +2,7 @@ * \file CyBle_L2cap.h * * \file CYBLE_StackL2cap.h -* \version 3.53 +* \version 3.61 * * \brief * This file contains the L2CAP APIs of the BLE Host Stack IP @@ -12,7 +12,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.c index 6124da0..9d32f4d 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_bas.c -* \version 3.53 +* \version 3.61 * * \brief * Contains the source code for BLE Battery Service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.h index 27d6d37..da6c980 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_bas.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_bas.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants for Battery Service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.c index d6e7f93..6d28e67 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_dis.c -* \version 3.53 +* \version 3.61 * * \brief * Contains the source code for the Device Information Service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.h index 223f302..9f4666f 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_dis.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CYBLE_dis.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants for Device Information @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.c index 1e98405..487ea68 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CYBLE_eventHandler.c -* \version 3.53 +* \version 3.61 * * \brief * This file contains the source code for the Event Handler State Machine @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -188,6 +188,9 @@ CYBLE_DISC_SRVC_INFO_T cyBle_serverInfo[CYBLE_SRVI_COUNT] = /*8*/ #ifdef CYBLE_IPSS_CLIENT {{CYBLE_GATT_INVALID_ATTR_HANDLE_VALUE, CYBLE_GATT_INVALID_ATTR_HANDLE_VALUE}, CYBLE_UUID_INTERNET_PROTOCOL_SUPPORT_SERVICE}, #endif /* CYBLE_IPSS_CLIENT */ +#ifdef CYBLE_OTS_CLIENT + {{CYBLE_GATT_INVALID_ATTR_HANDLE_VALUE, CYBLE_GATT_INVALID_ATTR_HANDLE_VALUE}, CYBLE_UUID_OTS_SERVICE}, +#endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_PASS_CLIENT {{CYBLE_GATT_INVALID_ATTR_HANDLE_VALUE, CYBLE_GATT_INVALID_ATTR_HANDLE_VALUE}, CYBLE_UUID_PHONE_ALERT_STATUS_SERVICE}, #endif /* CYBLE_PASS_CLIENT */ @@ -380,6 +383,12 @@ static void CyBle_WriteReqHandler(CYBLE_GATTS_WRITE_REQ_PARAM_T *eventParam) gattErr = CyBle_LnssWriteEventHandler(eventParam); } #endif /* CYBLE_LNS_SERVER */ +#ifdef CYBLE_OTS_SERVER + if(((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) && (gattErr == CYBLE_GATT_ERR_NONE)) + { + gattErr = CyBle_OtssWriteEventHandler(eventParam); + } +#endif /* CYBLE_OTS_SERVER */ #ifdef CYBLE_PASS_SERVER if(((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) && (gattErr == CYBLE_GATT_ERR_NONE)) { @@ -532,6 +541,13 @@ static void CyBle_ValueConfirmation(const CYBLE_CONN_HANDLE_T *eventParam) } #endif /* CYBLE_LNS_SERVER */ + #ifdef CYBLE_OTS_SERVER + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtssConfirmationEventHandler(eventParam); + } + #endif /* CYBLE_OTS_SERVER */ + #ifdef CYBLE_PLXS_SERVER if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -726,6 +742,13 @@ static void CyBle_GattcWriteResponseEventHandler(const CYBLE_CONN_HANDLE_T *even } #endif /* CYBLE_LNS_CLIENT */ +#ifdef CYBLE_OTS_CLIENT + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtscWriteResponseEventHandler(eventParam); + } +#endif /* CYBLE_OTS_CLIENT */ + #ifdef CYBLE_PASS_CLIENT if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -1008,6 +1031,12 @@ static void CyBle_IndicationEventHandler(CYBLE_GATTC_HANDLE_VALUE_IND_PARAM_T *e CyBle_LnscIndicationEventHandler(eventParam); } #endif /* CYBLE_LNS_CLIENT */ +#ifdef CYBLE_OTS_CLIENT + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtscIndicationEventHandler(eventParam); + } +#endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_PLXS_CLIENT if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -1223,6 +1252,12 @@ static void CyBle_ReadResponseEventHandler(CYBLE_GATTC_READ_RSP_PARAM_T *eventPa CyBle_NdcscReadResponseEventHandler(eventParam); } #endif /* CYBLE_NDCS_CLIENT */ +#ifdef CYBLE_OTS_CLIENT + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtscReadResponseEventHandler(eventParam); + } +#endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_PASS_CLIENT if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -2028,6 +2063,12 @@ void CyBle_EventHandler(uint8 eventCode, void *eventParam) CyBle_IpssPrepareWriteRequestEventHandler((CYBLE_GATTS_PREP_WRITE_REQ_PARAM_T *)eventParam); } #endif /* CYBLE_IPS_SERVER */ + #ifdef CYBLE_OTS_SERVER + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtssPrepareWriteRequestEventHandler((CYBLE_GATTS_PREP_WRITE_REQ_PARAM_T *)eventParam); + } + #endif /* CYBLE_OTS_SERVER */ #ifdef CYBLE_UDS_SERVER if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -2052,6 +2093,9 @@ void CyBle_EventHandler(uint8 eventCode, void *eventParam) #ifdef CYBLE_IPS_SERVER CyBle_IpssExecuteWriteRequestEventHandler((CYBLE_GATTS_EXEC_WRITE_REQ_T *)eventParam); #endif /* CYBLE_IPS_SERVER */ + #ifdef CYBLE_OTS_SERVER + CyBle_OtssExecuteWriteRequestEventHandler((CYBLE_GATTS_EXEC_WRITE_REQ_T *)eventParam); + #endif /* CYBLE_OTS_SERVER */ #ifdef CYBLE_UDS_SERVER CyBle_UdssExecuteWriteRequestEventHandler((CYBLE_GATTS_EXEC_WRITE_REQ_T *)eventParam); #endif /* CYBLE_UDS_SERVER */ @@ -2089,6 +2133,9 @@ void CyBle_EventHandler(uint8 eventCode, void *eventParam) #ifdef CYBLE_IPS_CLIENT CyBle_IpscReadLongRespEventHandler((CYBLE_GATTC_READ_RSP_PARAM_T *)eventParam); #endif /* CYBLE_IPS_CLIENT */ + #ifdef CYBLE_OTS_CLIENT + CyBle_OtscReadLongRespEventHandler((CYBLE_GATTC_READ_RSP_PARAM_T *)eventParam); + #endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_UDS_CLIENT if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -2158,6 +2205,12 @@ void CyBle_EventHandler(uint8 eventCode, void *eventParam) CyBle_IpscExecuteWriteResponseEventHandler((CYBLE_GATTC_EXEC_WRITE_RSP_T *)eventParam); } #endif /* CYBLE_IPS_CLIENT */ + #ifdef CYBLE_OTS_CLIENT + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtscExecuteWriteResponseEventHandler((CYBLE_GATTC_EXEC_WRITE_RSP_T *)eventParam); + } + #endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_UDS_CLIENT if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { @@ -2591,6 +2644,11 @@ void CyBle_ReadByTypeEventHandler(CYBLE_GATTC_READ_BY_TYPE_RSP_PARAM_T *eventPar CyBle_LnscDiscoverCharacteristicsEventHandler(&discCharInfo); break; #endif /* CYBLE_LNS_CLIENT */ + #ifdef CYBLE_OTS_CLIENT + case CYBLE_UUID_OTS_SERVICE: + CyBle_OtscDiscoverCharacteristicsEventHandler(&discCharInfo); + break; + #endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_PASS_CLIENT case CYBLE_UUID_PHONE_ALERT_STATUS_SERVICE: CyBle_PasscDiscoverCharacteristicsEventHandler(&discCharInfo); @@ -3127,6 +3185,13 @@ static CYBLE_GATT_ATTR_HANDLE_RANGE_T CyBle_GetCharRange(void) charRange.endHandle = cyBle_lnsc.charInfo[charIdx].endHandle; } #endif /* CYBLE_LNS_CLIENT */ +#ifdef CYBLE_OTS_CLIENT + if((cyBle_disCount >= (uint8) CYBLE_SCDI_OTS_FEATURE) && (cyBle_disCount <= (uint8) CYBLE_SCDI_OTS_OBJECT_CHANGED)) + { + charRange.startHandle = cyBle_otsc.charInfo[(cyBle_disCount - CYBLE_SCDI_OTS_FEATURE) + 1u].valueHandle + 1u; + charRange.endHandle = cyBle_otsc.charInfo[(cyBle_disCount - CYBLE_SCDI_OTS_FEATURE) + 1u].endHandle; + } +#endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_PASS_CLIENT if((cyBle_disCount == (uint8) CYBLE_SCDI_PASS_AS) || (cyBle_disCount == (uint8) CYBLE_SCDI_PASS_RS)) { @@ -3444,6 +3509,15 @@ void CyBle_FindInfoEventHandler(CYBLE_GATTC_FIND_INFO_RSP_PARAM_T *eventParam) } #endif /* CYBLE_LNS_CLIENT */ + #ifdef CYBLE_OTS_CLIENT + if((cyBle_disCount >= (uint8) CYBLE_SCDI_OTS_FEATURE) && + (cyBle_disCount <= (uint8) CYBLE_SCDI_OTS_OBJECT_CHANGED)) + { + uint8 charIdx = (cyBle_disCount - CYBLE_SCDI_OTS_FEATURE) + 1u; + CyBle_OtscDiscoverCharDescriptorsEventHandler((CYBLE_OTS_CHAR_INDEX_T)charIdx, &discDescrInfo); + } + #endif /* CYBLE_OTS_CLIENT */ + #ifdef CYBLE_PASS_CLIENT if((cyBle_disCount == (uint8) CYBLE_SCDI_PASS_AS) || (cyBle_disCount == (uint8) CYBLE_SCDI_PASS_RS)) @@ -3503,12 +3577,14 @@ void CyBle_FindInfoEventHandler(CYBLE_GATTC_FIND_INFO_RSP_PARAM_T *eventParam) CyBle_UdscDiscoverCharDescriptorsEventHandler(&discDescrInfo); } #endif /* CYBLE_UDS_CLIENT */ + #ifdef CYBLE_WPTS_CLIENT if(cyBle_disCount == (uint8) CYBLE_SCDI_WPTS_PRU_ALERT) { CyBle_WptscDiscoverCharDescriptorsEventHandler(&discDescrInfo); } #endif /* CYBLE_WPTS_CLIENT */ + #ifdef CYBLE_WSS_CLIENT if((cyBle_disCount >= (uint8) CYBLE_SCDI_WSS_WEIGHT_SCALE_FEATURE) && (cyBle_disCount <= (uint8) CYBLE_SCDI_WSS_WEIGHT_WEIGHT_MEASUREMENT)) @@ -3832,6 +3908,12 @@ void CyBle_ErrorResponseEventHandler(const CYBLE_GATTC_ERR_RSP_PARAM_T *eventPar CyBle_LnscErrorResponseEventHandler(eventParam); } #endif /* CYBLE_LNS_CLIENT */ + #ifdef CYBLE_OTS_CLIENT + if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) + { + CyBle_OtscErrorResponseEventHandler(eventParam); + } + #endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_PASS_CLIENT if((cyBle_eventHandlerFlag & CYBLE_CALLBACK) != 0u) { diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.h index c497df1..56d59ac 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_eventHandler.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CYBLE_eventHandler.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the prototypes and constants used in the Event Handler State Machine @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -100,6 +100,9 @@ #ifdef CYBLE_NDCS #include "BLE_ndcs.h" #endif /* CYBLE_NDCS */ +#ifdef CYBLE_OTS + #include "BLE_ots.h" +#endif /* CYBLE_OTS */ #ifdef CYBLE_PASS #include "BLE_pass.h" #endif /* CYBLE_PASS */ @@ -1585,6 +1588,81 @@ typedef enum */ CYBLE_EVT_NDCSC_READ_CHAR_RESPONSE, + /**************************************** + OTS Service Events + ***************************************/ + + /** OTS Server - Indication for Object Transfer Service Characteristic + was enabled. The parameter of this event is a structure + of CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSS_INDICATION_ENABLED, + + /** OTSS Server - Indication for Object Transfer Service Characteristic + was disabled. The parameter of this event is a structure + of CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSS_INDICATION_DISABLED, + + /** OTS Server - Object Transfer Service Characteristic + Indication was confirmed. The parameter of this event + is a structure of CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSS_INDICATION_CONFIRMED, + + /** OTS Server - Write Request for Object Transfer Service Characteristic + was received. The parameter of this event is a structure + of CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSS_WRITE_CHAR, + + /** OTSS Server - Write Request for Object Transfer Service + Characteristic Descriptor was received. The parameter of this event is a structure of + CYBLE_OTSS_DESCR_VALUE_T type. + */ + CYBLE_EVT_OTSS_WRITE_DESCR, + + /** OTS Client - Object Transfer Service Characteristic + Indication was received. The parameter of this event + is a structure of CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSC_INDICATION, + + /** OTS Client - Read Response for Read Request for Object Transfer Service Characteristic + Value. The parameter of this event is a structure of + CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSC_READ_CHAR_RESPONSE, + + /** OTS Client - Read Response for Long Read Request of Object Transfer + Service Characteristic value. The parameter of this event + is a structure of CYBLE_IPS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSC_READ_BLOB_RSP, + + /** OTS Client - Write Response for Write Request for Object Transfer Service + Characteristic Value. The parameter of this event is a structure of + CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSC_WRITE_CHAR_RESPONSE, + + /** OTS Client - Read Response for Read Request for Object Transfer Service + Characteristic Descriptor Read Request. The parameter of this event is a + structure of CYBLE_OTS_DESCR_VALUE_T type. + */ + CYBLE_EVT_OTSC_READ_DESCR_RESPONSE, + + /** OTS Client - Write Response for Write Request for Object Transfer Service + Client Characteristic Configuration Descriptor Value. The parameter of + this event is a structure of CYBLE_OTS_DESCR_VALUE_T type. + */ + CYBLE_EVT_OTSC_WRITE_DESCR_RESPONSE, + + /** OTS Client - Error Response for Write Request for Object Transfer Service + Characteristic Value. The parameter of this event is a structure of + CYBLE_OTS_CHAR_VALUE_T type. + */ + CYBLE_EVT_OTSC_ERROR_RESPONSE, /**************************************** Phone Alert Status Service Events @@ -2290,6 +2368,9 @@ typedef enum #ifdef CYBLE_PLXS_CLIENT CYBLE_SRVI_PLXS, #endif /* CYBLE_PLXS_CLIENT */ +#ifdef CYBLE_OTS_CLIENT + CYBLE_SRVI_OTS, +#endif /* CYBLE_OTS_CLIENT */ #ifdef CYBLE_RSCS_CLIENT CYBLE_SRVI_RSCS, #endif /* CYBLE_RSCS_CLIENT */ @@ -2419,6 +2500,24 @@ typedef enum CYBLE_SCDI_LNS_CP, /**< L&N Control Point characteristic index */ CYBLE_SCDI_LNS_NV, /**< Navigation characteristic index */ #endif /* CYBLE_LNS_CLIENT */ + +#ifdef CYBLE_OTS_CLIENT + CYBLE_SCDI_OTS_FEATURE, /**< Exposes which optional features are supported by the Server implementation.*/ + CYBLE_SCDI_OTS_OBJECT_NAME, /**< The name of the Current Object. */ + CYBLE_SCDI_OTS_OBJECT_TYPE, /**< The type of the Current Object, identifying the object type by UUID. */ + CYBLE_SCDI_OTS_OBJECT_SIZE, /**< The current size as well as the allocated size of the Current Object. */ + CYBLE_SCDI_OTS_OBJECT_FIRST_CREATED, /**< Date and time when the object contents were first created. */ + CYBLE_SCDI_OTS_OBJECT_LAST_MODIFIED, /**< Date and time when the object content was last modified. */ + CYBLE_SCDI_OTS_OBJECT_ID, /**< The Object ID of the Current Object. The Object ID is a LUID (Locally Unique Identifier). */ + CYBLE_SCDI_OTS_OBJECT_PROPERTIES, /**< The properties of the Current Object. */ + CYBLE_SCDI_OBJECT_ACTION_CONTROL_POINT, /**< Is used by a Client to control certain behaviors of the Server. */ + CYBLE_SCDI_OBJECT_LIST_CONTROL_POINT, /**< Provides a mechanism for the Client to find the desired object and to designate it as the Current Object. */ + CYBLE_SCDI_OBJECT_LIST_FILTER_1, /**< The filter conditions determines which objects are included in or excluded from the list of objects.*/ + CYBLE_SCDI_OBJECT_LIST_FILTER_2, /**< The filter conditions determines which objects are included in or excluded from the list of objects.*/ + CYBLE_SCDI_OBJECT_LIST_FILTER_3, /**< The filter conditions determines which objects are included in or excluded from the list of objects.*/ + CYBLE_SCDI_OTS_OBJECT_CHANGED, /**< Enables a Client to receive an indication if the contents and/or metadata of one or more objects are changed.*/ +#endif /* CYBLE_OTS_CLIENT */ + #ifdef CYBLE_PASS_CLIENT CYBLE_SCDI_PASS_AS, /**< Alert Status characteristic index */ CYBLE_SCDI_PASS_RS, /**< Ringer Settings characteristic index */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.c index 684ad0c..0290be0 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_gatt.c -* \version 3.53 +* \version 3.61 * * \brief * This file contains the source code for the GATT API of the BLE Component. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.h index 15e57d5..5e0a424 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_gatt.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_gatt.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the prototypes and constants used in the BLE GATT profile. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -305,8 +305,9 @@ extern CYBLE_GATT_ATTR_HANDLE_RANGE_T cyBle_gattcDiscoveryRange; #define CYBLE_UUID_CGM_SERVICE (0x181Fu) #define CYBLE_UUID_INTERNET_PROTOCOL_SUPPORT_SERVICE (0x1820u) #define CYBLE_UUID_IPS_SERVICE (0x1821u) -#define CYBLE_UUID_PLX_SERVICE (0x1822u) +#define CYBLE_UUID_PLX_SERVICE (0x1822u) #define CYBLE_UUID_HTTP_PROXY_SERVICE (0x1823u) +#define CYBLE_UUID_OTS_SERVICE (0x1825u) #define CYBLE_UUID_FIND_ME_SERVICE (0x18A3u) #define CYBLE_UUID_WIRELESS_POWER_TRANSFER_SERVICE (0xFFFEu) @@ -564,6 +565,19 @@ extern CYBLE_GATT_ATTR_HANDLE_RANGE_T cyBle_gattcDiscoveryRange; #define CYBLE_UUID_CHAR_HTTP_STATUS_CODE (0x2AB8u) #define CYBLE_UUID_CHAR_HTTPS_SECURITY (0x2ABBu) +/* OTS Characteristics defines */ +#define CYBLE_UUID_CHAR_OBJECT_FEATURE (0x2ABDu) +#define CYBLE_UUID_CHAR_OBJECT_NAME (0x2ABEu) +#define CYBLE_UUID_CHAR_OBJECT_TYPE (0x2ABFu) +#define CYBLE_UUID_CHAR_OBJECT_SIZE (0x2AC0u) +#define CYBLE_UUID_CHAR_OBJECT_FIRST_CREATED (0x2AC1u) +#define CYBLE_UUID_CHAR_OBJECT_LAST_MODIFIED (0x2AC2u) +#define CYBLE_UUID_CHAR_OBJECT_ID (0x2AC3u) +#define CYBLE_UUID_CHAR_OBJECT_PROPERTIES (0x2AC4u) +#define CYBLE_UUID_CHAR_OBJECT_ACTION_CONTROL_POINT (0x2AC5u) +#define CYBLE_UUID_CHAR_OBJECT_LIST_CONTROL_POINT (0x2AC6u) +#define CYBLE_UUID_CHAR_OBJECT_LIST_FILTER (0x2AC7u) +#define CYBLE_UUID_CHAR_OBJECT_CHANGED (0x2AC8u) /* GATT Characteristic Properties bit field */ #define CYBLE_CHAR_PROP_BROADCAST (0x01u) diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.c index 6558b4e..4daa984 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_hids.c -* \version 3.53 +* \version 3.61 * * \brief * Contains the source code for the HID service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.h index 4a8bced..773374c 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_hids.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_hids.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants for HID service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.c b/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.c index 6c42a34..5ae4430 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.c +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_scps.c -* \version 3.53 +* \version 3.61 * * \brief * Contains the source code for the Scan Parameter service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.h b/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.h index f9cff94..cfe1f2a 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.h +++ b/BLE.cydsn/Generated_Source/PSoC4/BLE_scps.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file CYBLE_scps.h -* \version 3.53 +* \version 3.61 * * \brief * Contains the function prototypes and constants for the Scan Parameter service. * ******************************************************************************** * \copyright -* Copyright 2014-2018, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2014-2019, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/BLE.cydsn/Generated_Source/PSoC4/Cm0Iar.icf b/BLE.cydsn/Generated_Source/PSoC4/Cm0Iar.icf index ce4bfe3..0d5e225 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/Cm0Iar.icf +++ b/BLE.cydsn/Generated_Source/PSoC4/Cm0Iar.icf @@ -5,9 +5,9 @@ define symbol __ICFEDIT_intvec_start__ = 0x00000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x0; -define symbol __ICFEDIT_region_ROM_end__ = 262144 - 1; +define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + 32768 - 1; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + 16384 - 1; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x0800; define symbol __ICFEDIT_size_heap__ = 0x400; @@ -15,9 +15,9 @@ define symbol __ICFEDIT_size_heap__ = 0x400; /******** Definitions ********/ -define symbol CY_FLASH_SIZE = 262144; +define symbol CY_FLASH_SIZE = 131072; define symbol CY_APPL_ORIGIN = 0; -define symbol CY_FLASH_ROW_SIZE = 256; +define symbol CY_FLASH_ROW_SIZE = 128; define symbol CY_APPL_LOADABLE = 0; define symbol CY_APPL_LOADER = 0; define symbol CY_APPL_NUM = 1; diff --git a/BLE.cydsn/Generated_Source/PSoC4/Cm0RealView.scat b/BLE.cydsn/Generated_Source/PSoC4/Cm0RealView.scat index 089901e..68d1e80 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/Cm0RealView.scat +++ b/BLE.cydsn/Generated_Source/PSoC4/Cm0RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm0RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief This Linker Descriptor file describes the memory layout of the PSOC4 ;* device family. The memory layout of the final binary and hex images as well @@ -28,9 +28,9 @@ #include "cyfitter.h" #include "cycodeshareimport.scat" -#define CY_FLASH_SIZE 262144 +#define CY_FLASH_SIZE 131072 #define CY_APPL_ORIGIN 0 -#define CY_FLASH_ROW_SIZE 256 +#define CY_FLASH_ROW_SIZE 128 #define CY_METADATA_SIZE 64 #define CY_APPL_FOR_STACK_AND_COPIER 0 @@ -116,11 +116,11 @@ APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) .ANY (+RW, +ZI) } - ARM_LIB_HEAP (0x20000000 + 32768 - 0x400 - 0x0800) EMPTY 0x400 + ARM_LIB_HEAP (0x20000000 + 16384 - 0x400 - 0x0800) EMPTY 0x400 { } - ARM_LIB_STACK (0x20000000 + 32768) EMPTY -0x0800 + ARM_LIB_STACK (0x20000000 + 16384) EMPTY -0x0800 { } } diff --git a/BLE.cydsn/Generated_Source/PSoC4/Cm0Start.c b/BLE.cydsn/Generated_Source/PSoC4/Cm0Start.c index e3d9780..ac50a37 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/Cm0Start.c +++ b/BLE.cydsn/Generated_Source/PSoC4/Cm0Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm0Start.c -* \version 5.70 +* \version 5.80 * * \brief Startup code for the ARM CM0. * diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s b/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s index b4dd111..d2ef0ea 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s +++ b/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief Assembly routines for GNU as. * diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s b/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s index 81aa2af..deca789 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s +++ b/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; \file CyBootAsmIar.s -; \version 5.70 +; \version 5.80 ; ; \brief Assembly routines for IAR Embedded Workbench IDE. ; diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s b/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s index a1396f0..b4b545d 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s +++ b/BLE.cydsn/Generated_Source/PSoC4/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; \file CyBootAsmRv.s -; \version 5.70 +; \version 5.80 ; ; \brief Assembly routines for RealView. ; diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyFlash.c b/BLE.cydsn/Generated_Source/PSoC4/CyFlash.c index 2a1f2ad..fae8c31 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyFlash.c +++ b/BLE.cydsn/Generated_Source/PSoC4/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH. * diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyFlash.h b/BLE.cydsn/Generated_Source/PSoC4/CyFlash.h index 0ea8ecf..b10203f 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyFlash.h +++ b/BLE.cydsn/Generated_Source/PSoC4/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH. * diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyLib.c b/BLE.cydsn/Generated_Source/PSoC4/CyLib.c index 75d5292..95276d3 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyLib.c +++ b/BLE.cydsn/Generated_Source/PSoC4/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the Clocking, Interrupts, SysTick, and * Voltage Detect. @@ -71,17 +71,6 @@ uint32 CySysTickInitVar = 0u; /* 47 MHz */ 0x34u, /* 48 MHz */ 0x35u }; #endif /* (CY_IP_SRSSV2) */ -#if (CY_IP_IMO_TRIMMABLE_BY_WCO) - /* Conversion between IMO frequency and WCO DPLL max offset steps */ - const uint8 cyImoFreqMhz2DpllOffset[CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE] = { - /* 26 MHz */ 238u, /* 27 MHz */ 219u, /* 28 MHz */ 201u, /* 29 MHz */ 185u, - /* 30 MHz */ 170u, /* 31 MHz */ 155u, /* 32 MHz */ 142u, /* 33 MHz */ 130u, - /* 34 MHz */ 118u, /* 35 MHz */ 107u, /* 36 MHz */ 96u, /* 37 MHz */ 86u, - /* 38 MHz */ 77u, /* 39 MHz */ 68u, /* 40 MHz */ 59u, /* 41 MHz */ 51u, - /* 42 MHz */ 44u, /* 43 MHz */ 36u, /* 44 MHz */ 29u, /* 45 MHz */ 23u, - /* 46 MHz */ 16u, /* 47 MHz */ 10u, /* 48 MHz */ 4u }; -#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ - /* Stored CY_SYS_CLK_IMO_TRIM4_REG when modified for USB lock */ #if (CY_IP_IMO_TRIMMABLE_BY_USB && CY_IP_SRSSV2) uint32 CySysClkImoTrim4 = 0u; @@ -91,6 +80,7 @@ uint32 CySysTickInitVar = 0u; /* Stored PUMP_SEL configuration during disable (IMO output by default) */ uint32 CySysClkPumpConfig = CY_SYS_CLK_PUMP_ENABLE; + /******************************************************************************* * Function Name: CySysClkImoStart ****************************************************************************//** @@ -220,7 +210,9 @@ void CySysClkImoStop(void) #endif /* (CY_IP_SRSSLT) */ #endif /* (CY_IP_SRSSV2) */ - + + CY_SYS_CLK_IMO_TRIM1_REG = 0; + /* For the WCO locking mode, the IMO gain needs to be CY_SYS_CLK_IMO_TRIM4_GAIN */ #if(CY_IP_SRSSV2) if ((CY_SYS_CLK_IMO_TRIM4_REG & CY_SYS_CLK_IMO_TRIM4_GAIN_MASK) == 0u) @@ -241,28 +233,25 @@ void CySysClkImoStop(void) /* Set DPLL Loop Filter Integral and Proportional Gains Setting */ regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_IGAIN | CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN); - /* Set maximum allowed IMO offset */ - if (freq < CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT) - { - regTmp |= (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); - } - else - { - lfLimit = (uint32) CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ) + - cyImoFreqMhz2DpllOffset[freq - CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET]; - - lfLimit = (lfLimit > CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX) ? - CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX : lfLimit; - - regTmp |= (lfLimit << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT); - } - CY_SYS_CLK_WCO_DPLL_REG = regTmp; - + flashCtlReg = CY_FLASH_CTL_REG; CySysFlashSetWaitCycles(CY_SYS_CLK_IMO_MAX_FREQ_MHZ); CY_SYS_CLK_WCO_CONFIG_REG |= CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; - CyDelay(CY_SYS_CLK_WCO_IMO_TIMEOUT_MS); + + regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + + while (lfLimit < (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX - CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_STEP)) + { + CyDelay(CY_SYS_CLK_WCO_DPLL_TIMEOUT_MS); + lfLimit += CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_STEP; + CY_SYS_CLK_WCO_DPLL_REG = (regTmp | (lfLimit << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)); + } + + CyDelay(CY_SYS_CLK_WCO_DPLL_TIMEOUT_MS); + CY_SYS_CLK_WCO_DPLL_REG = (regTmp | (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)); + CY_FLASH_CTL_REG = flashCtlReg; CyExitCriticalSection(interruptState); @@ -285,7 +274,44 @@ void CySysClkImoStop(void) *******************************************************************************/ void CySysClkImoDisableWcoLock(void) { + #if(CY_IP_SRSSV2) + uint32 i; + #endif /* (CY_IP_SRSSV2) */ + + uint32 freq; + + /* Get current IMO frequency based on the register value */ + #if(CY_IP_SRSSV2) + freq = CY_SYS_CLK_IMO_MIN_FREQ_MHZ; + for(i = 0u; i < CY_SYS_CLK_IMO_FREQ_TABLE_SIZE; i++) + { + if ((uint8) (CY_SYS_CLK_IMO_TRIM2_REG & CY_SYS_CLK_IMO_FREQ_BITS_MASK) == cyImoFreqMhz2Reg[i]) + { + freq = i + CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET; + break; + } + } + #else + /* Calculate frequency by shifting register field value and adding constant. */ + #if(CY_IP_SRSSLT) + freq = (((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ) >> + ((CY_SYS_CLK_SELECT_REG >> CY_SYS_CLK_SELECT_HFCLK_DIV_SHIFT) & + (uint32) CY_SYS_CLK_SELECT_HFCLK_DIV_MASK)); + #else + freq = ((uint32) ((CY_SYS_CLK_IMO_SELECT_REG & ((uint32) CY_SYS_CLK_IMO_SELECT_FREQ_MASK)) << + CY_SYS_CLK_IMO_SELECT_FREQ_SHIFT) + CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #endif /* (CY_IP_SRSSLT) */ + + #endif /* (CY_IP_SRSSV2) */ + CY_SYS_CLK_WCO_CONFIG_REG &= (uint32) ~CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE; + + #if(CY_IP_SRSSLT) + CY_SYS_CLK_IMO_TRIM1_REG = CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_MIN_FREQ_MHZ); + #else + CY_SYS_CLK_IMO_TRIM1_REG = CY_SFLASH_IMO_TRIM_REG(freq - CY_SYS_CLK_IMO_FREQ_TABLE_OFFSET); + #endif } diff --git a/BLE.cydsn/Generated_Source/PSoC4/CyLib.h b/BLE.cydsn/Generated_Source/PSoC4/CyLib.h index c818cc1..57a136e 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/CyLib.h +++ b/BLE.cydsn/Generated_Source/PSoC4/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, and interrupts. * @@ -744,11 +744,9 @@ extern uint32 CySysTickInitVar; #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN (( uint32 )(( uint32 ) 2u << CY_SYS_CLK_WCO_CONFIG_DPLL_LF_PGAIN_SHIFT)) #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX ((uint32) 0xFFu) + #define CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_STEP ((uint32) 16u) #define CY_SYS_CLK_WCO_IMO_TIMEOUT_MS ((uint32) 20u) - - #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_SAFE_POINT (26u) - #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_SIZE (23u) - #define CY_SYS_CLK_IMO_FREQ_WCO_DPLL_TABLE_OFFSET (26u) + #define CY_SYS_CLK_WCO_DPLL_TIMEOUT_MS ((uint32) 1u) #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/cm0gcc.ld b/BLE.cydsn/Generated_Source/PSoC4/cm0gcc.ld index 9fe9799..14cb2f2 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cm0gcc.ld +++ b/BLE.cydsn/Generated_Source/PSoC4/cm0gcc.ld @@ -28,13 +28,13 @@ INCLUDE cycodeshareimport.ld MEMORY { - rom (rx) : ORIGIN = 0x0, LENGTH = 262144 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32768 + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16384 } CY_APPL_ORIGIN = 0; -CY_FLASH_ROW_SIZE = 256; +CY_FLASH_ROW_SIZE = 128; CY_APPL_NUM = 1; CY_APPL_MAX = 1; CY_METADATA_SIZE = 64; diff --git a/BLE.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h b/BLE.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h index 51de779..1a66be2 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h +++ b/BLE.cydsn/Generated_Source/PSoC4/core_cm0_psoc4.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm0_psoc4.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSOC4 device family. * This includes types necessary for core_cm0.h. diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyPm.c b/BLE.cydsn/Generated_Source/PSoC4/cyPm.c index 3181e33..68610be 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyPm.c +++ b/BLE.cydsn/Generated_Source/PSoC4/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * @@ -71,6 +71,10 @@ void CySysPmDeepSleep(void) #if(CY_IP_ECO_SRSSLT) volatile uint32 pllResoreFlag = 0u; #endif /* (CY_IP_ECO_SRSSLT) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + uint32 regTmp = 0u; + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ interruptState = CyEnterCriticalSection(); @@ -92,6 +96,16 @@ void CySysPmDeepSleep(void) #if (CY_IP_CPUSS && CY_IP_SRSSV2) CY_PM_CPUSS_CONFIG_REG |= CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS; #endif /* (CY_IP_CPUSS && CY_IP_SRSSV2) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (0u != (CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE)) + { + regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + CY_SYS_CLK_WCO_DPLL_REG = (regTmp | (((CY_SYS_CLK_IMO_TRIM1_REG + CY_PM_WCO_DPLL_LF_LIMIT_TEMP_DRIFT) & + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX) << + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ /* Adjust delay to wait for references to settle on wakeup from Deep Sleep */ CY_PM_PWR_KEY_DELAY_REG = CY_SFLASH_DPSLP_KEY_DELAY_REG; @@ -114,6 +128,16 @@ void CySysPmDeepSleep(void) /* Restore system clock configuration */ CY_SYS_CLK_SELECT_REG = clkSelectReg; #endif /* (CY_IP_SRSSV2) */ + + #if (CY_IP_IMO_TRIMMABLE_BY_WCO) + if (0u != (CY_SYS_CLK_WCO_CONFIG_REG & CY_SYS_CLK_WCO_CONFIG_DPLL_ENABLE)) + { + CyDelayUs(CY_PM_WCO_DPLL_WAKEUP_DELAY); + regTmp = CY_SYS_CLK_WCO_DPLL_REG & ~(CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MASK); + CY_SYS_CLK_WCO_DPLL_REG = (regTmp | (CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_MAX << + CY_SYS_CLK_WCO_CONFIG_DPLL_LF_LIMIT_SHIFT)); + } + #endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ #if (CY_IP_CPUSS && CY_IP_SRSSV2) CY_PM_CPUSS_CONFIG_REG &= (uint32) (~CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS); diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyPm.h b/BLE.cydsn/Generated_Source/PSoC4/cyPm.h index 7b0641a..d30c0de 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyPm.h +++ b/BLE.cydsn/Generated_Source/PSoC4/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * @@ -202,6 +202,11 @@ void CySysPmDeepSleep(void); #define CY_PM_PWR_KEY_DELAY_FREQ_DEFAULT (48u) #endif /* (CY_IP_SRSSV2) */ +#if (CY_IP_IMO_TRIMMABLE_BY_WCO) + #define CY_PM_WCO_DPLL_WAKEUP_DELAY (35u) + #define CY_PM_WCO_DPLL_LF_LIMIT_TEMP_DRIFT (4u) +#endif /* (CY_IP_IMO_TRIMMABLE_BY_WCO) */ + #if (CY_PSOC4_4100 || CY_PSOC4_4200 || CY_PSOC4_4000U) /* 0 - normal operation, 1 - Flash Accelerator in bypass mode */ #define CY_PM_CPUSS_CONFIG_FLSH_ACC_BYPASS ((uint32) 0x02u) diff --git a/BLE.cydsn/Generated_Source/PSoC4/cydevice_trm.h b/BLE.cydsn/Generated_Source/PSoC4/cydevice_trm.h index d2c09f6..9bc2092 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cydevice_trm.h +++ b/BLE.cydsn/Generated_Source/PSoC4/cydevice_trm.h @@ -17,11 +17,11 @@ #if !defined(CYDEVICE_TRM_H) #define CYDEVICE_TRM_H #define CYDEV_FLASH_BASE 0x00000000u -#define CYDEV_FLASH_SIZE 0x00040000u +#define CYDEV_FLASH_SIZE 0x00020000u #define CYREG_FLASH_DATA_MBASE 0x00000000u -#define CYREG_FLASH_DATA_MSIZE 0x00040000u +#define CYREG_FLASH_DATA_MSIZE 0x00020000u #define CYDEV_SFLASH_BASE 0x0ffff000u -#define CYDEV_SFLASH_SIZE 0x00001000u +#define CYDEV_SFLASH_SIZE 0x00000800u #define CYREG_SFLASH_PROT_ROW0 0x0ffff000u #define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u #define CYFLD_SFLASH_DATA8__SIZE 0x00000008u @@ -88,102 +88,102 @@ #define CYREG_SFLASH_PROT_ROW61 0x0ffff03du #define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu #define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu -#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff0ffu +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07fu #define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u #define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u #define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u #define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u #define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u #define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u -#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff100u -#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff101u -#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff102u -#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff103u -#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff104u -#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff105u -#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff106u -#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff107u -#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff108u -#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff109u -#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff10au -#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff10bu -#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff10cu -#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff10du -#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff10eu -#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff10fu -#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff110u -#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff111u -#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff112u -#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff113u -#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff114u -#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff115u -#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff116u -#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff117u -#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff118u -#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff119u -#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff11au -#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff11bu -#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff11cu -#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff11du -#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff11eu -#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff11fu -#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff120u -#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff121u -#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff122u -#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff123u -#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff124u -#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff125u -#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff126u -#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff127u -#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff128u -#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff129u -#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff12au -#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff12bu -#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff12cu -#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff12du -#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff12eu -#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff12fu -#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff130u -#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff131u -#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff132u -#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff133u -#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff134u -#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff135u -#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff136u -#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff137u -#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff138u -#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff139u -#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff13au -#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff13bu -#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff13cu -#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff13du -#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff13eu -#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff13fu -#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff140u -#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff141u -#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff142u -#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff143u -#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff144u -#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff145u -#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff146u -#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff147u -#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff148u -#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff149u -#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff14au -#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff14bu -#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff14cu -#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff14du -#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff14eu -#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff14fu -#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff150u -#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff151u -#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff152u -#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff153u -#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff154u -#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff155u -#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff156u -#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff157u -#define CYREG_SFLASH_BLESS_BB_BUMP2 0x0ffff158u +#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff080u +#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff081u +#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff082u +#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff083u +#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff084u +#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff085u +#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff086u +#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff087u +#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff088u +#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff089u +#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff08au +#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff08bu +#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff08cu +#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff08du +#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff08eu +#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff08fu +#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff090u +#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff091u +#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff092u +#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff093u +#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff094u +#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff095u +#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff096u +#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff097u +#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff098u +#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff099u +#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff09au +#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff09bu +#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff09cu +#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff09du +#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff09eu +#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff09fu +#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff0a0u +#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff0a1u +#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff0a2u +#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff0a3u +#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff0a4u +#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff0a5u +#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff0a6u +#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff0a7u +#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff0a8u +#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff0a9u +#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff0aau +#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff0abu +#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff0acu +#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff0adu +#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff0aeu +#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff0afu +#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff0b0u +#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff0b1u +#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff0b2u +#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff0b3u +#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff0b4u +#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff0b5u +#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff0b6u +#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff0b7u +#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff0b8u +#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff0b9u +#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff0bau +#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff0bbu +#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff0bcu +#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff0bdu +#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff0beu +#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff0bfu +#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff0c0u +#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff0c1u +#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff0c2u +#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff0c3u +#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff0c4u +#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff0c5u +#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff0c6u +#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff0c7u +#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff0c8u +#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff0c9u +#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff0cau +#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff0cbu +#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff0ccu +#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff0cdu +#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff0ceu +#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff0cfu +#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff0d0u +#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff0d1u +#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff0d2u +#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff0d3u +#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff0d4u +#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff0d5u +#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff0d6u +#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff0d7u +#define CYREG_SFLASH_BLESS_BB_BUMP2 0x0ffff0d8u #define CYFLD_SFLASH_V2I_RCAL__OFFSET 0x00000000u #define CYFLD_SFLASH_V2I_RCAL__SIZE 0x00000005u #define CYFLD_SFLASH_V2I__OFFSET 0x00000005u @@ -192,9 +192,9 @@ #define CYFLD_SFLASH_VBG_TRIM__SIZE 0x00000003u #define CYFLD_SFLASH_SY_IBIAS__OFFSET 0x0000000du #define CYFLD_SFLASH_SY_IBIAS__SIZE 0x00000003u -#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff158u -#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff159u -#define CYREG_SFLASH_BLESS_BB_XO 0x0ffff15au +#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff0d8u +#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff0d9u +#define CYREG_SFLASH_BLESS_BB_XO 0x0ffff0dau #define CYFLD_SFLASH_DIS_XOCORE_SUPFILT__OFFSET 0x00000000u #define CYFLD_SFLASH_DIS_XOCORE_SUPFILT__SIZE 0x00000001u #define CYFLD_SFLASH_EN_RE_FASTSTART__OFFSET 0x00000001u @@ -215,10 +215,10 @@ #define CYFLD_SFLASH_CTRL_RPREF__SIZE 0x00000002u #define CYFLD_SFLASH_rev_bb_xo__OFFSET 0x0000000fu #define CYFLD_SFLASH_rev_bb_xo__SIZE 0x00000001u -#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff15au -#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff15bu -#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff15cu -#define CYREG_SFLASH_BLESS_SY_BUMP1 0x0ffff15cu +#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff0dau +#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff0dbu +#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff0dcu +#define CYREG_SFLASH_BLESS_SY_BUMP1 0x0ffff0dcu #define CYFLD_SFLASH_VCO__OFFSET 0x00000000u #define CYFLD_SFLASH_VCO__SIZE 0x00000004u #define CYFLD_SFLASH_LOFB_POWERSAVE__OFFSET 0x00000004u @@ -231,9 +231,9 @@ #define CYFLD_SFLASH_LOPATH__SIZE 0x00000004u #define CYFLD_SFLASH_PDCPLPF__OFFSET 0x0000000cu #define CYFLD_SFLASH_PDCPLPF__SIZE 0x00000004u -#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff15du -#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff15eu -#define CYREG_SFLASH_BLESS_LDO 0x0ffff15eu +#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff0ddu +#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff0deu +#define CYREG_SFLASH_BLESS_LDO 0x0ffff0deu #define CYFLD_SFLASH_BUMP_BALUM_HF__OFFSET 0x00000000u #define CYFLD_SFLASH_BUMP_BALUM_HF__SIZE 0x00000003u #define CYFLD_SFLASH_BUMP_SY_VCO__OFFSET 0x00000003u @@ -246,161 +246,115 @@ #define CYFLD_SFLASH_BUMP_SY_FFFB__SIZE 0x00000003u #define CYFLD_SFLASH_REV_LDO__OFFSET 0x0000000cu #define CYFLD_SFLASH_REV_LDO__SIZE 0x00000004u -#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff15fu -#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff160u -#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff161u -#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff162u -#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff163u -#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff164u -#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff165u -#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff166u -#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff167u -#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff168u -#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff169u -#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff16au -#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff16bu -#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff16cu -#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff16du -#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff16eu -#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff16fu -#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff170u -#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff171u -#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff172u -#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff173u -#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff174u -#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff175u -#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff176u -#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff177u -#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff178u -#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff179u -#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff17au -#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff17bu -#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff17cu -#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff17du -#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff17eu -#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff17fu -#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff200u +#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff0dfu +#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff0e0u +#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff0e1u +#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff0e2u +#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff0e3u +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4u +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5u +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6u +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7u +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8u +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9u +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0eau +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0ebu +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ecu +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0edu +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0eeu +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0efu +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0u +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1u +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2u +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3u +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4u +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5u +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6u +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7u +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8u +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9u +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fau +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fbu +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fcu +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fdu +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0feu +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ffu +#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff100u #define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u #define CYFLD_SFLASH_DATA32__SIZE 0x00000020u -#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff204u -#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff208u -#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff20cu -#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff210u -#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff214u -#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff218u -#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff21cu -#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff220u -#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff224u -#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff228u -#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff22cu -#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff230u -#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff234u -#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff238u -#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff23cu -#define CYREG_SFLASH_SILICON_ID 0x0ffff244u +#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff104u +#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff108u +#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff10cu +#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff110u +#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff114u +#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff118u +#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff11cu +#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff120u +#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff124u +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128u +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12cu +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130u +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134u +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138u +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13cu +#define CYREG_SFLASH_SILICON_ID 0x0ffff144u #define CYFLD_SFLASH_ID__OFFSET 0x00000000u #define CYFLD_SFLASH_ID__SIZE 0x00000010u -#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff250u +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150u #define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u #define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au -#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff252u -#define CYREG_SFLASH_SWD_CONFIG 0x0ffff254u +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152u +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154u #define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u #define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u -#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 0x0ffff255u +#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 0x0ffff155u #define CYFLD_SFLASH_IDAC__OFFSET 0x00000000u #define CYFLD_SFLASH_IDAC__SIZE 0x00000005u #define CYFLD_SFLASH_SLOPE__OFFSET 0x00000005u #define CYFLD_SFLASH_SLOPE__SIZE 0x00000003u -#define CYREG_SFLASH_SWD_LISTEN 0x0ffff258u +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158u #define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u #define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u -#define CYREG_SFLASH_FLASH_START 0x0ffff25cu +#define CYREG_SFLASH_FLASH_START 0x0ffff15cu #define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u #define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u -#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff260u +#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160u #define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000u #define CYFLD_SFLASH_TRIM8__SIZE 0x00000008u -#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff261u -#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff262u -#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff263u -#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff264u +#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161u +#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162u +#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163u +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164u #define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u #define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u -#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff266u +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166u #define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u #define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u -#define CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0 0x0ffff26cu -#define CYFLD_SFLASH_FCAL_BIAS_SEL__OFFSET 0x00000000u -#define CYFLD_SFLASH_FCAL_BIAS_SEL__SIZE 0x00000002u -#define CYFLD_SFLASH_ACAP_BIAS_SEL__OFFSET 0x00000002u -#define CYFLD_SFLASH_ACAP_BIAS_SEL__SIZE 0x00000002u -#define CYFLD_SFLASH_ICP_XFACTOR__OFFSET 0x00000004u -#define CYFLD_SFLASH_ICP_XFACTOR__SIZE 0x00000002u -#define CYFLD_SFLASH_ICP_OFFSET__OFFSET 0x00000006u -#define CYFLD_SFLASH_ICP_OFFSET__SIZE 0x00000002u -#define CYFLD_SFLASH_CLKNC_MODE__OFFSET 0x00000008u -#define CYFLD_SFLASH_CLKNC_MODE__SIZE 0x00000001u -#define CYFLD_SFLASH_PUP_MON__OFFSET 0x00000009u -#define CYFLD_SFLASH_PUP_MON__SIZE 0x00000001u -#define CYFLD_SFLASH_VCTRL_PULLDN__OFFSET 0x0000000au -#define CYFLD_SFLASH_VCTRL_PULLDN__SIZE 0x00000001u -#define CYFLD_SFLASH_VMOD_PULLDN__OFFSET 0x0000000bu -#define CYFLD_SFLASH_VMOD_PULLDN__SIZE 0x00000001u -#define CYFLD_SFLASH_RST_DLY__OFFSET 0x0000000cu -#define CYFLD_SFLASH_RST_DLY__SIZE 0x00000002u -#define CYFLD_SFLASH_PDCP_OFFSET__OFFSET 0x0000000eu -#define CYFLD_SFLASH_PDCP_OFFSET__SIZE 0x00000002u -#define CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1 0x0ffff26du -#define CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0 0x0ffff26eu -#define CYFLD_SFLASH_LNA_IBIAS__OFFSET 0x00000000u -#define CYFLD_SFLASH_LNA_IBIAS__SIZE 0x00000002u -#define CYFLD_SFLASH_TIA_IBIAS__OFFSET 0x00000002u -#define CYFLD_SFLASH_TIA_IBIAS__SIZE 0x00000002u -#define CYFLD_SFLASH_CBPF_IBIAS__OFFSET 0x00000004u -#define CYFLD_SFLASH_CBPF_IBIAS__SIZE 0x00000002u -#define CYFLD_SFLASH_IF_CM_IBIAS__OFFSET 0x00000006u -#define CYFLD_SFLASH_IF_CM_IBIAS__SIZE 0x00000002u -#define CYFLD_SFLASH_CBPF_HIZ_ENABLE__OFFSET 0x00000008u -#define CYFLD_SFLASH_CBPF_HIZ_ENABLE__SIZE 0x00000001u -#define CYFLD_SFLASH_COMPLEX_DISABLE__OFFSET 0x00000009u -#define CYFLD_SFLASH_COMPLEX_DISABLE__SIZE 0x00000001u -#define CYFLD_SFLASH_SY_R2HIGHMODE__OFFSET 0x0000000au -#define CYFLD_SFLASH_SY_R2HIGHMODE__SIZE 0x00000001u -#define CYFLD_SFLASH_SY_HILINEARITYR2_MODE__OFFSET 0x0000000bu -#define CYFLD_SFLASH_SY_HILINEARITYR2_MODE__SIZE 0x00000001u -#define CYFLD_SFLASH_SY_LOWKVAMODE__OFFSET 0x0000000cu -#define CYFLD_SFLASH_SY_LOWKVAMODE__SIZE 0x00000001u -#define CYFLD_SFLASH_SY_LOWKVMMODE__OFFSET 0x0000000du -#define CYFLD_SFLASH_SY_LOWKVMMODE__SIZE 0x00000001u -#define CYFLD_SFLASH_REV_RX_BUMP2__OFFSET 0x0000000eu -#define CYFLD_SFLASH_REV_RX_BUMP2__SIZE 0x00000002u -#define CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1 0x0ffff26fu -#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff270u +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170u #define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u #define CYFLD_SFLASH_KEY8__SIZE 0x00000008u -#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff271u -#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff272u -#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff273u -#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff274u -#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff275u -#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff276u -#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff277u -#define CYREG_SFLASH_DIE_LOT0 0x0ffff278u +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171u +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172u +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173u +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174u +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175u +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176u +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177u +#define CYREG_SFLASH_DIE_LOT0 0x0ffff178u #define CYFLD_SFLASH_LOT__OFFSET 0x00000000u #define CYFLD_SFLASH_LOT__SIZE 0x00000008u -#define CYREG_SFLASH_DIE_LOT1 0x0ffff279u -#define CYREG_SFLASH_DIE_LOT2 0x0ffff27au -#define CYREG_SFLASH_DIE_WAFER 0x0ffff27bu +#define CYREG_SFLASH_DIE_LOT1 0x0ffff179u +#define CYREG_SFLASH_DIE_LOT2 0x0ffff17au +#define CYREG_SFLASH_DIE_WAFER 0x0ffff17bu #define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u #define CYFLD_SFLASH_WAFER__SIZE 0x00000008u -#define CYREG_SFLASH_DIE_X 0x0ffff27cu +#define CYREG_SFLASH_DIE_X 0x0ffff17cu #define CYFLD_SFLASH_X__OFFSET 0x00000000u #define CYFLD_SFLASH_X__SIZE 0x00000008u -#define CYREG_SFLASH_DIE_Y 0x0ffff27du +#define CYREG_SFLASH_DIE_Y 0x0ffff17du #define CYFLD_SFLASH_Y__OFFSET 0x00000000u #define CYFLD_SFLASH_Y__SIZE 0x00000008u -#define CYREG_SFLASH_DIE_SORT 0x0ffff27eu +#define CYREG_SFLASH_DIE_SORT 0x0ffff17eu #define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u #define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001u #define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001u @@ -413,1392 +367,880 @@ #define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001u #define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005u #define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001u -#define CYREG_SFLASH_DIE_MINOR 0x0ffff27fu +#define CYREG_SFLASH_DIE_MINOR 0x0ffff17fu #define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u #define CYFLD_SFLASH_MINOR__SIZE 0x00000008u -#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff33eu +#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff1beu #define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000u #define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008u -#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff33fu -#define CYREG_SFLASH_IMO_MAXF0 0x0ffff340u +#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff1bfu +#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0u #define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000u #define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006u -#define CYREG_SFLASH_IMO_ABS0 0x0ffff341u +#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1u #define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000u #define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006u -#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff342u +#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2u #define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000u #define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006u -#define CYREG_SFLASH_IMO_MAXF1 0x0ffff343u -#define CYREG_SFLASH_IMO_ABS1 0x0ffff344u -#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff345u -#define CYREG_SFLASH_IMO_MAXF2 0x0ffff346u -#define CYREG_SFLASH_IMO_ABS2 0x0ffff347u -#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff348u -#define CYREG_SFLASH_IMO_MAXF3 0x0ffff349u -#define CYREG_SFLASH_IMO_ABS3 0x0ffff34au -#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff34bu -#define CYREG_SFLASH_IMO_ABS4 0x0ffff34cu -#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff34du -#define CYREG_SFLASH_IMO_TRIM0 0x0ffff350u +#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3u +#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4u +#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5u +#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6u +#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7u +#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8u +#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9u +#define CYREG_SFLASH_IMO_ABS3 0x0ffff1cau +#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cbu +#define CYREG_SFLASH_IMO_ABS4 0x0ffff1ccu +#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cdu +#define CYREG_SFLASH_IMO_TRIM0 0x0ffff1d0u #define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u #define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u -#define CYREG_SFLASH_IMO_TRIM1 0x0ffff351u -#define CYREG_SFLASH_IMO_TRIM2 0x0ffff352u -#define CYREG_SFLASH_IMO_TRIM3 0x0ffff353u -#define CYREG_SFLASH_IMO_TRIM4 0x0ffff354u -#define CYREG_SFLASH_IMO_TRIM5 0x0ffff355u -#define CYREG_SFLASH_IMO_TRIM6 0x0ffff356u -#define CYREG_SFLASH_IMO_TRIM7 0x0ffff357u -#define CYREG_SFLASH_IMO_TRIM8 0x0ffff358u -#define CYREG_SFLASH_IMO_TRIM9 0x0ffff359u -#define CYREG_SFLASH_IMO_TRIM10 0x0ffff35au -#define CYREG_SFLASH_IMO_TRIM11 0x0ffff35bu -#define CYREG_SFLASH_IMO_TRIM12 0x0ffff35cu -#define CYREG_SFLASH_IMO_TRIM13 0x0ffff35du -#define CYREG_SFLASH_IMO_TRIM14 0x0ffff35eu -#define CYREG_SFLASH_IMO_TRIM15 0x0ffff35fu -#define CYREG_SFLASH_IMO_TRIM16 0x0ffff360u -#define CYREG_SFLASH_IMO_TRIM17 0x0ffff361u -#define CYREG_SFLASH_IMO_TRIM18 0x0ffff362u -#define CYREG_SFLASH_IMO_TRIM19 0x0ffff363u -#define CYREG_SFLASH_IMO_TRIM20 0x0ffff364u -#define CYREG_SFLASH_IMO_TRIM21 0x0ffff365u -#define CYREG_SFLASH_IMO_TRIM22 0x0ffff366u -#define CYREG_SFLASH_IMO_TRIM23 0x0ffff367u -#define CYREG_SFLASH_IMO_TRIM24 0x0ffff368u -#define CYREG_SFLASH_IMO_TRIM25 0x0ffff369u -#define CYREG_SFLASH_IMO_TRIM26 0x0ffff36au -#define CYREG_SFLASH_IMO_TRIM27 0x0ffff36bu -#define CYREG_SFLASH_IMO_TRIM28 0x0ffff36cu -#define CYREG_SFLASH_IMO_TRIM29 0x0ffff36du -#define CYREG_SFLASH_IMO_TRIM30 0x0ffff36eu -#define CYREG_SFLASH_IMO_TRIM31 0x0ffff36fu -#define CYREG_SFLASH_IMO_TRIM32 0x0ffff370u -#define CYREG_SFLASH_IMO_TRIM33 0x0ffff371u -#define CYREG_SFLASH_IMO_TRIM34 0x0ffff372u -#define CYREG_SFLASH_IMO_TRIM35 0x0ffff373u -#define CYREG_SFLASH_IMO_TRIM36 0x0ffff374u -#define CYREG_SFLASH_IMO_TRIM37 0x0ffff375u -#define CYREG_SFLASH_IMO_TRIM38 0x0ffff376u -#define CYREG_SFLASH_IMO_TRIM39 0x0ffff377u -#define CYREG_SFLASH_IMO_TRIM40 0x0ffff378u -#define CYREG_SFLASH_IMO_TRIM41 0x0ffff379u -#define CYREG_SFLASH_IMO_TRIM42 0x0ffff37au -#define CYREG_SFLASH_IMO_TRIM43 0x0ffff37bu -#define CYREG_SFLASH_IMO_TRIM44 0x0ffff37cu -#define CYREG_SFLASH_IMO_TRIM45 0x0ffff37du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff400u +#define CYREG_SFLASH_IMO_TRIM1 0x0ffff1d1u +#define CYREG_SFLASH_IMO_TRIM2 0x0ffff1d2u +#define CYREG_SFLASH_IMO_TRIM3 0x0ffff1d3u +#define CYREG_SFLASH_IMO_TRIM4 0x0ffff1d4u +#define CYREG_SFLASH_IMO_TRIM5 0x0ffff1d5u +#define CYREG_SFLASH_IMO_TRIM6 0x0ffff1d6u +#define CYREG_SFLASH_IMO_TRIM7 0x0ffff1d7u +#define CYREG_SFLASH_IMO_TRIM8 0x0ffff1d8u +#define CYREG_SFLASH_IMO_TRIM9 0x0ffff1d9u +#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1dau +#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1dbu +#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dcu +#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1ddu +#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1deu +#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1dfu +#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0u +#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1u +#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2u +#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3u +#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4u +#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5u +#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6u +#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7u +#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8u +#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9u +#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1eau +#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1ebu +#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ecu +#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1edu +#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1eeu +#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1efu +#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0u +#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1u +#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2u +#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3u +#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4u +#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5u +#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6u +#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7u +#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8u +#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9u +#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fau +#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fbu +#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fcu +#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff200u #define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000u #define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff401u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff402u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff403u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff404u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff405u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff406u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff407u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff408u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff409u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff40au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff40bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff40cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff40du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff40eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff40fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff410u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff411u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff412u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff413u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff414u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff415u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff416u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff417u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff418u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff419u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff41au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff41bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff41cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff41du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff41eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff41fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff420u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff421u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff422u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff423u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff424u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff425u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff426u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff427u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff428u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff429u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff42au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff42bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff42cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff42du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff42eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff42fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff430u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff431u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff432u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff433u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff434u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff435u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff436u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff437u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff438u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff439u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff43au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff43bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff43cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff43du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff43eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff43fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff440u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff441u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff442u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff443u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff444u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff445u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff446u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff447u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff448u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff449u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff44au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff44bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff44cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff44du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff44eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff44fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff450u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff451u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff452u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff453u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff454u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff455u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff456u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff457u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff458u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff459u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff45au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff45bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff45cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff45du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff45eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff45fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff460u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff461u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff462u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff463u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff464u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff465u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff466u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff467u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff468u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff469u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff46au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff46bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff46cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff46du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff46eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff46fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff470u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff471u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff472u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff473u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff474u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff475u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff476u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff477u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff478u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff479u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff47au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff47bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff47cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff47du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff47eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff47fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff480u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff481u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff482u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff483u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff484u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff485u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff486u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff487u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff488u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff489u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff48au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff48bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff48cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff48du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff48eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff48fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff490u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff491u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff492u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff493u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff494u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff495u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff496u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff497u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff498u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff499u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff49au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff49bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff49cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff49du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff49eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff49fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff4a0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff4a1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff4a2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff4a3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff4a4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff4a5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff4a6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff4a7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff4a8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff4a9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff4aau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff4abu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff4acu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff4adu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff4aeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff4afu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff4b0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff4b1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff4b2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff4b3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff4b4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff4b5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff4b6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff4b7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff4b8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff4b9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff4bau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff4bbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff4bcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff4bdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff4beu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff4bfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff4c0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff4c1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff4c2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff4c3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff4c4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff4c5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff4c6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff4c7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff4c8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff4c9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff4cau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff4cbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff4ccu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff4cdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff4ceu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff4cfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff4d0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff4d1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff4d2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff4d3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff4d4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff4d5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff4d6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff4d7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff4d8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff4d9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff4dau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff4dbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff4dcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff4ddu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff4deu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff4dfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff4e0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff4e1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff4e2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff4e3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff4e4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff4e5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff4e6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff4e7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff4e8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff4e9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff4eau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff4ebu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff4ecu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff4edu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff4eeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff4efu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff4f0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff4f1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff4f2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff4f3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff4f4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff4f5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff4f6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff4f7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff4f8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff4f9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff4fau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff4fbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff4fcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff4fdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff4feu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff4ffu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff500u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff501u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff502u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff503u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff504u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff505u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff506u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff507u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff508u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff509u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff50au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff50bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff50cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff50du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff50eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff50fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff510u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff511u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff512u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff513u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff514u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff515u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff516u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff517u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff518u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff519u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff51au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff51bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff51cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff51du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff51eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff51fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff520u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff521u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff522u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff523u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff524u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff525u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff526u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff527u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff528u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff529u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff52au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff52bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff52cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff52du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff52eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff52fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff530u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff531u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff532u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff533u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff534u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff535u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff536u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff537u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff538u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff539u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff53au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff53bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff53cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff53du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff53eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff53fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff540u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff541u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff542u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff543u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff544u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff545u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff546u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff547u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff548u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff549u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff54au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff54bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff54cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff54du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff54eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff54fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff550u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff551u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff552u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff553u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff554u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff555u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff556u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff557u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff558u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff559u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff55au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff55bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff55cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff55du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff55eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff55fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff560u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff561u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff562u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff563u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff564u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff565u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff566u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff567u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff568u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff569u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff56au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff56bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff56cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff56du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff56eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff56fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff570u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff571u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff572u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff573u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff574u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff575u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff576u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff577u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff578u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff579u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff57au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff57bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff57cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff57du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff57eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff57fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff580u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff581u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff582u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff583u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff584u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff585u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff586u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff587u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff588u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff589u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff58au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff58bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff58cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff58du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff58eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff58fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff590u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff591u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff592u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff593u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff594u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff595u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff596u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff597u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff598u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff599u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff59au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff59bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff59cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff59du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff59eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff59fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff5a0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff5a1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff5a2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff5a3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff5a4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff5a5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff5a6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff5a7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff5a8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff5a9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff5aau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff5abu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff5acu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff5adu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff5aeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff5afu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff5b0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff5b1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff5b2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff5b3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff5b4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff5b5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff5b6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff5b7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff5b8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff5b9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff5bau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff5bbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff5bcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff5bdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff5beu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff5bfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff5c0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff5c1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff5c2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff5c3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff5c4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff5c5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff5c6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff5c7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff5c8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff5c9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff5cau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff5cbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff5ccu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff5cdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff5ceu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff5cfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff5d0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff5d1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff5d2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff5d3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff5d4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff5d5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff5d6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff5d7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff5d8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff5d9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff5dau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff5dbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff5dcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff5ddu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff5deu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff5dfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff5e0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff5e1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff5e2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff5e3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff5e4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff5e5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff5e6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff5e7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff5e8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff5e9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff5eau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff5ebu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff5ecu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff5edu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff5eeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff5efu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff5f0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff5f1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff5f2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff5f3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff5f4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff5f5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff5f6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff5f7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff5f8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff5f9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff5fau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff5fbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff5fcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff5fdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff5feu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff5ffu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH512 0x0ffff600u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH513 0x0ffff601u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH514 0x0ffff602u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH515 0x0ffff603u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH516 0x0ffff604u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH517 0x0ffff605u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH518 0x0ffff606u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH519 0x0ffff607u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH520 0x0ffff608u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH521 0x0ffff609u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH522 0x0ffff60au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH523 0x0ffff60bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH524 0x0ffff60cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH525 0x0ffff60du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH526 0x0ffff60eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH527 0x0ffff60fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH528 0x0ffff610u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH529 0x0ffff611u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH530 0x0ffff612u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH531 0x0ffff613u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH532 0x0ffff614u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH533 0x0ffff615u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH534 0x0ffff616u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH535 0x0ffff617u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH536 0x0ffff618u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH537 0x0ffff619u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH538 0x0ffff61au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH539 0x0ffff61bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH540 0x0ffff61cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH541 0x0ffff61du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH542 0x0ffff61eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH543 0x0ffff61fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH544 0x0ffff620u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH545 0x0ffff621u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH546 0x0ffff622u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH547 0x0ffff623u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH548 0x0ffff624u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH549 0x0ffff625u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH550 0x0ffff626u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH551 0x0ffff627u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH552 0x0ffff628u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH553 0x0ffff629u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH554 0x0ffff62au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH555 0x0ffff62bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH556 0x0ffff62cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH557 0x0ffff62du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH558 0x0ffff62eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH559 0x0ffff62fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH560 0x0ffff630u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH561 0x0ffff631u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH562 0x0ffff632u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH563 0x0ffff633u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH564 0x0ffff634u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH565 0x0ffff635u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH566 0x0ffff636u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH567 0x0ffff637u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH568 0x0ffff638u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH569 0x0ffff639u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH570 0x0ffff63au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH571 0x0ffff63bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH572 0x0ffff63cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH573 0x0ffff63du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH574 0x0ffff63eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH575 0x0ffff63fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH576 0x0ffff640u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH577 0x0ffff641u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH578 0x0ffff642u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH579 0x0ffff643u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH580 0x0ffff644u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH581 0x0ffff645u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH582 0x0ffff646u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH583 0x0ffff647u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH584 0x0ffff648u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH585 0x0ffff649u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH586 0x0ffff64au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH587 0x0ffff64bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH588 0x0ffff64cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH589 0x0ffff64du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH590 0x0ffff64eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH591 0x0ffff64fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH592 0x0ffff650u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH593 0x0ffff651u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH594 0x0ffff652u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH595 0x0ffff653u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH596 0x0ffff654u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH597 0x0ffff655u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH598 0x0ffff656u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH599 0x0ffff657u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH600 0x0ffff658u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH601 0x0ffff659u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH602 0x0ffff65au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH603 0x0ffff65bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH604 0x0ffff65cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH605 0x0ffff65du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH606 0x0ffff65eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH607 0x0ffff65fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH608 0x0ffff660u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH609 0x0ffff661u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH610 0x0ffff662u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH611 0x0ffff663u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH612 0x0ffff664u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH613 0x0ffff665u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH614 0x0ffff666u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH615 0x0ffff667u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH616 0x0ffff668u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH617 0x0ffff669u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH618 0x0ffff66au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH619 0x0ffff66bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH620 0x0ffff66cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH621 0x0ffff66du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH622 0x0ffff66eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH623 0x0ffff66fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH624 0x0ffff670u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH625 0x0ffff671u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH626 0x0ffff672u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH627 0x0ffff673u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH628 0x0ffff674u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH629 0x0ffff675u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH630 0x0ffff676u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH631 0x0ffff677u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH632 0x0ffff678u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH633 0x0ffff679u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH634 0x0ffff67au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH635 0x0ffff67bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH636 0x0ffff67cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH637 0x0ffff67du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH638 0x0ffff67eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH639 0x0ffff67fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH640 0x0ffff680u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH641 0x0ffff681u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH642 0x0ffff682u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH643 0x0ffff683u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH644 0x0ffff684u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH645 0x0ffff685u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH646 0x0ffff686u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH647 0x0ffff687u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH648 0x0ffff688u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH649 0x0ffff689u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH650 0x0ffff68au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH651 0x0ffff68bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH652 0x0ffff68cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH653 0x0ffff68du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH654 0x0ffff68eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH655 0x0ffff68fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH656 0x0ffff690u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH657 0x0ffff691u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH658 0x0ffff692u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH659 0x0ffff693u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH660 0x0ffff694u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH661 0x0ffff695u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH662 0x0ffff696u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH663 0x0ffff697u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH664 0x0ffff698u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH665 0x0ffff699u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH666 0x0ffff69au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH667 0x0ffff69bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH668 0x0ffff69cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH669 0x0ffff69du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH670 0x0ffff69eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH671 0x0ffff69fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH672 0x0ffff6a0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH673 0x0ffff6a1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH674 0x0ffff6a2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH675 0x0ffff6a3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH676 0x0ffff6a4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH677 0x0ffff6a5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH678 0x0ffff6a6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH679 0x0ffff6a7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH680 0x0ffff6a8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH681 0x0ffff6a9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH682 0x0ffff6aau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH683 0x0ffff6abu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH684 0x0ffff6acu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH685 0x0ffff6adu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH686 0x0ffff6aeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH687 0x0ffff6afu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH688 0x0ffff6b0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH689 0x0ffff6b1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH690 0x0ffff6b2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH691 0x0ffff6b3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH692 0x0ffff6b4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH693 0x0ffff6b5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH694 0x0ffff6b6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH695 0x0ffff6b7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH696 0x0ffff6b8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH697 0x0ffff6b9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH698 0x0ffff6bau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH699 0x0ffff6bbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH700 0x0ffff6bcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH701 0x0ffff6bdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH702 0x0ffff6beu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH703 0x0ffff6bfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH704 0x0ffff6c0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH705 0x0ffff6c1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH706 0x0ffff6c2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH707 0x0ffff6c3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH708 0x0ffff6c4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH709 0x0ffff6c5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH710 0x0ffff6c6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH711 0x0ffff6c7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH712 0x0ffff6c8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH713 0x0ffff6c9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH714 0x0ffff6cau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH715 0x0ffff6cbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH716 0x0ffff6ccu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH717 0x0ffff6cdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH718 0x0ffff6ceu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH719 0x0ffff6cfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH720 0x0ffff6d0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH721 0x0ffff6d1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH722 0x0ffff6d2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH723 0x0ffff6d3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH724 0x0ffff6d4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH725 0x0ffff6d5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH726 0x0ffff6d6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH727 0x0ffff6d7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH728 0x0ffff6d8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH729 0x0ffff6d9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH730 0x0ffff6dau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH731 0x0ffff6dbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH732 0x0ffff6dcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH733 0x0ffff6ddu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH734 0x0ffff6deu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH735 0x0ffff6dfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH736 0x0ffff6e0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH737 0x0ffff6e1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH738 0x0ffff6e2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH739 0x0ffff6e3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH740 0x0ffff6e4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH741 0x0ffff6e5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH742 0x0ffff6e6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH743 0x0ffff6e7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH744 0x0ffff6e8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH745 0x0ffff6e9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH746 0x0ffff6eau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH747 0x0ffff6ebu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH748 0x0ffff6ecu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH749 0x0ffff6edu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH750 0x0ffff6eeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH751 0x0ffff6efu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH752 0x0ffff6f0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH753 0x0ffff6f1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH754 0x0ffff6f2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH755 0x0ffff6f3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH756 0x0ffff6f4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH757 0x0ffff6f5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH758 0x0ffff6f6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH759 0x0ffff6f7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH760 0x0ffff6f8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH761 0x0ffff6f9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH762 0x0ffff6fau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH763 0x0ffff6fbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH764 0x0ffff6fcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH765 0x0ffff6fdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH766 0x0ffff6feu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH767 0x0ffff6ffu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH768 0x0ffff700u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH769 0x0ffff701u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH770 0x0ffff702u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH771 0x0ffff703u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH772 0x0ffff704u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH773 0x0ffff705u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH774 0x0ffff706u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH775 0x0ffff707u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH776 0x0ffff708u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH777 0x0ffff709u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH778 0x0ffff70au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH779 0x0ffff70bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH780 0x0ffff70cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH781 0x0ffff70du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH782 0x0ffff70eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH783 0x0ffff70fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH784 0x0ffff710u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH785 0x0ffff711u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH786 0x0ffff712u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH787 0x0ffff713u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH788 0x0ffff714u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH789 0x0ffff715u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH790 0x0ffff716u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH791 0x0ffff717u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH792 0x0ffff718u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH793 0x0ffff719u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH794 0x0ffff71au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH795 0x0ffff71bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH796 0x0ffff71cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH797 0x0ffff71du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH798 0x0ffff71eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH799 0x0ffff71fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH800 0x0ffff720u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH801 0x0ffff721u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH802 0x0ffff722u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH803 0x0ffff723u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH804 0x0ffff724u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH805 0x0ffff725u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH806 0x0ffff726u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH807 0x0ffff727u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH808 0x0ffff728u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH809 0x0ffff729u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH810 0x0ffff72au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH811 0x0ffff72bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH812 0x0ffff72cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH813 0x0ffff72du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH814 0x0ffff72eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH815 0x0ffff72fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH816 0x0ffff730u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH817 0x0ffff731u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH818 0x0ffff732u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH819 0x0ffff733u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH820 0x0ffff734u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH821 0x0ffff735u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH822 0x0ffff736u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH823 0x0ffff737u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH824 0x0ffff738u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH825 0x0ffff739u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH826 0x0ffff73au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH827 0x0ffff73bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH828 0x0ffff73cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH829 0x0ffff73du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH830 0x0ffff73eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH831 0x0ffff73fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH832 0x0ffff740u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH833 0x0ffff741u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH834 0x0ffff742u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH835 0x0ffff743u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH836 0x0ffff744u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH837 0x0ffff745u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH838 0x0ffff746u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH839 0x0ffff747u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH840 0x0ffff748u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH841 0x0ffff749u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH842 0x0ffff74au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH843 0x0ffff74bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH844 0x0ffff74cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH845 0x0ffff74du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH846 0x0ffff74eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH847 0x0ffff74fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH848 0x0ffff750u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH849 0x0ffff751u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH850 0x0ffff752u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH851 0x0ffff753u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH852 0x0ffff754u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH853 0x0ffff755u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH854 0x0ffff756u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH855 0x0ffff757u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH856 0x0ffff758u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH857 0x0ffff759u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH858 0x0ffff75au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH859 0x0ffff75bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH860 0x0ffff75cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH861 0x0ffff75du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH862 0x0ffff75eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH863 0x0ffff75fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH864 0x0ffff760u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH865 0x0ffff761u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH866 0x0ffff762u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH867 0x0ffff763u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH868 0x0ffff764u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH869 0x0ffff765u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH870 0x0ffff766u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH871 0x0ffff767u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH872 0x0ffff768u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH873 0x0ffff769u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH874 0x0ffff76au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH875 0x0ffff76bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH876 0x0ffff76cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH877 0x0ffff76du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH878 0x0ffff76eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH879 0x0ffff76fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH880 0x0ffff770u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH881 0x0ffff771u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH882 0x0ffff772u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH883 0x0ffff773u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH884 0x0ffff774u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH885 0x0ffff775u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH886 0x0ffff776u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH887 0x0ffff777u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH888 0x0ffff778u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH889 0x0ffff779u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH890 0x0ffff77au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH891 0x0ffff77bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH892 0x0ffff77cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH893 0x0ffff77du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH894 0x0ffff77eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH895 0x0ffff77fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH896 0x0ffff780u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH897 0x0ffff781u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH898 0x0ffff782u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH899 0x0ffff783u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH900 0x0ffff784u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH901 0x0ffff785u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH902 0x0ffff786u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH903 0x0ffff787u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH904 0x0ffff788u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH905 0x0ffff789u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH906 0x0ffff78au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH907 0x0ffff78bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH908 0x0ffff78cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH909 0x0ffff78du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH910 0x0ffff78eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH911 0x0ffff78fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH912 0x0ffff790u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH913 0x0ffff791u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH914 0x0ffff792u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH915 0x0ffff793u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH916 0x0ffff794u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH917 0x0ffff795u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH918 0x0ffff796u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH919 0x0ffff797u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH920 0x0ffff798u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH921 0x0ffff799u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH922 0x0ffff79au -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH923 0x0ffff79bu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH924 0x0ffff79cu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH925 0x0ffff79du -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH926 0x0ffff79eu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH927 0x0ffff79fu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH928 0x0ffff7a0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH929 0x0ffff7a1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH930 0x0ffff7a2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH931 0x0ffff7a3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH932 0x0ffff7a4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH933 0x0ffff7a5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH934 0x0ffff7a6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH935 0x0ffff7a7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH936 0x0ffff7a8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH937 0x0ffff7a9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH938 0x0ffff7aau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH939 0x0ffff7abu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH940 0x0ffff7acu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH941 0x0ffff7adu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH942 0x0ffff7aeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH943 0x0ffff7afu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH944 0x0ffff7b0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH945 0x0ffff7b1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH946 0x0ffff7b2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH947 0x0ffff7b3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH948 0x0ffff7b4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH949 0x0ffff7b5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH950 0x0ffff7b6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH951 0x0ffff7b7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH952 0x0ffff7b8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH953 0x0ffff7b9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH954 0x0ffff7bau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH955 0x0ffff7bbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH956 0x0ffff7bcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH957 0x0ffff7bdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH958 0x0ffff7beu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH959 0x0ffff7bfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH960 0x0ffff7c0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH961 0x0ffff7c1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH962 0x0ffff7c2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH963 0x0ffff7c3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH964 0x0ffff7c4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH965 0x0ffff7c5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH966 0x0ffff7c6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH967 0x0ffff7c7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH968 0x0ffff7c8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH969 0x0ffff7c9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH970 0x0ffff7cau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH971 0x0ffff7cbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH972 0x0ffff7ccu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH973 0x0ffff7cdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH974 0x0ffff7ceu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH975 0x0ffff7cfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH976 0x0ffff7d0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH977 0x0ffff7d1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH978 0x0ffff7d2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH979 0x0ffff7d3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH980 0x0ffff7d4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH981 0x0ffff7d5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH982 0x0ffff7d6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH983 0x0ffff7d7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH984 0x0ffff7d8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH985 0x0ffff7d9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH986 0x0ffff7dau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH987 0x0ffff7dbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH988 0x0ffff7dcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH989 0x0ffff7ddu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH990 0x0ffff7deu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH991 0x0ffff7dfu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH992 0x0ffff7e0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH993 0x0ffff7e1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH994 0x0ffff7e2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH995 0x0ffff7e3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH996 0x0ffff7e4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH997 0x0ffff7e5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH998 0x0ffff7e6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH999 0x0ffff7e7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 0x0ffff7e8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 0x0ffff7e9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 0x0ffff7eau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 0x0ffff7ebu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 0x0ffff7ecu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 0x0ffff7edu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 0x0ffff7eeu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 0x0ffff7efu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 0x0ffff7f0u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 0x0ffff7f1u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 0x0ffff7f2u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 0x0ffff7f3u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 0x0ffff7f4u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 0x0ffff7f5u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 0x0ffff7f6u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 0x0ffff7f7u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 0x0ffff7f8u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 0x0ffff7f9u -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 0x0ffff7fau -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 0x0ffff7fbu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 0x0ffff7fcu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 0x0ffff7fdu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 0x0ffff7feu -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 0x0ffff7ffu -#define CYREG_SFLASH_ALT_PROT_ROW0 0x0ffff800u -#define CYREG_SFLASH_ALT_PROT_ROW1 0x0ffff801u -#define CYREG_SFLASH_ALT_PROT_ROW2 0x0ffff802u -#define CYREG_SFLASH_ALT_PROT_ROW3 0x0ffff803u -#define CYREG_SFLASH_ALT_PROT_ROW4 0x0ffff804u -#define CYREG_SFLASH_ALT_PROT_ROW5 0x0ffff805u -#define CYREG_SFLASH_ALT_PROT_ROW6 0x0ffff806u -#define CYREG_SFLASH_ALT_PROT_ROW7 0x0ffff807u -#define CYREG_SFLASH_ALT_PROT_ROW8 0x0ffff808u -#define CYREG_SFLASH_ALT_PROT_ROW9 0x0ffff809u -#define CYREG_SFLASH_ALT_PROT_ROW10 0x0ffff80au -#define CYREG_SFLASH_ALT_PROT_ROW11 0x0ffff80bu -#define CYREG_SFLASH_ALT_PROT_ROW12 0x0ffff80cu -#define CYREG_SFLASH_ALT_PROT_ROW13 0x0ffff80du -#define CYREG_SFLASH_ALT_PROT_ROW14 0x0ffff80eu -#define CYREG_SFLASH_ALT_PROT_ROW15 0x0ffff80fu -#define CYREG_SFLASH_ALT_PROT_ROW16 0x0ffff810u -#define CYREG_SFLASH_ALT_PROT_ROW17 0x0ffff811u -#define CYREG_SFLASH_ALT_PROT_ROW18 0x0ffff812u -#define CYREG_SFLASH_ALT_PROT_ROW19 0x0ffff813u -#define CYREG_SFLASH_ALT_PROT_ROW20 0x0ffff814u -#define CYREG_SFLASH_ALT_PROT_ROW21 0x0ffff815u -#define CYREG_SFLASH_ALT_PROT_ROW22 0x0ffff816u -#define CYREG_SFLASH_ALT_PROT_ROW23 0x0ffff817u -#define CYREG_SFLASH_ALT_PROT_ROW24 0x0ffff818u -#define CYREG_SFLASH_ALT_PROT_ROW25 0x0ffff819u -#define CYREG_SFLASH_ALT_PROT_ROW26 0x0ffff81au -#define CYREG_SFLASH_ALT_PROT_ROW27 0x0ffff81bu -#define CYREG_SFLASH_ALT_PROT_ROW28 0x0ffff81cu -#define CYREG_SFLASH_ALT_PROT_ROW29 0x0ffff81du -#define CYREG_SFLASH_ALT_PROT_ROW30 0x0ffff81eu -#define CYREG_SFLASH_ALT_PROT_ROW31 0x0ffff81fu -#define CYREG_SFLASH_ALT_PROT_ROW32 0x0ffff820u -#define CYREG_SFLASH_ALT_PROT_ROW33 0x0ffff821u -#define CYREG_SFLASH_ALT_PROT_ROW34 0x0ffff822u -#define CYREG_SFLASH_ALT_PROT_ROW35 0x0ffff823u -#define CYREG_SFLASH_ALT_PROT_ROW36 0x0ffff824u -#define CYREG_SFLASH_ALT_PROT_ROW37 0x0ffff825u -#define CYREG_SFLASH_ALT_PROT_ROW38 0x0ffff826u -#define CYREG_SFLASH_ALT_PROT_ROW39 0x0ffff827u -#define CYREG_SFLASH_ALT_PROT_ROW40 0x0ffff828u -#define CYREG_SFLASH_ALT_PROT_ROW41 0x0ffff829u -#define CYREG_SFLASH_ALT_PROT_ROW42 0x0ffff82au -#define CYREG_SFLASH_ALT_PROT_ROW43 0x0ffff82bu -#define CYREG_SFLASH_ALT_PROT_ROW44 0x0ffff82cu -#define CYREG_SFLASH_ALT_PROT_ROW45 0x0ffff82du -#define CYREG_SFLASH_ALT_PROT_ROW46 0x0ffff82eu -#define CYREG_SFLASH_ALT_PROT_ROW47 0x0ffff82fu -#define CYREG_SFLASH_ALT_PROT_ROW48 0x0ffff830u -#define CYREG_SFLASH_ALT_PROT_ROW49 0x0ffff831u -#define CYREG_SFLASH_ALT_PROT_ROW50 0x0ffff832u -#define CYREG_SFLASH_ALT_PROT_ROW51 0x0ffff833u -#define CYREG_SFLASH_ALT_PROT_ROW52 0x0ffff834u -#define CYREG_SFLASH_ALT_PROT_ROW53 0x0ffff835u -#define CYREG_SFLASH_ALT_PROT_ROW54 0x0ffff836u -#define CYREG_SFLASH_ALT_PROT_ROW55 0x0ffff837u -#define CYREG_SFLASH_ALT_PROT_ROW56 0x0ffff838u -#define CYREG_SFLASH_ALT_PROT_ROW57 0x0ffff839u -#define CYREG_SFLASH_ALT_PROT_ROW58 0x0ffff83au -#define CYREG_SFLASH_ALT_PROT_ROW59 0x0ffff83bu -#define CYREG_SFLASH_ALT_PROT_ROW60 0x0ffff83cu -#define CYREG_SFLASH_ALT_PROT_ROW61 0x0ffff83du -#define CYREG_SFLASH_ALT_PROT_ROW62 0x0ffff83eu -#define CYREG_SFLASH_ALT_PROT_ROW63 0x0ffff83fu -#define CYREG_SFLASH_ALT_PROT_ROW64 0x0ffff840u -#define CYREG_SFLASH_ALT_PROT_ROW65 0x0ffff841u -#define CYREG_SFLASH_ALT_PROT_ROW66 0x0ffff842u -#define CYREG_SFLASH_ALT_PROT_ROW67 0x0ffff843u -#define CYREG_SFLASH_ALT_PROT_ROW68 0x0ffff844u -#define CYREG_SFLASH_ALT_PROT_ROW69 0x0ffff845u -#define CYREG_SFLASH_ALT_PROT_ROW70 0x0ffff846u -#define CYREG_SFLASH_ALT_PROT_ROW71 0x0ffff847u -#define CYREG_SFLASH_ALT_PROT_ROW72 0x0ffff848u -#define CYREG_SFLASH_ALT_PROT_ROW73 0x0ffff849u -#define CYREG_SFLASH_ALT_PROT_ROW74 0x0ffff84au -#define CYREG_SFLASH_ALT_PROT_ROW75 0x0ffff84bu -#define CYREG_SFLASH_ALT_PROT_ROW76 0x0ffff84cu -#define CYREG_SFLASH_ALT_PROT_ROW77 0x0ffff84du -#define CYREG_SFLASH_ALT_PROT_ROW78 0x0ffff84eu -#define CYREG_SFLASH_ALT_PROT_ROW79 0x0ffff84fu -#define CYREG_SFLASH_ALT_PROT_ROW80 0x0ffff850u -#define CYREG_SFLASH_ALT_PROT_ROW81 0x0ffff851u -#define CYREG_SFLASH_ALT_PROT_ROW82 0x0ffff852u -#define CYREG_SFLASH_ALT_PROT_ROW83 0x0ffff853u -#define CYREG_SFLASH_ALT_PROT_ROW84 0x0ffff854u -#define CYREG_SFLASH_ALT_PROT_ROW85 0x0ffff855u -#define CYREG_SFLASH_ALT_PROT_ROW86 0x0ffff856u -#define CYREG_SFLASH_ALT_PROT_ROW87 0x0ffff857u -#define CYREG_SFLASH_ALT_PROT_ROW88 0x0ffff858u -#define CYREG_SFLASH_ALT_PROT_ROW89 0x0ffff859u -#define CYREG_SFLASH_ALT_PROT_ROW90 0x0ffff85au -#define CYREG_SFLASH_ALT_PROT_ROW91 0x0ffff85bu -#define CYREG_SFLASH_ALT_PROT_ROW92 0x0ffff85cu -#define CYREG_SFLASH_ALT_PROT_ROW93 0x0ffff85du -#define CYREG_SFLASH_ALT_PROT_ROW94 0x0ffff85eu -#define CYREG_SFLASH_ALT_PROT_ROW95 0x0ffff85fu -#define CYREG_SFLASH_ALT_PROT_ROW96 0x0ffff860u -#define CYREG_SFLASH_ALT_PROT_ROW97 0x0ffff861u -#define CYREG_SFLASH_ALT_PROT_ROW98 0x0ffff862u -#define CYREG_SFLASH_ALT_PROT_ROW99 0x0ffff863u -#define CYREG_SFLASH_ALT_PROT_ROW100 0x0ffff864u -#define CYREG_SFLASH_ALT_PROT_ROW101 0x0ffff865u -#define CYREG_SFLASH_ALT_PROT_ROW102 0x0ffff866u -#define CYREG_SFLASH_ALT_PROT_ROW103 0x0ffff867u -#define CYREG_SFLASH_ALT_PROT_ROW104 0x0ffff868u -#define CYREG_SFLASH_ALT_PROT_ROW105 0x0ffff869u -#define CYREG_SFLASH_ALT_PROT_ROW106 0x0ffff86au -#define CYREG_SFLASH_ALT_PROT_ROW107 0x0ffff86bu -#define CYREG_SFLASH_ALT_PROT_ROW108 0x0ffff86cu -#define CYREG_SFLASH_ALT_PROT_ROW109 0x0ffff86du -#define CYREG_SFLASH_ALT_PROT_ROW110 0x0ffff86eu -#define CYREG_SFLASH_ALT_PROT_ROW111 0x0ffff86fu -#define CYREG_SFLASH_ALT_PROT_ROW112 0x0ffff870u -#define CYREG_SFLASH_ALT_PROT_ROW113 0x0ffff871u -#define CYREG_SFLASH_ALT_PROT_ROW114 0x0ffff872u -#define CYREG_SFLASH_ALT_PROT_ROW115 0x0ffff873u -#define CYREG_SFLASH_ALT_PROT_ROW116 0x0ffff874u -#define CYREG_SFLASH_ALT_PROT_ROW117 0x0ffff875u -#define CYREG_SFLASH_ALT_PROT_ROW118 0x0ffff876u -#define CYREG_SFLASH_ALT_PROT_ROW119 0x0ffff877u -#define CYREG_SFLASH_ALT_PROT_ROW120 0x0ffff878u -#define CYREG_SFLASH_ALT_PROT_ROW121 0x0ffff879u -#define CYREG_SFLASH_ALT_PROT_ROW122 0x0ffff87au -#define CYREG_SFLASH_ALT_PROT_ROW123 0x0ffff87bu -#define CYREG_SFLASH_ALT_PROT_ROW124 0x0ffff87cu -#define CYREG_SFLASH_ALT_PROT_ROW125 0x0ffff87du -#define CYREG_SFLASH_ALT_PROT_ROW126 0x0ffff87eu -#define CYREG_SFLASH_ALT_PROT_ROW127 0x0ffff87fu -#define CYREG_SFLASH_ALT_PROT_ROW128 0x0ffff880u -#define CYREG_SFLASH_ALT_PROT_ROW129 0x0ffff881u -#define CYREG_SFLASH_ALT_PROT_ROW130 0x0ffff882u -#define CYREG_SFLASH_ALT_PROT_ROW131 0x0ffff883u -#define CYREG_SFLASH_ALT_PROT_ROW132 0x0ffff884u -#define CYREG_SFLASH_ALT_PROT_ROW133 0x0ffff885u -#define CYREG_SFLASH_ALT_PROT_ROW134 0x0ffff886u -#define CYREG_SFLASH_ALT_PROT_ROW135 0x0ffff887u -#define CYREG_SFLASH_ALT_PROT_ROW136 0x0ffff888u -#define CYREG_SFLASH_ALT_PROT_ROW137 0x0ffff889u -#define CYREG_SFLASH_ALT_PROT_ROW138 0x0ffff88au -#define CYREG_SFLASH_ALT_PROT_ROW139 0x0ffff88bu -#define CYREG_SFLASH_ALT_PROT_ROW140 0x0ffff88cu -#define CYREG_SFLASH_ALT_PROT_ROW141 0x0ffff88du -#define CYREG_SFLASH_ALT_PROT_ROW142 0x0ffff88eu -#define CYREG_SFLASH_ALT_PROT_ROW143 0x0ffff88fu -#define CYREG_SFLASH_ALT_PROT_ROW144 0x0ffff890u -#define CYREG_SFLASH_ALT_PROT_ROW145 0x0ffff891u -#define CYREG_SFLASH_ALT_PROT_ROW146 0x0ffff892u -#define CYREG_SFLASH_ALT_PROT_ROW147 0x0ffff893u -#define CYREG_SFLASH_ALT_PROT_ROW148 0x0ffff894u -#define CYREG_SFLASH_ALT_PROT_ROW149 0x0ffff895u -#define CYREG_SFLASH_ALT_PROT_ROW150 0x0ffff896u -#define CYREG_SFLASH_ALT_PROT_ROW151 0x0ffff897u -#define CYREG_SFLASH_ALT_PROT_ROW152 0x0ffff898u -#define CYREG_SFLASH_ALT_PROT_ROW153 0x0ffff899u -#define CYREG_SFLASH_ALT_PROT_ROW154 0x0ffff89au -#define CYREG_SFLASH_ALT_PROT_ROW155 0x0ffff89bu -#define CYREG_SFLASH_ALT_PROT_ROW156 0x0ffff89cu -#define CYREG_SFLASH_ALT_PROT_ROW157 0x0ffff89du -#define CYREG_SFLASH_ALT_PROT_ROW158 0x0ffff89eu -#define CYREG_SFLASH_ALT_PROT_ROW159 0x0ffff89fu -#define CYREG_SFLASH_ALT_PROT_ROW160 0x0ffff8a0u -#define CYREG_SFLASH_ALT_PROT_ROW161 0x0ffff8a1u -#define CYREG_SFLASH_ALT_PROT_ROW162 0x0ffff8a2u -#define CYREG_SFLASH_ALT_PROT_ROW163 0x0ffff8a3u -#define CYREG_SFLASH_ALT_PROT_ROW164 0x0ffff8a4u -#define CYREG_SFLASH_ALT_PROT_ROW165 0x0ffff8a5u -#define CYREG_SFLASH_ALT_PROT_ROW166 0x0ffff8a6u -#define CYREG_SFLASH_ALT_PROT_ROW167 0x0ffff8a7u -#define CYREG_SFLASH_ALT_PROT_ROW168 0x0ffff8a8u -#define CYREG_SFLASH_ALT_PROT_ROW169 0x0ffff8a9u -#define CYREG_SFLASH_ALT_PROT_ROW170 0x0ffff8aau -#define CYREG_SFLASH_ALT_PROT_ROW171 0x0ffff8abu -#define CYREG_SFLASH_ALT_PROT_ROW172 0x0ffff8acu -#define CYREG_SFLASH_ALT_PROT_ROW173 0x0ffff8adu -#define CYREG_SFLASH_ALT_PROT_ROW174 0x0ffff8aeu -#define CYREG_SFLASH_ALT_PROT_ROW175 0x0ffff8afu -#define CYREG_SFLASH_ALT_PROT_ROW176 0x0ffff8b0u -#define CYREG_SFLASH_ALT_PROT_ROW177 0x0ffff8b1u -#define CYREG_SFLASH_ALT_PROT_ROW178 0x0ffff8b2u -#define CYREG_SFLASH_ALT_PROT_ROW179 0x0ffff8b3u -#define CYREG_SFLASH_ALT_PROT_ROW180 0x0ffff8b4u -#define CYREG_SFLASH_ALT_PROT_ROW181 0x0ffff8b5u -#define CYREG_SFLASH_ALT_PROT_ROW182 0x0ffff8b6u -#define CYREG_SFLASH_ALT_PROT_ROW183 0x0ffff8b7u -#define CYREG_SFLASH_ALT_PROT_ROW184 0x0ffff8b8u -#define CYREG_SFLASH_ALT_PROT_ROW185 0x0ffff8b9u -#define CYREG_SFLASH_ALT_PROT_ROW186 0x0ffff8bau -#define CYREG_SFLASH_ALT_PROT_ROW187 0x0ffff8bbu -#define CYREG_SFLASH_ALT_PROT_ROW188 0x0ffff8bcu -#define CYREG_SFLASH_ALT_PROT_ROW189 0x0ffff8bdu -#define CYREG_SFLASH_ALT_PROT_ROW190 0x0ffff8beu -#define CYREG_SFLASH_ALT_PROT_ROW191 0x0ffff8bfu -#define CYREG_SFLASH_ALT_PROT_ROW192 0x0ffff8c0u -#define CYREG_SFLASH_ALT_PROT_ROW193 0x0ffff8c1u -#define CYREG_SFLASH_ALT_PROT_ROW194 0x0ffff8c2u -#define CYREG_SFLASH_ALT_PROT_ROW195 0x0ffff8c3u -#define CYREG_SFLASH_ALT_PROT_ROW196 0x0ffff8c4u -#define CYREG_SFLASH_ALT_PROT_ROW197 0x0ffff8c5u -#define CYREG_SFLASH_ALT_PROT_ROW198 0x0ffff8c6u -#define CYREG_SFLASH_ALT_PROT_ROW199 0x0ffff8c7u -#define CYREG_SFLASH_ALT_PROT_ROW200 0x0ffff8c8u -#define CYREG_SFLASH_ALT_PROT_ROW201 0x0ffff8c9u -#define CYREG_SFLASH_ALT_PROT_ROW202 0x0ffff8cau -#define CYREG_SFLASH_ALT_PROT_ROW203 0x0ffff8cbu -#define CYREG_SFLASH_ALT_PROT_ROW204 0x0ffff8ccu -#define CYREG_SFLASH_ALT_PROT_ROW205 0x0ffff8cdu -#define CYREG_SFLASH_ALT_PROT_ROW206 0x0ffff8ceu -#define CYREG_SFLASH_ALT_PROT_ROW207 0x0ffff8cfu -#define CYREG_SFLASH_ALT_PROT_ROW208 0x0ffff8d0u -#define CYREG_SFLASH_ALT_PROT_ROW209 0x0ffff8d1u -#define CYREG_SFLASH_ALT_PROT_ROW210 0x0ffff8d2u -#define CYREG_SFLASH_ALT_PROT_ROW211 0x0ffff8d3u -#define CYREG_SFLASH_ALT_PROT_ROW212 0x0ffff8d4u -#define CYREG_SFLASH_ALT_PROT_ROW213 0x0ffff8d5u -#define CYREG_SFLASH_ALT_PROT_ROW214 0x0ffff8d6u -#define CYREG_SFLASH_ALT_PROT_ROW215 0x0ffff8d7u -#define CYREG_SFLASH_ALT_PROT_ROW216 0x0ffff8d8u -#define CYREG_SFLASH_ALT_PROT_ROW217 0x0ffff8d9u -#define CYREG_SFLASH_ALT_PROT_ROW218 0x0ffff8dau -#define CYREG_SFLASH_ALT_PROT_ROW219 0x0ffff8dbu -#define CYREG_SFLASH_ALT_PROT_ROW220 0x0ffff8dcu -#define CYREG_SFLASH_ALT_PROT_ROW221 0x0ffff8ddu -#define CYREG_SFLASH_ALT_PROT_ROW222 0x0ffff8deu -#define CYREG_SFLASH_ALT_PROT_ROW223 0x0ffff8dfu -#define CYREG_SFLASH_ALT_PROT_ROW224 0x0ffff8e0u -#define CYREG_SFLASH_ALT_PROT_ROW225 0x0ffff8e1u -#define CYREG_SFLASH_ALT_PROT_ROW226 0x0ffff8e2u -#define CYREG_SFLASH_ALT_PROT_ROW227 0x0ffff8e3u -#define CYREG_SFLASH_ALT_PROT_ROW228 0x0ffff8e4u -#define CYREG_SFLASH_ALT_PROT_ROW229 0x0ffff8e5u -#define CYREG_SFLASH_ALT_PROT_ROW230 0x0ffff8e6u -#define CYREG_SFLASH_ALT_PROT_ROW231 0x0ffff8e7u -#define CYREG_SFLASH_ALT_PROT_ROW232 0x0ffff8e8u -#define CYREG_SFLASH_ALT_PROT_ROW233 0x0ffff8e9u -#define CYREG_SFLASH_ALT_PROT_ROW234 0x0ffff8eau -#define CYREG_SFLASH_ALT_PROT_ROW235 0x0ffff8ebu -#define CYREG_SFLASH_ALT_PROT_ROW236 0x0ffff8ecu -#define CYREG_SFLASH_ALT_PROT_ROW237 0x0ffff8edu -#define CYREG_SFLASH_ALT_PROT_ROW238 0x0ffff8eeu -#define CYREG_SFLASH_ALT_PROT_ROW239 0x0ffff8efu -#define CYREG_SFLASH_ALT_PROT_ROW240 0x0ffff8f0u -#define CYREG_SFLASH_ALT_PROT_ROW241 0x0ffff8f1u -#define CYREG_SFLASH_ALT_PROT_ROW242 0x0ffff8f2u -#define CYREG_SFLASH_ALT_PROT_ROW243 0x0ffff8f3u -#define CYREG_SFLASH_ALT_PROT_ROW244 0x0ffff8f4u -#define CYREG_SFLASH_ALT_PROT_ROW245 0x0ffff8f5u -#define CYREG_SFLASH_ALT_PROT_ROW246 0x0ffff8f6u -#define CYREG_SFLASH_ALT_PROT_ROW247 0x0ffff8f7u -#define CYREG_SFLASH_ALT_PROT_ROW248 0x0ffff8f8u -#define CYREG_SFLASH_ALT_PROT_ROW249 0x0ffff8f9u -#define CYREG_SFLASH_ALT_PROT_ROW250 0x0ffff8fau -#define CYREG_SFLASH_ALT_PROT_ROW251 0x0ffff8fbu -#define CYREG_SFLASH_ALT_PROT_ROW252 0x0ffff8fcu -#define CYREG_SFLASH_ALT_PROT_ROW253 0x0ffff8fdu -#define CYREG_SFLASH_ALT_PROT_ROW254 0x0ffff8feu -#define CYREG_SFLASH_ALT_PROT_ROW255 0x0ffff8ffu -#define CYREG_SFLASH_ALT_PP 0x0ffffb20u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff201u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff202u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff203u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff204u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff205u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff206u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff207u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff208u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff209u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff20au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff20bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff20cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff20du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff20eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff20fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff210u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff211u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff212u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff213u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff214u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff215u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff216u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff217u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff218u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff219u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff21au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff21bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff21cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff21du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff21eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff21fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff220u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff221u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff222u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff223u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff224u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff225u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff226u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff227u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff228u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff229u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff22au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff22bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff22cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff22du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff22eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff22fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff230u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff231u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff232u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff233u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff234u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff235u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff236u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff237u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff238u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff239u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff23au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff23bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff23cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff23du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff23eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff23fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff240u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff241u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff242u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff243u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff244u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff245u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff246u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff247u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff248u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff249u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff24au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff24bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff24cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff24du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff24eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff24fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff250u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff251u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff252u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff253u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff254u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff255u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff256u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff257u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff258u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff259u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff25au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff25bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff25cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff25du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff25eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff25fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff260u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff261u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff262u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff263u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff264u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff265u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff266u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff267u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff268u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff269u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff26au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff26bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff26cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff26du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff26eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff26fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff270u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff271u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff272u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff273u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff274u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff275u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff276u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff277u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff278u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff279u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff27au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff27bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff27cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff27du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff27eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff27fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff280u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff281u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff282u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff283u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff284u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff285u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff286u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff287u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff288u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff289u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff28au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff28bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff28cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff28du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff28eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff28fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff290u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff291u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff292u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff293u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff294u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff295u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff296u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff297u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff298u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff299u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff29au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff29bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff29cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff29du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff29eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff29fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff2a0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff2a1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff2a2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff2a3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff2a4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff2a5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff2a6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff2a7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff2a8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff2a9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff2aau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff2abu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff2acu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff2adu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff2aeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff2afu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff2b0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff2b1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff2b2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff2b3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff2b4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff2b5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff2b6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff2b7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff2b8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff2b9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff2bau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff2bbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff2bcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff2bdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff2beu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff2bfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff2c0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff2c1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff2c2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff2c3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff2c4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff2c5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff2c6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff2c7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff2c8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff2c9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff2cau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff2cbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff2ccu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff2cdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff2ceu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff2cfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff2d0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff2d1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff2d2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff2d3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff2d4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff2d5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff2d6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff2d7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff2d8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff2d9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff2dau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff2dbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff2dcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff2ddu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff2deu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff2dfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff2e0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff2e1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff2e2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff2e3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff2e4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff2e5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff2e6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff2e7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff2e8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff2e9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff2eau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff2ebu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff2ecu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff2edu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff2eeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff2efu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff2f0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff2f1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff2f2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff2f3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff2f4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff2f5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff2f6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff2f7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff2f8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff2f9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff2fau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff2fbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff2fcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff2fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff2feu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff2ffu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff300u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff301u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff302u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff303u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff304u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff305u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff306u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff307u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff308u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff309u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff30au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff30bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff30cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff30du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff30eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff30fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff310u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff311u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff312u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff313u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff314u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff315u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff316u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff317u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff318u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff319u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff31au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff31bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff31cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff31du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff31eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff31fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff320u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff321u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff322u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff323u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff324u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff325u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff326u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff327u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff328u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff329u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff32au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff32bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff32cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff32du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff32eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff32fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff330u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff331u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff332u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff333u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff334u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff335u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff336u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff337u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff338u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff339u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff33au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff33bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff33cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff33du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff33eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff33fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff340u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff341u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff342u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff343u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff344u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff345u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff346u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff347u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff348u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff349u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff34au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff34bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff34cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff34du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff34eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff34fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff350u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff351u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff352u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff353u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff354u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff355u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff356u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff357u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff358u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff359u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff35au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff35bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff35cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff35du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff35eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff35fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff360u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff361u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff362u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff363u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff364u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff365u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff366u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff367u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff368u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff369u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff36au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff36bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff36cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff36du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff36eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff36fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff370u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff371u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff372u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff373u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff374u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff375u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff376u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff377u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff378u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff379u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff37au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff37bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff37cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff37du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff37eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff37fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff380u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff381u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff382u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff383u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff384u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff385u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff386u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff387u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff388u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff389u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff38au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff38bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff38cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff38du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff38eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff38fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff390u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff391u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff392u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff393u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff394u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff395u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff396u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff397u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff398u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff399u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff39au +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff39bu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff39cu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff39du +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff39eu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff39fu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff3a0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff3a1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff3a2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff3a3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff3a4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff3a5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff3a6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff3a7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff3a8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff3a9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff3aau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff3abu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff3acu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff3adu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff3aeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff3afu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff3b0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff3b1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff3b2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff3b3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff3b4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff3b5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff3b6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff3b7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff3b8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff3b9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff3bau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff3bbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff3bcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff3bdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff3beu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff3bfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff3c0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff3c1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff3c2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff3c3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff3c4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff3c5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff3c6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff3c7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff3c8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff3c9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff3cau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff3cbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff3ccu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff3cdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff3ceu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff3cfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff3d0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff3d1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff3d2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff3d3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff3d4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff3d5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff3d6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff3d7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff3d8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff3d9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff3dau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff3dbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff3dcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff3ddu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff3deu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff3dfu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff3e0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff3e1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff3e2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff3e3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff3e4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff3e5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff3e6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff3e7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff3e8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff3e9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff3eau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff3ebu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff3ecu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff3edu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff3eeu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff3efu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff3f0u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff3f1u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff3f2u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff3f3u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff3f4u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff3f5u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff3f6u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff3f7u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff3f8u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff3f9u +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff3fau +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff3fbu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff3fcu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff3fdu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff3feu +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff3ffu +#define CYREG_SFLASH_ALT_PROT_ROW0 0x0ffff400u +#define CYREG_SFLASH_ALT_PROT_ROW1 0x0ffff401u +#define CYREG_SFLASH_ALT_PROT_ROW2 0x0ffff402u +#define CYREG_SFLASH_ALT_PROT_ROW3 0x0ffff403u +#define CYREG_SFLASH_ALT_PROT_ROW4 0x0ffff404u +#define CYREG_SFLASH_ALT_PROT_ROW5 0x0ffff405u +#define CYREG_SFLASH_ALT_PROT_ROW6 0x0ffff406u +#define CYREG_SFLASH_ALT_PROT_ROW7 0x0ffff407u +#define CYREG_SFLASH_ALT_PROT_ROW8 0x0ffff408u +#define CYREG_SFLASH_ALT_PROT_ROW9 0x0ffff409u +#define CYREG_SFLASH_ALT_PROT_ROW10 0x0ffff40au +#define CYREG_SFLASH_ALT_PROT_ROW11 0x0ffff40bu +#define CYREG_SFLASH_ALT_PROT_ROW12 0x0ffff40cu +#define CYREG_SFLASH_ALT_PROT_ROW13 0x0ffff40du +#define CYREG_SFLASH_ALT_PROT_ROW14 0x0ffff40eu +#define CYREG_SFLASH_ALT_PROT_ROW15 0x0ffff40fu +#define CYREG_SFLASH_ALT_PROT_ROW16 0x0ffff410u +#define CYREG_SFLASH_ALT_PROT_ROW17 0x0ffff411u +#define CYREG_SFLASH_ALT_PROT_ROW18 0x0ffff412u +#define CYREG_SFLASH_ALT_PROT_ROW19 0x0ffff413u +#define CYREG_SFLASH_ALT_PROT_ROW20 0x0ffff414u +#define CYREG_SFLASH_ALT_PROT_ROW21 0x0ffff415u +#define CYREG_SFLASH_ALT_PROT_ROW22 0x0ffff416u +#define CYREG_SFLASH_ALT_PROT_ROW23 0x0ffff417u +#define CYREG_SFLASH_ALT_PROT_ROW24 0x0ffff418u +#define CYREG_SFLASH_ALT_PROT_ROW25 0x0ffff419u +#define CYREG_SFLASH_ALT_PROT_ROW26 0x0ffff41au +#define CYREG_SFLASH_ALT_PROT_ROW27 0x0ffff41bu +#define CYREG_SFLASH_ALT_PROT_ROW28 0x0ffff41cu +#define CYREG_SFLASH_ALT_PROT_ROW29 0x0ffff41du +#define CYREG_SFLASH_ALT_PROT_ROW30 0x0ffff41eu +#define CYREG_SFLASH_ALT_PROT_ROW31 0x0ffff41fu +#define CYREG_SFLASH_ALT_PROT_ROW32 0x0ffff420u +#define CYREG_SFLASH_ALT_PROT_ROW33 0x0ffff421u +#define CYREG_SFLASH_ALT_PROT_ROW34 0x0ffff422u +#define CYREG_SFLASH_ALT_PROT_ROW35 0x0ffff423u +#define CYREG_SFLASH_ALT_PROT_ROW36 0x0ffff424u +#define CYREG_SFLASH_ALT_PROT_ROW37 0x0ffff425u +#define CYREG_SFLASH_ALT_PROT_ROW38 0x0ffff426u +#define CYREG_SFLASH_ALT_PROT_ROW39 0x0ffff427u +#define CYREG_SFLASH_ALT_PROT_ROW40 0x0ffff428u +#define CYREG_SFLASH_ALT_PROT_ROW41 0x0ffff429u +#define CYREG_SFLASH_ALT_PROT_ROW42 0x0ffff42au +#define CYREG_SFLASH_ALT_PROT_ROW43 0x0ffff42bu +#define CYREG_SFLASH_ALT_PROT_ROW44 0x0ffff42cu +#define CYREG_SFLASH_ALT_PROT_ROW45 0x0ffff42du +#define CYREG_SFLASH_ALT_PROT_ROW46 0x0ffff42eu +#define CYREG_SFLASH_ALT_PROT_ROW47 0x0ffff42fu +#define CYREG_SFLASH_ALT_PROT_ROW48 0x0ffff430u +#define CYREG_SFLASH_ALT_PROT_ROW49 0x0ffff431u +#define CYREG_SFLASH_ALT_PROT_ROW50 0x0ffff432u +#define CYREG_SFLASH_ALT_PROT_ROW51 0x0ffff433u +#define CYREG_SFLASH_ALT_PROT_ROW52 0x0ffff434u +#define CYREG_SFLASH_ALT_PROT_ROW53 0x0ffff435u +#define CYREG_SFLASH_ALT_PROT_ROW54 0x0ffff436u +#define CYREG_SFLASH_ALT_PROT_ROW55 0x0ffff437u +#define CYREG_SFLASH_ALT_PROT_ROW56 0x0ffff438u +#define CYREG_SFLASH_ALT_PROT_ROW57 0x0ffff439u +#define CYREG_SFLASH_ALT_PROT_ROW58 0x0ffff43au +#define CYREG_SFLASH_ALT_PROT_ROW59 0x0ffff43bu +#define CYREG_SFLASH_ALT_PROT_ROW60 0x0ffff43cu +#define CYREG_SFLASH_ALT_PROT_ROW61 0x0ffff43du +#define CYREG_SFLASH_ALT_PROT_ROW62 0x0ffff43eu +#define CYREG_SFLASH_ALT_PROT_ROW63 0x0ffff43fu +#define CYREG_SFLASH_ALT_PROT_ROW64 0x0ffff440u +#define CYREG_SFLASH_ALT_PROT_ROW65 0x0ffff441u +#define CYREG_SFLASH_ALT_PROT_ROW66 0x0ffff442u +#define CYREG_SFLASH_ALT_PROT_ROW67 0x0ffff443u +#define CYREG_SFLASH_ALT_PROT_ROW68 0x0ffff444u +#define CYREG_SFLASH_ALT_PROT_ROW69 0x0ffff445u +#define CYREG_SFLASH_ALT_PROT_ROW70 0x0ffff446u +#define CYREG_SFLASH_ALT_PROT_ROW71 0x0ffff447u +#define CYREG_SFLASH_ALT_PROT_ROW72 0x0ffff448u +#define CYREG_SFLASH_ALT_PROT_ROW73 0x0ffff449u +#define CYREG_SFLASH_ALT_PROT_ROW74 0x0ffff44au +#define CYREG_SFLASH_ALT_PROT_ROW75 0x0ffff44bu +#define CYREG_SFLASH_ALT_PROT_ROW76 0x0ffff44cu +#define CYREG_SFLASH_ALT_PROT_ROW77 0x0ffff44du +#define CYREG_SFLASH_ALT_PROT_ROW78 0x0ffff44eu +#define CYREG_SFLASH_ALT_PROT_ROW79 0x0ffff44fu +#define CYREG_SFLASH_ALT_PROT_ROW80 0x0ffff450u +#define CYREG_SFLASH_ALT_PROT_ROW81 0x0ffff451u +#define CYREG_SFLASH_ALT_PROT_ROW82 0x0ffff452u +#define CYREG_SFLASH_ALT_PROT_ROW83 0x0ffff453u +#define CYREG_SFLASH_ALT_PROT_ROW84 0x0ffff454u +#define CYREG_SFLASH_ALT_PROT_ROW85 0x0ffff455u +#define CYREG_SFLASH_ALT_PROT_ROW86 0x0ffff456u +#define CYREG_SFLASH_ALT_PROT_ROW87 0x0ffff457u +#define CYREG_SFLASH_ALT_PROT_ROW88 0x0ffff458u +#define CYREG_SFLASH_ALT_PROT_ROW89 0x0ffff459u +#define CYREG_SFLASH_ALT_PROT_ROW90 0x0ffff45au +#define CYREG_SFLASH_ALT_PROT_ROW91 0x0ffff45bu +#define CYREG_SFLASH_ALT_PROT_ROW92 0x0ffff45cu +#define CYREG_SFLASH_ALT_PROT_ROW93 0x0ffff45du +#define CYREG_SFLASH_ALT_PROT_ROW94 0x0ffff45eu +#define CYREG_SFLASH_ALT_PROT_ROW95 0x0ffff45fu +#define CYREG_SFLASH_ALT_PROT_ROW96 0x0ffff460u +#define CYREG_SFLASH_ALT_PROT_ROW97 0x0ffff461u +#define CYREG_SFLASH_ALT_PROT_ROW98 0x0ffff462u +#define CYREG_SFLASH_ALT_PROT_ROW99 0x0ffff463u +#define CYREG_SFLASH_ALT_PROT_ROW100 0x0ffff464u +#define CYREG_SFLASH_ALT_PROT_ROW101 0x0ffff465u +#define CYREG_SFLASH_ALT_PROT_ROW102 0x0ffff466u +#define CYREG_SFLASH_ALT_PROT_ROW103 0x0ffff467u +#define CYREG_SFLASH_ALT_PROT_ROW104 0x0ffff468u +#define CYREG_SFLASH_ALT_PROT_ROW105 0x0ffff469u +#define CYREG_SFLASH_ALT_PROT_ROW106 0x0ffff46au +#define CYREG_SFLASH_ALT_PROT_ROW107 0x0ffff46bu +#define CYREG_SFLASH_ALT_PROT_ROW108 0x0ffff46cu +#define CYREG_SFLASH_ALT_PROT_ROW109 0x0ffff46du +#define CYREG_SFLASH_ALT_PROT_ROW110 0x0ffff46eu +#define CYREG_SFLASH_ALT_PROT_ROW111 0x0ffff46fu +#define CYREG_SFLASH_ALT_PROT_ROW112 0x0ffff470u +#define CYREG_SFLASH_ALT_PROT_ROW113 0x0ffff471u +#define CYREG_SFLASH_ALT_PROT_ROW114 0x0ffff472u +#define CYREG_SFLASH_ALT_PROT_ROW115 0x0ffff473u +#define CYREG_SFLASH_ALT_PROT_ROW116 0x0ffff474u +#define CYREG_SFLASH_ALT_PROT_ROW117 0x0ffff475u +#define CYREG_SFLASH_ALT_PROT_ROW118 0x0ffff476u +#define CYREG_SFLASH_ALT_PROT_ROW119 0x0ffff477u +#define CYREG_SFLASH_ALT_PROT_ROW120 0x0ffff478u +#define CYREG_SFLASH_ALT_PROT_ROW121 0x0ffff479u +#define CYREG_SFLASH_ALT_PROT_ROW122 0x0ffff47au +#define CYREG_SFLASH_ALT_PROT_ROW123 0x0ffff47bu +#define CYREG_SFLASH_ALT_PROT_ROW124 0x0ffff47cu +#define CYREG_SFLASH_ALT_PROT_ROW125 0x0ffff47du +#define CYREG_SFLASH_ALT_PROT_ROW126 0x0ffff47eu +#define CYREG_SFLASH_ALT_PROT_ROW127 0x0ffff47fu +#define CYREG_SFLASH_ALT_PROT_ROW128 0x0ffff480u +#define CYREG_SFLASH_ALT_PROT_ROW129 0x0ffff481u +#define CYREG_SFLASH_ALT_PROT_ROW130 0x0ffff482u +#define CYREG_SFLASH_ALT_PROT_ROW131 0x0ffff483u +#define CYREG_SFLASH_ALT_PROT_ROW132 0x0ffff484u +#define CYREG_SFLASH_ALT_PROT_ROW133 0x0ffff485u +#define CYREG_SFLASH_ALT_PROT_ROW134 0x0ffff486u +#define CYREG_SFLASH_ALT_PROT_ROW135 0x0ffff487u +#define CYREG_SFLASH_ALT_PROT_ROW136 0x0ffff488u +#define CYREG_SFLASH_ALT_PROT_ROW137 0x0ffff489u +#define CYREG_SFLASH_ALT_PROT_ROW138 0x0ffff48au +#define CYREG_SFLASH_ALT_PROT_ROW139 0x0ffff48bu +#define CYREG_SFLASH_ALT_PROT_ROW140 0x0ffff48cu +#define CYREG_SFLASH_ALT_PROT_ROW141 0x0ffff48du +#define CYREG_SFLASH_ALT_PROT_ROW142 0x0ffff48eu +#define CYREG_SFLASH_ALT_PROT_ROW143 0x0ffff48fu +#define CYREG_SFLASH_ALT_PROT_ROW144 0x0ffff490u +#define CYREG_SFLASH_ALT_PROT_ROW145 0x0ffff491u +#define CYREG_SFLASH_ALT_PROT_ROW146 0x0ffff492u +#define CYREG_SFLASH_ALT_PROT_ROW147 0x0ffff493u +#define CYREG_SFLASH_ALT_PROT_ROW148 0x0ffff494u +#define CYREG_SFLASH_ALT_PROT_ROW149 0x0ffff495u +#define CYREG_SFLASH_ALT_PROT_ROW150 0x0ffff496u +#define CYREG_SFLASH_ALT_PROT_ROW151 0x0ffff497u +#define CYREG_SFLASH_ALT_PROT_ROW152 0x0ffff498u +#define CYREG_SFLASH_ALT_PROT_ROW153 0x0ffff499u +#define CYREG_SFLASH_ALT_PROT_ROW154 0x0ffff49au +#define CYREG_SFLASH_ALT_PROT_ROW155 0x0ffff49bu +#define CYREG_SFLASH_ALT_PROT_ROW156 0x0ffff49cu +#define CYREG_SFLASH_ALT_PROT_ROW157 0x0ffff49du +#define CYREG_SFLASH_ALT_PROT_ROW158 0x0ffff49eu +#define CYREG_SFLASH_ALT_PROT_ROW159 0x0ffff49fu +#define CYREG_SFLASH_ALT_PROT_ROW160 0x0ffff4a0u +#define CYREG_SFLASH_ALT_PROT_ROW161 0x0ffff4a1u +#define CYREG_SFLASH_ALT_PROT_ROW162 0x0ffff4a2u +#define CYREG_SFLASH_ALT_PROT_ROW163 0x0ffff4a3u +#define CYREG_SFLASH_ALT_PROT_ROW164 0x0ffff4a4u +#define CYREG_SFLASH_ALT_PROT_ROW165 0x0ffff4a5u +#define CYREG_SFLASH_ALT_PROT_ROW166 0x0ffff4a6u +#define CYREG_SFLASH_ALT_PROT_ROW167 0x0ffff4a7u +#define CYREG_SFLASH_ALT_PROT_ROW168 0x0ffff4a8u +#define CYREG_SFLASH_ALT_PROT_ROW169 0x0ffff4a9u +#define CYREG_SFLASH_ALT_PROT_ROW170 0x0ffff4aau +#define CYREG_SFLASH_ALT_PROT_ROW171 0x0ffff4abu +#define CYREG_SFLASH_ALT_PROT_ROW172 0x0ffff4acu +#define CYREG_SFLASH_ALT_PROT_ROW173 0x0ffff4adu +#define CYREG_SFLASH_ALT_PROT_ROW174 0x0ffff4aeu +#define CYREG_SFLASH_ALT_PROT_ROW175 0x0ffff4afu +#define CYREG_SFLASH_ALT_PROT_ROW176 0x0ffff4b0u +#define CYREG_SFLASH_ALT_PROT_ROW177 0x0ffff4b1u +#define CYREG_SFLASH_ALT_PROT_ROW178 0x0ffff4b2u +#define CYREG_SFLASH_ALT_PROT_ROW179 0x0ffff4b3u +#define CYREG_SFLASH_ALT_PROT_ROW180 0x0ffff4b4u +#define CYREG_SFLASH_ALT_PROT_ROW181 0x0ffff4b5u +#define CYREG_SFLASH_ALT_PROT_ROW182 0x0ffff4b6u +#define CYREG_SFLASH_ALT_PROT_ROW183 0x0ffff4b7u +#define CYREG_SFLASH_ALT_PROT_ROW184 0x0ffff4b8u +#define CYREG_SFLASH_ALT_PROT_ROW185 0x0ffff4b9u +#define CYREG_SFLASH_ALT_PROT_ROW186 0x0ffff4bau +#define CYREG_SFLASH_ALT_PROT_ROW187 0x0ffff4bbu +#define CYREG_SFLASH_ALT_PROT_ROW188 0x0ffff4bcu +#define CYREG_SFLASH_ALT_PROT_ROW189 0x0ffff4bdu +#define CYREG_SFLASH_ALT_PROT_ROW190 0x0ffff4beu +#define CYREG_SFLASH_ALT_PROT_ROW191 0x0ffff4bfu +#define CYREG_SFLASH_ALT_PROT_ROW192 0x0ffff4c0u +#define CYREG_SFLASH_ALT_PROT_ROW193 0x0ffff4c1u +#define CYREG_SFLASH_ALT_PROT_ROW194 0x0ffff4c2u +#define CYREG_SFLASH_ALT_PROT_ROW195 0x0ffff4c3u +#define CYREG_SFLASH_ALT_PROT_ROW196 0x0ffff4c4u +#define CYREG_SFLASH_ALT_PROT_ROW197 0x0ffff4c5u +#define CYREG_SFLASH_ALT_PROT_ROW198 0x0ffff4c6u +#define CYREG_SFLASH_ALT_PROT_ROW199 0x0ffff4c7u +#define CYREG_SFLASH_ALT_PROT_ROW200 0x0ffff4c8u +#define CYREG_SFLASH_ALT_PROT_ROW201 0x0ffff4c9u +#define CYREG_SFLASH_ALT_PROT_ROW202 0x0ffff4cau +#define CYREG_SFLASH_ALT_PROT_ROW203 0x0ffff4cbu +#define CYREG_SFLASH_ALT_PROT_ROW204 0x0ffff4ccu +#define CYREG_SFLASH_ALT_PROT_ROW205 0x0ffff4cdu +#define CYREG_SFLASH_ALT_PROT_ROW206 0x0ffff4ceu +#define CYREG_SFLASH_ALT_PROT_ROW207 0x0ffff4cfu +#define CYREG_SFLASH_ALT_PROT_ROW208 0x0ffff4d0u +#define CYREG_SFLASH_ALT_PROT_ROW209 0x0ffff4d1u +#define CYREG_SFLASH_ALT_PROT_ROW210 0x0ffff4d2u +#define CYREG_SFLASH_ALT_PROT_ROW211 0x0ffff4d3u +#define CYREG_SFLASH_ALT_PROT_ROW212 0x0ffff4d4u +#define CYREG_SFLASH_ALT_PROT_ROW213 0x0ffff4d5u +#define CYREG_SFLASH_ALT_PROT_ROW214 0x0ffff4d6u +#define CYREG_SFLASH_ALT_PROT_ROW215 0x0ffff4d7u +#define CYREG_SFLASH_ALT_PROT_ROW216 0x0ffff4d8u +#define CYREG_SFLASH_ALT_PROT_ROW217 0x0ffff4d9u +#define CYREG_SFLASH_ALT_PROT_ROW218 0x0ffff4dau +#define CYREG_SFLASH_ALT_PROT_ROW219 0x0ffff4dbu +#define CYREG_SFLASH_ALT_PROT_ROW220 0x0ffff4dcu +#define CYREG_SFLASH_ALT_PROT_ROW221 0x0ffff4ddu +#define CYREG_SFLASH_ALT_PROT_ROW222 0x0ffff4deu +#define CYREG_SFLASH_ALT_PROT_ROW223 0x0ffff4dfu +#define CYREG_SFLASH_ALT_PROT_ROW224 0x0ffff4e0u +#define CYREG_SFLASH_ALT_PROT_ROW225 0x0ffff4e1u +#define CYREG_SFLASH_ALT_PROT_ROW226 0x0ffff4e2u +#define CYREG_SFLASH_ALT_PROT_ROW227 0x0ffff4e3u +#define CYREG_SFLASH_ALT_PROT_ROW228 0x0ffff4e4u +#define CYREG_SFLASH_ALT_PROT_ROW229 0x0ffff4e5u +#define CYREG_SFLASH_ALT_PROT_ROW230 0x0ffff4e6u +#define CYREG_SFLASH_ALT_PROT_ROW231 0x0ffff4e7u +#define CYREG_SFLASH_ALT_PROT_ROW232 0x0ffff4e8u +#define CYREG_SFLASH_ALT_PROT_ROW233 0x0ffff4e9u +#define CYREG_SFLASH_ALT_PROT_ROW234 0x0ffff4eau +#define CYREG_SFLASH_ALT_PROT_ROW235 0x0ffff4ebu +#define CYREG_SFLASH_ALT_PROT_ROW236 0x0ffff4ecu +#define CYREG_SFLASH_ALT_PROT_ROW237 0x0ffff4edu +#define CYREG_SFLASH_ALT_PROT_ROW238 0x0ffff4eeu +#define CYREG_SFLASH_ALT_PROT_ROW239 0x0ffff4efu +#define CYREG_SFLASH_ALT_PROT_ROW240 0x0ffff4f0u +#define CYREG_SFLASH_ALT_PROT_ROW241 0x0ffff4f1u +#define CYREG_SFLASH_ALT_PROT_ROW242 0x0ffff4f2u +#define CYREG_SFLASH_ALT_PROT_ROW243 0x0ffff4f3u +#define CYREG_SFLASH_ALT_PROT_ROW244 0x0ffff4f4u +#define CYREG_SFLASH_ALT_PROT_ROW245 0x0ffff4f5u +#define CYREG_SFLASH_ALT_PROT_ROW246 0x0ffff4f6u +#define CYREG_SFLASH_ALT_PROT_ROW247 0x0ffff4f7u +#define CYREG_SFLASH_ALT_PROT_ROW248 0x0ffff4f8u +#define CYREG_SFLASH_ALT_PROT_ROW249 0x0ffff4f9u +#define CYREG_SFLASH_ALT_PROT_ROW250 0x0ffff4fau +#define CYREG_SFLASH_ALT_PROT_ROW251 0x0ffff4fbu +#define CYREG_SFLASH_ALT_PROT_ROW252 0x0ffff4fcu +#define CYREG_SFLASH_ALT_PROT_ROW253 0x0ffff4fdu +#define CYREG_SFLASH_ALT_PROT_ROW254 0x0ffff4feu +#define CYREG_SFLASH_ALT_PROT_ROW255 0x0ffff4ffu +#define CYREG_SFLASH_ALT_PP 0x0ffff5a0u #define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000u #define CYFLD_SFLASH_PERIOD__SIZE 0x00000018u #define CYFLD_SFLASH_PDAC__OFFSET 0x00000018u #define CYFLD_SFLASH_PDAC__SIZE 0x00000004u #define CYFLD_SFLASH_NDAC__OFFSET 0x0000001cu #define CYFLD_SFLASH_NDAC__SIZE 0x00000004u -#define CYREG_SFLASH_ALT_E 0x0ffffb24u -#define CYREG_SFLASH_ALT_P 0x0ffffb28u -#define CYREG_SFLASH_ALT_EA_E 0x0ffffb2cu -#define CYREG_SFLASH_ALT_EA_P 0x0ffffb30u -#define CYREG_SFLASH_ALT_ES_E 0x0ffffb34u -#define CYREG_SFLASH_ALT_ES_P_EO 0x0ffffb38u -#define CYREG_SFLASH_ALT_E_VCTAT 0x0ffffb3cu +#define CYREG_SFLASH_ALT_E 0x0ffff5a4u +#define CYREG_SFLASH_ALT_P 0x0ffff5a8u +#define CYREG_SFLASH_ALT_EA_E 0x0ffff5acu +#define CYREG_SFLASH_ALT_EA_P 0x0ffff5b0u +#define CYREG_SFLASH_ALT_ES_E 0x0ffff5b4u +#define CYREG_SFLASH_ALT_ES_P_EO 0x0ffff5b8u +#define CYREG_SFLASH_ALT_E_VCTAT 0x0ffff5bcu #define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000u #define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004u #define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004u #define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002u #define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006u #define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001u -#define CYREG_SFLASH_ALT_P_VCTAT 0x0ffffb3du +#define CYREG_SFLASH_ALT_P_VCTAT 0x0ffff5bdu #define CYDEV_ROM_BASE 0x10000000u #define CYDEV_ROM_SIZE 0x00002000u #define CYREG_ROM_DATA_MBASE 0x10000000u #define CYREG_ROM_DATA_MSIZE 0x00002000u #define CYDEV_SRAM_BASE 0x20000000u -#define CYDEV_SRAM_SIZE 0x00008000u +#define CYDEV_SRAM_SIZE 0x00004000u #define CYREG_SRAM_DATA_MBASE 0x20000000u -#define CYREG_SRAM_DATA_MSIZE 0x00008000u +#define CYREG_SRAM_DATA_MSIZE 0x00004000u #define CYDEV_PERI_BASE 0x40010000u #define CYDEV_PERI_SIZE 0x00010000u #define CYREG_PERI_DIV_CMD 0x40010000u @@ -1849,29 +1291,6 @@ #define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003u #define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005u #define CYREG_PERI_DIV_16_5_CTL1 0x40010404u -#define CYREG_PERI_TR_CTL 0x40010600u -#define CYFLD_PERI_TR_SEL__OFFSET 0x00000000u -#define CYFLD_PERI_TR_SEL__SIZE 0x00000007u -#define CYFLD_PERI_TR_GROUP__OFFSET 0x00000008u -#define CYFLD_PERI_TR_GROUP__SIZE 0x00000004u -#define CYFLD_PERI_TR_COUNT__OFFSET 0x00000010u -#define CYFLD_PERI_TR_COUNT__SIZE 0x00000008u -#define CYFLD_PERI_TR_OUT__OFFSET 0x0000001eu -#define CYFLD_PERI_TR_OUT__SIZE 0x00000001u -#define CYFLD_PERI_TR_ACT__OFFSET 0x0000001fu -#define CYFLD_PERI_TR_ACT__SIZE 0x00000001u -#define CYDEV_PERI_TR_GROUP_BASE 0x40012000u -#define CYDEV_PERI_TR_GROUP_SIZE 0x00000200u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL0 0x40012000u -#define CYFLD_PERI_TR_GROUP_SEL__OFFSET 0x00000000u -#define CYFLD_PERI_TR_GROUP_SEL__SIZE 0x00000005u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL1 0x40012004u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL2 0x40012008u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL3 0x4001200cu -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL4 0x40012010u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL5 0x40012014u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL6 0x40012018u -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL7 0x4001201cu #define CYDEV_HSIOM_BASE 0x40020000u #define CYDEV_HSIOM_SIZE 0x00004000u #define CYREG_HSIOM_PORT_SEL0 0x40020000u @@ -6254,165 +5673,9 @@ #define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001u #define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008u #define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001u -#define CYFLD_CPUSS_ARB__OFFSET 0x00000010u -#define CYFLD_CPUSS_ARB__SIZE 0x00000002u #define CYREG_CPUSS_ROM_CTL 0x40100034u #define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000u #define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001u -#define CYREG_CPUSS_RAM_CTL 0x40100038u -#define CYREG_CPUSS_DMAC_CTL 0x4010003cu -#define CYREG_CPUSS_SL_CTL0 0x40100100u -#define CYREG_CPUSS_SL_CTL1 0x40100104u -#define CYREG_CPUSS_SL_CTL2 0x40100108u -#define CYDEV_DMAC_BASE 0x40101000u -#define CYDEV_DMAC_SIZE 0x00001000u -#define CYREG_DMAC_CTL 0x40101000u -#define CYFLD_DMAC_ENABLED__OFFSET 0x0000001fu -#define CYFLD_DMAC_ENABLED__SIZE 0x00000001u -#define CYREG_DMAC_STATUS 0x40101010u -#define CYFLD_DMAC_DATA_NR__OFFSET 0x00000000u -#define CYFLD_DMAC_DATA_NR__SIZE 0x00000010u -#define CYFLD_DMAC_CH_ADDR__OFFSET 0x00000010u -#define CYFLD_DMAC_CH_ADDR__SIZE 0x00000003u -#define CYFLD_DMAC_STATE__OFFSET 0x00000018u -#define CYFLD_DMAC_STATE__SIZE 0x00000003u -#define CYFLD_DMAC_PRIO__OFFSET 0x0000001cu -#define CYFLD_DMAC_PRIO__SIZE 0x00000002u -#define CYFLD_DMAC_PING_PONG__OFFSET 0x0000001eu -#define CYFLD_DMAC_PING_PONG__SIZE 0x00000001u -#define CYFLD_DMAC_ACTIVE__OFFSET 0x0000001fu -#define CYFLD_DMAC_ACTIVE__SIZE 0x00000001u -#define CYREG_DMAC_STATUS_SRC_ADDR 0x40101014u -#define CYFLD_DMAC_ADDR__OFFSET 0x00000000u -#define CYFLD_DMAC_ADDR__SIZE 0x00000020u -#define CYREG_DMAC_STATUS_DST_ADDR 0x40101018u -#define CYREG_DMAC_STATUS_CH_ACT 0x4010101cu -#define CYFLD_DMAC_CH__OFFSET 0x00000000u -#define CYFLD_DMAC_CH__SIZE 0x00000008u -#define CYREG_DMAC_CH_CTL0 0x40101080u -#define CYREG_DMAC_CH_CTL1 0x40101084u -#define CYREG_DMAC_CH_CTL2 0x40101088u -#define CYREG_DMAC_CH_CTL3 0x4010108cu -#define CYREG_DMAC_CH_CTL4 0x40101090u -#define CYREG_DMAC_CH_CTL5 0x40101094u -#define CYREG_DMAC_CH_CTL6 0x40101098u -#define CYREG_DMAC_CH_CTL7 0x4010109cu -#define CYREG_DMAC_INTR 0x401017f0u -#define CYREG_DMAC_INTR_SET 0x401017f4u -#define CYREG_DMAC_INTR_MASK 0x401017f8u -#define CYREG_DMAC_INTR_MASKED 0x401017fcu -#define CYDEV_DMAC_DESCR0_BASE 0x40101800u -#define CYDEV_DMAC_DESCR0_SIZE 0x00000020u -#define CYREG_DMAC_DESCR0_PING_SRC 0x40101800u -#define CYFLD_DMAC_DESCR_ADDR__OFFSET 0x00000000u -#define CYFLD_DMAC_DESCR_ADDR__SIZE 0x00000020u -#define CYREG_DMAC_DESCR0_PING_DST 0x40101804u -#define CYREG_DMAC_DESCR0_PING_CTL 0x40101808u -#define CYFLD_DMAC_DESCR_DATA_NR__OFFSET 0x00000000u -#define CYFLD_DMAC_DESCR_DATA_NR__SIZE 0x00000010u -#define CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET 0x00000010u -#define CYFLD_DMAC_DESCR_DATA_SIZE__SIZE 0x00000002u -#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET 0x00000014u -#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET 0x00000015u -#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET 0x00000016u -#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET 0x00000017u -#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET 0x00000018u -#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE 0x00000002u -#define CYFLD_DMAC_DESCR_INV_DESCR__OFFSET 0x0000001au -#define CYFLD_DMAC_DESCR_INV_DESCR__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET 0x0000001bu -#define CYFLD_DMAC_DESCR_SET_CAUSE__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET 0x0000001cu -#define CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_FLIPPING__OFFSET 0x0000001du -#define CYFLD_DMAC_DESCR_FLIPPING__SIZE 0x00000001u -#define CYFLD_DMAC_DESCR_OPCODE__OFFSET 0x0000001eu -#define CYFLD_DMAC_DESCR_OPCODE__SIZE 0x00000002u -#define CYREG_DMAC_DESCR0_PING_STATUS 0x4010180cu -#define CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET 0x00000000u -#define CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE 0x00000010u -#define CYFLD_DMAC_DESCR_RESPONSE__OFFSET 0x00000010u -#define CYFLD_DMAC_DESCR_RESPONSE__SIZE 0x00000003u -#define CYFLD_DMAC_DESCR_VALID__OFFSET 0x0000001fu -#define CYFLD_DMAC_DESCR_VALID__SIZE 0x00000001u -#define CYREG_DMAC_DESCR0_PONG_SRC 0x40101810u -#define CYREG_DMAC_DESCR0_PONG_DST 0x40101814u -#define CYREG_DMAC_DESCR0_PONG_CTL 0x40101818u -#define CYREG_DMAC_DESCR0_PONG_STATUS 0x4010181cu -#define CYDEV_DMAC_DESCR1_BASE 0x40101820u -#define CYDEV_DMAC_DESCR1_SIZE 0x00000020u -#define CYREG_DMAC_DESCR1_PING_SRC 0x40101820u -#define CYREG_DMAC_DESCR1_PING_DST 0x40101824u -#define CYREG_DMAC_DESCR1_PING_CTL 0x40101828u -#define CYREG_DMAC_DESCR1_PING_STATUS 0x4010182cu -#define CYREG_DMAC_DESCR1_PONG_SRC 0x40101830u -#define CYREG_DMAC_DESCR1_PONG_DST 0x40101834u -#define CYREG_DMAC_DESCR1_PONG_CTL 0x40101838u -#define CYREG_DMAC_DESCR1_PONG_STATUS 0x4010183cu -#define CYDEV_DMAC_DESCR2_BASE 0x40101840u -#define CYDEV_DMAC_DESCR2_SIZE 0x00000020u -#define CYREG_DMAC_DESCR2_PING_SRC 0x40101840u -#define CYREG_DMAC_DESCR2_PING_DST 0x40101844u -#define CYREG_DMAC_DESCR2_PING_CTL 0x40101848u -#define CYREG_DMAC_DESCR2_PING_STATUS 0x4010184cu -#define CYREG_DMAC_DESCR2_PONG_SRC 0x40101850u -#define CYREG_DMAC_DESCR2_PONG_DST 0x40101854u -#define CYREG_DMAC_DESCR2_PONG_CTL 0x40101858u -#define CYREG_DMAC_DESCR2_PONG_STATUS 0x4010185cu -#define CYDEV_DMAC_DESCR3_BASE 0x40101860u -#define CYDEV_DMAC_DESCR3_SIZE 0x00000020u -#define CYREG_DMAC_DESCR3_PING_SRC 0x40101860u -#define CYREG_DMAC_DESCR3_PING_DST 0x40101864u -#define CYREG_DMAC_DESCR3_PING_CTL 0x40101868u -#define CYREG_DMAC_DESCR3_PING_STATUS 0x4010186cu -#define CYREG_DMAC_DESCR3_PONG_SRC 0x40101870u -#define CYREG_DMAC_DESCR3_PONG_DST 0x40101874u -#define CYREG_DMAC_DESCR3_PONG_CTL 0x40101878u -#define CYREG_DMAC_DESCR3_PONG_STATUS 0x4010187cu -#define CYDEV_DMAC_DESCR4_BASE 0x40101880u -#define CYDEV_DMAC_DESCR4_SIZE 0x00000020u -#define CYREG_DMAC_DESCR4_PING_SRC 0x40101880u -#define CYREG_DMAC_DESCR4_PING_DST 0x40101884u -#define CYREG_DMAC_DESCR4_PING_CTL 0x40101888u -#define CYREG_DMAC_DESCR4_PING_STATUS 0x4010188cu -#define CYREG_DMAC_DESCR4_PONG_SRC 0x40101890u -#define CYREG_DMAC_DESCR4_PONG_DST 0x40101894u -#define CYREG_DMAC_DESCR4_PONG_CTL 0x40101898u -#define CYREG_DMAC_DESCR4_PONG_STATUS 0x4010189cu -#define CYDEV_DMAC_DESCR5_BASE 0x401018a0u -#define CYDEV_DMAC_DESCR5_SIZE 0x00000020u -#define CYREG_DMAC_DESCR5_PING_SRC 0x401018a0u -#define CYREG_DMAC_DESCR5_PING_DST 0x401018a4u -#define CYREG_DMAC_DESCR5_PING_CTL 0x401018a8u -#define CYREG_DMAC_DESCR5_PING_STATUS 0x401018acu -#define CYREG_DMAC_DESCR5_PONG_SRC 0x401018b0u -#define CYREG_DMAC_DESCR5_PONG_DST 0x401018b4u -#define CYREG_DMAC_DESCR5_PONG_CTL 0x401018b8u -#define CYREG_DMAC_DESCR5_PONG_STATUS 0x401018bcu -#define CYDEV_DMAC_DESCR6_BASE 0x401018c0u -#define CYDEV_DMAC_DESCR6_SIZE 0x00000020u -#define CYREG_DMAC_DESCR6_PING_SRC 0x401018c0u -#define CYREG_DMAC_DESCR6_PING_DST 0x401018c4u -#define CYREG_DMAC_DESCR6_PING_CTL 0x401018c8u -#define CYREG_DMAC_DESCR6_PING_STATUS 0x401018ccu -#define CYREG_DMAC_DESCR6_PONG_SRC 0x401018d0u -#define CYREG_DMAC_DESCR6_PONG_DST 0x401018d4u -#define CYREG_DMAC_DESCR6_PONG_CTL 0x401018d8u -#define CYREG_DMAC_DESCR6_PONG_STATUS 0x401018dcu -#define CYDEV_DMAC_DESCR7_BASE 0x401018e0u -#define CYDEV_DMAC_DESCR7_SIZE 0x00000020u -#define CYREG_DMAC_DESCR7_PING_SRC 0x401018e0u -#define CYREG_DMAC_DESCR7_PING_DST 0x401018e4u -#define CYREG_DMAC_DESCR7_PING_CTL 0x401018e8u -#define CYREG_DMAC_DESCR7_PING_STATUS 0x401018ecu -#define CYREG_DMAC_DESCR7_PONG_SRC 0x401018f0u -#define CYREG_DMAC_DESCR7_PONG_DST 0x401018f4u -#define CYREG_DMAC_DESCR7_PONG_CTL 0x401018f8u -#define CYREG_DMAC_DESCR7_PONG_STATUS 0x401018fcu #define CYDEV_SPCIF_BASE 0x40110000u #define CYDEV_SPCIF_SIZE 0x00010000u #define CYREG_SPCIF_GEOMETRY 0x40110000u @@ -8081,33 +7344,8 @@ #define CYREG_BLE_BLERD_READ_IQ_4 0x402e010cu #define CYFLD_BLE_BLERD_ADC_4__OFFSET 0x00000000u #define CYFLD_BLE_BLERD_ADC_4__SIZE 0x00000020u -#define CYREG_BLE_BLERD_AGC_GAIN_COMP_1 0x402e0180u -#define CYFLD_BLE_BLERD_GAIN_5__OFFSET 0x00000000u -#define CYFLD_BLE_BLERD_GAIN_5__SIZE 0x00000005u -#define CYFLD_BLE_BLERD_GAIN_4__OFFSET 0x00000005u -#define CYFLD_BLE_BLERD_GAIN_4__SIZE 0x00000005u -#define CYFLD_BLE_BLERD_GAIN_3__OFFSET 0x0000000au -#define CYFLD_BLE_BLERD_GAIN_3__SIZE 0x00000005u -#define CYREG_BLE_BLERD_AGC_GAIN_COMP_2 0x402e0184u -#define CYFLD_BLE_BLERD_GAIN_2__OFFSET 0x00000000u -#define CYFLD_BLE_BLERD_GAIN_2__SIZE 0x00000005u -#define CYFLD_BLE_BLERD_GAIN_1__OFFSET 0x00000005u -#define CYFLD_BLE_BLERD_GAIN_1__SIZE 0x00000005u -#define CYFLD_BLE_BLERD_GAIN_0__OFFSET 0x0000000au -#define CYFLD_BLE_BLERD_GAIN_0__SIZE 0x00000005u -#define CYREG_BLE_BLERD_PA_RSSI_NEW 0x402e0188u -#define CYFLD_BLE_BLERD_PA_RAMP_STEP__OFFSET 0x00000000u -#define CYFLD_BLE_BLERD_PA_RAMP_STEP__SIZE 0x00000002u -#define CYFLD_BLE_BLERD_PA_RAMP_NEW__OFFSET 0x00000003u -#define CYFLD_BLE_BLERD_PA_RAMP_NEW__SIZE 0x00000001u -#define CYFLD_BLE_BLERD_MIN_RSSI_NEW__OFFSET 0x00000004u -#define CYFLD_BLE_BLERD_MIN_RSSI_NEW__SIZE 0x00000001u -#define CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__OFFSET 0x00000005u -#define CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__OFFSET 0x00000006u -#define CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__SIZE 0x00000001u #define CYDEV_BLE_BLELL_BASE 0x402e1000u -#define CYDEV_BLE_BLELL_SIZE 0x00003000u +#define CYDEV_BLE_BLELL_SIZE 0x00001000u #define CYREG_BLE_BLELL_COMMAND_REGISTER 0x402e1000u #define CYFLD_BLE_BLELL_COMMAND__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_COMMAND__SIZE 0x00000008u @@ -8154,14 +7392,6 @@ #define CYFLD_BLE_BLELL_RX_ADDR__SIZE 0x00000001u #define CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__OFFSET 0x0000000au #define CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INITA_RPA_CHECK__OFFSET 0x0000000bu -#define CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET 0x0000000cu -#define CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__OFFSET 0x0000000du -#define CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET 0x0000000eu -#define CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE 0x00000001u #define CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET 0x0000000fu #define CYFLD_BLE_BLELL_RCV_TX_ADDR__SIZE 0x00000001u #define CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT 0x402e101cu @@ -8186,14 +7416,6 @@ #define CYFLD_BLE_BLELL_ADV_TIMEOUT__SIZE 0x00000001u #define CYFLD_BLE_BLELL_ADV_ON__OFFSET 0x00000008u #define CYFLD_BLE_BLELL_ADV_ON__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET 0x0000000au -#define CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x0000000bu -#define CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x0000000cu -#define CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001u #define CYREG_BLE_BLELL_ADV_NEXT_INSTANT 0x402e1024u #define CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__SIZE 0x00000010u @@ -8210,14 +7432,6 @@ #define CYFLD_BLE_BLELL_SCAN_FILT_POLICY__SIZE 0x00000002u #define CYFLD_BLE_BLELL_DUP_FILT_EN__OFFSET 0x00000005u #define CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET 0x00000008u -#define CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE 0x00000001u #define CYREG_BLE_BLELL_SCAN_INTR 0x402e1038u #define CYFLD_BLE_BLELL_SCAN_STRT_INTR__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_SCAN_STRT_INTR__SIZE 0x00000001u @@ -8229,18 +7443,8 @@ #define CYFLD_BLE_BLELL_ADV_RX_INTR__SIZE 0x00000001u #define CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET 0x00000004u #define CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__OFFSET 0x00000005u -#define CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE 0x00000001u #define CYFLD_BLE_BLELL_SCAN_ON__OFFSET 0x00000008u #define CYFLD_BLE_BLELL_SCAN_ON__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x0000000au -#define CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001u #define CYREG_BLE_BLELL_SCAN_NEXT_INSTANT 0x402e103cu #define CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__SIZE 0x00000010u @@ -8255,8 +7459,6 @@ #define CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__SIZE 0x00000001u #define CYFLD_BLE_BLELL_INIT_FILT_POLICY__OFFSET 0x00000003u #define CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__OFFSET 0x00000004u -#define CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE 0x00000001u #define CYREG_BLE_BLELL_INIT_INTR 0x402e1050u #define CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__SIZE 0x00000001u @@ -8266,16 +7468,6 @@ #define CYFLD_BLE_BLELL_INIT_TX_START_INTR__SIZE 0x00000001u #define CYFLD_BLE_BLELL_MASTER_CONN_CREATED__OFFSET 0x00000004u #define CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__OFFSET 0x00000005u -#define CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x00000008u -#define CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001u #define CYREG_BLE_BLELL_INIT_NEXT_INSTANT 0x402e1054u #define CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__SIZE 0x00000010u @@ -8470,7 +7662,7 @@ #define CYFLD_BLE_BLELL_LLID__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_LLID__SIZE 0x00000002u #define CYFLD_BLE_BLELL_DATA_LENGTH__OFFSET 0x00000002u -#define CYFLD_BLE_BLELL_DATA_LENGTH__SIZE 0x00000008u +#define CYFLD_BLE_BLELL_DATA_LENGTH__SIZE 0x00000005u #define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1 0x402e1144u #define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2 0x402e1148u #define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3 0x402e114cu @@ -8493,9 +7685,6 @@ #define CYREG_BLE_BLELL_DTM_RX_PKT_COUNT 0x402e1174u #define CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE 0x00000010u -#define CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT 0x402e1178u -#define CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_TEST_LENGTH_EXT__SIZE 0x00000003u #define CYREG_BLE_BLELL_TXRX_HOP 0x402e1188u #define CYFLD_BLE_BLELL_HOP_CH_TX__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_HOP_CH_TX__SIZE 0x00000007u @@ -8540,10 +7729,6 @@ #define CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__SIZE 0x00000001u #define CYFLD_BLE_BLELL_ADV_RAND_DISABLE__OFFSET 0x00000008u #define CYFLD_BLE_BLELL_ADV_RAND_DISABLE__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__OFFSET 0x0000000au -#define CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__SIZE 0x00000001u #define CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__OFFSET 0x0000000bu #define CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__SIZE 0x00000005u #define CYREG_BLE_BLELL_SCAN_CONFIG 0x402e11d8u @@ -8557,14 +7742,6 @@ #define CYFLD_BLE_BLELL_ADV_RX_EN__SIZE 0x00000001u #define CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET 0x00000004u #define CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET 0x00000005u -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET 0x00000008u -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE 0x00000001u #define CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET 0x0000000bu #define CYFLD_BLE_BLELL_BACKOFF_ENABLE__SIZE 0x00000001u #define CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__OFFSET 0x0000000du @@ -8578,12 +7755,6 @@ #define CYFLD_BLE_BLELL_CONN_REQ_TX_EN__SIZE 0x00000001u #define CYFLD_BLE_BLELL_CONN_CREATED__OFFSET 0x00000004u #define CYFLD_BLE_BLELL_CONN_CREATED__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__OFFSET 0x00000005u -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE 0x00000001u #define CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__OFFSET 0x0000000du #define CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__SIZE 0x00000003u #define CYREG_BLE_BLELL_CONN_CONFIG 0x402e11e0u @@ -8795,10 +7966,6 @@ #define CYFLD_BLE_BLELL_PAYLOAD_LENGTH__SIZE 0x00000005u #define CYFLD_BLE_BLELL_DIRECTION__OFFSET 0x00000007u #define CYFLD_BLE_BLELL_DIRECTION__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__OFFSET 0x00000008u -#define CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__SIZE 0x00000003u -#define CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__OFFSET 0x0000000bu -#define CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE 0x00000001u #define CYREG_BLE_BLELL_ENC_CONFIG 0x402e1490u #define CYFLD_BLE_BLELL_START_PROC__OFFSET 0x00000000u #define CYFLD_BLE_BLELL_START_PROC__SIZE 0x00000001u @@ -8873,97 +8040,6 @@ #define CYFLD_BLE_BLELL_RX_EN_DELAY__SIZE 0x00000008u #define CYFLD_BLE_BLELL_TX_EN_DELAY__OFFSET 0x00000008u #define CYFLD_BLE_BLELL_TX_EN_DELAY__SIZE 0x00000008u -#define CYREG_BLE_BLELL_LL_CONTROL 0x402e1f00u -#define CYFLD_BLE_BLELL_PRIV_1_2__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_PRIV_1_2__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_DLE__OFFSET 0x00000001u -#define CYFLD_BLE_BLELL_DLE__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_WL_READ_AS_MEM__OFFSET 0x00000002u -#define CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__OFFSET 0x00000003u -#define CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__OFFSET 0x00000004u -#define CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET 0x00000005u -#define CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET 0x00000008u -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET 0x0000000au -#define CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET 0x0000000bu -#define CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET 0x0000000cu -#define CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__OFFSET 0x0000000du -#define CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__OFFSET 0x0000000eu -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__OFFSET 0x0000000fu -#define CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE 0x00000001u -#define CYREG_BLE_BLELL_DEV_PA_ADDR_L 0x402e1f04u -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_L__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_L__SIZE 0x00000010u -#define CYREG_BLE_BLELL_DEV_PA_ADDR_M 0x402e1f08u -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_M__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_M__SIZE 0x00000010u -#define CYREG_BLE_BLELL_DEV_PA_ADDR_H 0x402e1f0cu -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_H__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_H__SIZE 0x00000010u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 0x402e1f10u -#define CYFLD_BLE_BLELL_VALID_ENTRY__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_VALID_ENTRY__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET 0x00000001u -#define CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET 0x00000002u -#define CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_WHITELISTED_PEER__OFFSET 0x00000003u -#define CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET 0x00000004u -#define CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET 0x00000005u -#define CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET 0x00000006u -#define CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET 0x00000007u -#define CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET 0x00000008u -#define CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE 0x00000001u -#define CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET 0x00000009u -#define CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE 0x00000001u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 0x402e1f14u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 0x402e1f18u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 0x402e1f1cu -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 0x402e1f20u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 0x402e1f24u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 0x402e1f28u -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 0x402e1f2cu -#define CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR 0x402e2000u -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE 0x00000010u -#define CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR 0x402e2060u -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE 0x00000010u -#define CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR 0x402e20c0u -#define CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE 0x00000010u -#define CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR 0x402e2120u -#define CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE 0x00000010u -#define CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR 0x402e2200u -#define CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__SIZE 0x00000010u -#define CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE 0x402e2800u -#define CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__SIZE 0x00000010u -#define CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE 0x402e3000u -#define CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__OFFSET 0x00000000u -#define CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__SIZE 0x00000010u #define CYDEV_BLE_BLESS_BASE 0x402ef000u #define CYDEV_BLE_BLESS_SIZE 0x00001000u #define CYREG_BLE_BLESS_WCO_CONFIG 0x402ef000u @@ -9020,8 +8096,6 @@ #define CYREG_BLE_BLESS_LF_CLK_CTRL 0x402ef074u #define CYFLD_BLE_BLESS_DISABLE_LF_CLK__OFFSET 0x00000000u #define CYFLD_BLE_BLESS_DISABLE_LF_CLK__SIZE 0x00000001u -#define CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__OFFSET 0x0000001du -#define CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__SIZE 0x00000003u #define CYREG_BLE_BLESS_WCO_TRIM 0x402eff00u #define CYFLD_BLE_BLESS_XGM__OFFSET 0x00000000u #define CYFLD_BLE_BLESS_XGM__SIZE 0x00000003u @@ -9917,8 +8991,8 @@ #define CYREG_ROMTABLE_CID1 0xf0000ff4u #define CYREG_ROMTABLE_CID2 0xf0000ff8u #define CYREG_ROMTABLE_CID3 0xf0000ffcu -#define CYDEV_FLS_SECTOR_SIZE 0x00020000u -#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000080u #define CYREG_SFLASH_PROT_ROW00 CYREG_SFLASH_PROT_ROW0 #define CYREG_SFLASH_PROT_ROW01 CYREG_SFLASH_PROT_ROW1 #define CYREG_SFLASH_PROT_ROW02 CYREG_SFLASH_PROT_ROW2 diff --git a/BLE.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc b/BLE.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc index 915165b..f88b6b2 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc +++ b/BLE.cydsn/Generated_Source/PSoC4/cydevicegnu_trm.inc @@ -15,11 +15,11 @@ ********************************************************************************/ .set CYDEV_FLASH_BASE, 0x00000000 -.set CYDEV_FLASH_SIZE, 0x00040000 +.set CYDEV_FLASH_SIZE, 0x00020000 .set CYREG_FLASH_DATA_MBASE, 0x00000000 -.set CYREG_FLASH_DATA_MSIZE, 0x00040000 +.set CYREG_FLASH_DATA_MSIZE, 0x00020000 .set CYDEV_SFLASH_BASE, 0x0ffff000 -.set CYDEV_SFLASH_SIZE, 0x00001000 +.set CYDEV_SFLASH_SIZE, 0x00000800 .set CYREG_SFLASH_PROT_ROW0, 0x0ffff000 .set CYFLD_SFLASH_DATA8__OFFSET, 0x00000000 .set CYFLD_SFLASH_DATA8__SIZE, 0x00000008 @@ -86,102 +86,102 @@ .set CYREG_SFLASH_PROT_ROW61, 0x0ffff03d .set CYREG_SFLASH_PROT_ROW62, 0x0ffff03e .set CYREG_SFLASH_PROT_ROW63, 0x0ffff03f -.set CYREG_SFLASH_PROT_PROTECTION, 0x0ffff0ff +.set CYREG_SFLASH_PROT_PROTECTION, 0x0ffff07f .set CYFLD_SFLASH_PROT_LEVEL__OFFSET, 0x00000000 .set CYFLD_SFLASH_PROT_LEVEL__SIZE, 0x00000002 .set CYVAL_SFLASH_PROT_LEVEL_VIRGIN, 0x00000001 .set CYVAL_SFLASH_PROT_LEVEL_OPEN, 0x00000000 .set CYVAL_SFLASH_PROT_LEVEL_PROTECTED, 0x00000002 .set CYVAL_SFLASH_PROT_LEVEL_KILL, 0x00000003 -.set CYREG_SFLASH_AV_PAIRS_8B0, 0x0ffff100 -.set CYREG_SFLASH_AV_PAIRS_8B1, 0x0ffff101 -.set CYREG_SFLASH_AV_PAIRS_8B2, 0x0ffff102 -.set CYREG_SFLASH_AV_PAIRS_8B3, 0x0ffff103 -.set CYREG_SFLASH_AV_PAIRS_8B4, 0x0ffff104 -.set CYREG_SFLASH_AV_PAIRS_8B5, 0x0ffff105 -.set CYREG_SFLASH_AV_PAIRS_8B6, 0x0ffff106 -.set CYREG_SFLASH_AV_PAIRS_8B7, 0x0ffff107 -.set CYREG_SFLASH_AV_PAIRS_8B8, 0x0ffff108 -.set CYREG_SFLASH_AV_PAIRS_8B9, 0x0ffff109 -.set CYREG_SFLASH_AV_PAIRS_8B10, 0x0ffff10a -.set CYREG_SFLASH_AV_PAIRS_8B11, 0x0ffff10b -.set CYREG_SFLASH_AV_PAIRS_8B12, 0x0ffff10c -.set CYREG_SFLASH_AV_PAIRS_8B13, 0x0ffff10d -.set CYREG_SFLASH_AV_PAIRS_8B14, 0x0ffff10e -.set CYREG_SFLASH_AV_PAIRS_8B15, 0x0ffff10f -.set CYREG_SFLASH_AV_PAIRS_8B16, 0x0ffff110 -.set CYREG_SFLASH_AV_PAIRS_8B17, 0x0ffff111 -.set CYREG_SFLASH_AV_PAIRS_8B18, 0x0ffff112 -.set CYREG_SFLASH_AV_PAIRS_8B19, 0x0ffff113 -.set CYREG_SFLASH_AV_PAIRS_8B20, 0x0ffff114 -.set CYREG_SFLASH_AV_PAIRS_8B21, 0x0ffff115 -.set CYREG_SFLASH_AV_PAIRS_8B22, 0x0ffff116 -.set CYREG_SFLASH_AV_PAIRS_8B23, 0x0ffff117 -.set CYREG_SFLASH_AV_PAIRS_8B24, 0x0ffff118 -.set CYREG_SFLASH_AV_PAIRS_8B25, 0x0ffff119 -.set CYREG_SFLASH_AV_PAIRS_8B26, 0x0ffff11a -.set CYREG_SFLASH_AV_PAIRS_8B27, 0x0ffff11b -.set CYREG_SFLASH_AV_PAIRS_8B28, 0x0ffff11c -.set CYREG_SFLASH_AV_PAIRS_8B29, 0x0ffff11d -.set CYREG_SFLASH_AV_PAIRS_8B30, 0x0ffff11e -.set CYREG_SFLASH_AV_PAIRS_8B31, 0x0ffff11f -.set CYREG_SFLASH_AV_PAIRS_8B32, 0x0ffff120 -.set CYREG_SFLASH_AV_PAIRS_8B33, 0x0ffff121 -.set CYREG_SFLASH_AV_PAIRS_8B34, 0x0ffff122 -.set CYREG_SFLASH_AV_PAIRS_8B35, 0x0ffff123 -.set CYREG_SFLASH_AV_PAIRS_8B36, 0x0ffff124 -.set CYREG_SFLASH_AV_PAIRS_8B37, 0x0ffff125 -.set CYREG_SFLASH_AV_PAIRS_8B38, 0x0ffff126 -.set CYREG_SFLASH_AV_PAIRS_8B39, 0x0ffff127 -.set CYREG_SFLASH_AV_PAIRS_8B40, 0x0ffff128 -.set CYREG_SFLASH_AV_PAIRS_8B41, 0x0ffff129 -.set CYREG_SFLASH_AV_PAIRS_8B42, 0x0ffff12a -.set CYREG_SFLASH_AV_PAIRS_8B43, 0x0ffff12b -.set CYREG_SFLASH_AV_PAIRS_8B44, 0x0ffff12c -.set CYREG_SFLASH_AV_PAIRS_8B45, 0x0ffff12d -.set CYREG_SFLASH_AV_PAIRS_8B46, 0x0ffff12e -.set CYREG_SFLASH_AV_PAIRS_8B47, 0x0ffff12f -.set CYREG_SFLASH_AV_PAIRS_8B48, 0x0ffff130 -.set CYREG_SFLASH_AV_PAIRS_8B49, 0x0ffff131 -.set CYREG_SFLASH_AV_PAIRS_8B50, 0x0ffff132 -.set CYREG_SFLASH_AV_PAIRS_8B51, 0x0ffff133 -.set CYREG_SFLASH_AV_PAIRS_8B52, 0x0ffff134 -.set CYREG_SFLASH_AV_PAIRS_8B53, 0x0ffff135 -.set CYREG_SFLASH_AV_PAIRS_8B54, 0x0ffff136 -.set CYREG_SFLASH_AV_PAIRS_8B55, 0x0ffff137 -.set CYREG_SFLASH_AV_PAIRS_8B56, 0x0ffff138 -.set CYREG_SFLASH_AV_PAIRS_8B57, 0x0ffff139 -.set CYREG_SFLASH_AV_PAIRS_8B58, 0x0ffff13a -.set CYREG_SFLASH_AV_PAIRS_8B59, 0x0ffff13b -.set CYREG_SFLASH_AV_PAIRS_8B60, 0x0ffff13c -.set CYREG_SFLASH_AV_PAIRS_8B61, 0x0ffff13d -.set CYREG_SFLASH_AV_PAIRS_8B62, 0x0ffff13e -.set CYREG_SFLASH_AV_PAIRS_8B63, 0x0ffff13f -.set CYREG_SFLASH_AV_PAIRS_8B64, 0x0ffff140 -.set CYREG_SFLASH_AV_PAIRS_8B65, 0x0ffff141 -.set CYREG_SFLASH_AV_PAIRS_8B66, 0x0ffff142 -.set CYREG_SFLASH_AV_PAIRS_8B67, 0x0ffff143 -.set CYREG_SFLASH_AV_PAIRS_8B68, 0x0ffff144 -.set CYREG_SFLASH_AV_PAIRS_8B69, 0x0ffff145 -.set CYREG_SFLASH_AV_PAIRS_8B70, 0x0ffff146 -.set CYREG_SFLASH_AV_PAIRS_8B71, 0x0ffff147 -.set CYREG_SFLASH_AV_PAIRS_8B72, 0x0ffff148 -.set CYREG_SFLASH_AV_PAIRS_8B73, 0x0ffff149 -.set CYREG_SFLASH_AV_PAIRS_8B74, 0x0ffff14a -.set CYREG_SFLASH_AV_PAIRS_8B75, 0x0ffff14b -.set CYREG_SFLASH_AV_PAIRS_8B76, 0x0ffff14c -.set CYREG_SFLASH_AV_PAIRS_8B77, 0x0ffff14d -.set CYREG_SFLASH_AV_PAIRS_8B78, 0x0ffff14e -.set CYREG_SFLASH_AV_PAIRS_8B79, 0x0ffff14f -.set CYREG_SFLASH_AV_PAIRS_8B80, 0x0ffff150 -.set CYREG_SFLASH_AV_PAIRS_8B81, 0x0ffff151 -.set CYREG_SFLASH_AV_PAIRS_8B82, 0x0ffff152 -.set CYREG_SFLASH_AV_PAIRS_8B83, 0x0ffff153 -.set CYREG_SFLASH_AV_PAIRS_8B84, 0x0ffff154 -.set CYREG_SFLASH_AV_PAIRS_8B85, 0x0ffff155 -.set CYREG_SFLASH_AV_PAIRS_8B86, 0x0ffff156 -.set CYREG_SFLASH_AV_PAIRS_8B87, 0x0ffff157 -.set CYREG_SFLASH_BLESS_BB_BUMP2, 0x0ffff158 +.set CYREG_SFLASH_AV_PAIRS_8B0, 0x0ffff080 +.set CYREG_SFLASH_AV_PAIRS_8B1, 0x0ffff081 +.set CYREG_SFLASH_AV_PAIRS_8B2, 0x0ffff082 +.set CYREG_SFLASH_AV_PAIRS_8B3, 0x0ffff083 +.set CYREG_SFLASH_AV_PAIRS_8B4, 0x0ffff084 +.set CYREG_SFLASH_AV_PAIRS_8B5, 0x0ffff085 +.set CYREG_SFLASH_AV_PAIRS_8B6, 0x0ffff086 +.set CYREG_SFLASH_AV_PAIRS_8B7, 0x0ffff087 +.set CYREG_SFLASH_AV_PAIRS_8B8, 0x0ffff088 +.set CYREG_SFLASH_AV_PAIRS_8B9, 0x0ffff089 +.set CYREG_SFLASH_AV_PAIRS_8B10, 0x0ffff08a +.set CYREG_SFLASH_AV_PAIRS_8B11, 0x0ffff08b +.set CYREG_SFLASH_AV_PAIRS_8B12, 0x0ffff08c +.set CYREG_SFLASH_AV_PAIRS_8B13, 0x0ffff08d +.set CYREG_SFLASH_AV_PAIRS_8B14, 0x0ffff08e +.set CYREG_SFLASH_AV_PAIRS_8B15, 0x0ffff08f +.set CYREG_SFLASH_AV_PAIRS_8B16, 0x0ffff090 +.set CYREG_SFLASH_AV_PAIRS_8B17, 0x0ffff091 +.set CYREG_SFLASH_AV_PAIRS_8B18, 0x0ffff092 +.set CYREG_SFLASH_AV_PAIRS_8B19, 0x0ffff093 +.set CYREG_SFLASH_AV_PAIRS_8B20, 0x0ffff094 +.set CYREG_SFLASH_AV_PAIRS_8B21, 0x0ffff095 +.set CYREG_SFLASH_AV_PAIRS_8B22, 0x0ffff096 +.set CYREG_SFLASH_AV_PAIRS_8B23, 0x0ffff097 +.set CYREG_SFLASH_AV_PAIRS_8B24, 0x0ffff098 +.set CYREG_SFLASH_AV_PAIRS_8B25, 0x0ffff099 +.set CYREG_SFLASH_AV_PAIRS_8B26, 0x0ffff09a +.set CYREG_SFLASH_AV_PAIRS_8B27, 0x0ffff09b +.set CYREG_SFLASH_AV_PAIRS_8B28, 0x0ffff09c +.set CYREG_SFLASH_AV_PAIRS_8B29, 0x0ffff09d +.set CYREG_SFLASH_AV_PAIRS_8B30, 0x0ffff09e +.set CYREG_SFLASH_AV_PAIRS_8B31, 0x0ffff09f +.set CYREG_SFLASH_AV_PAIRS_8B32, 0x0ffff0a0 +.set CYREG_SFLASH_AV_PAIRS_8B33, 0x0ffff0a1 +.set CYREG_SFLASH_AV_PAIRS_8B34, 0x0ffff0a2 +.set CYREG_SFLASH_AV_PAIRS_8B35, 0x0ffff0a3 +.set CYREG_SFLASH_AV_PAIRS_8B36, 0x0ffff0a4 +.set CYREG_SFLASH_AV_PAIRS_8B37, 0x0ffff0a5 +.set CYREG_SFLASH_AV_PAIRS_8B38, 0x0ffff0a6 +.set CYREG_SFLASH_AV_PAIRS_8B39, 0x0ffff0a7 +.set CYREG_SFLASH_AV_PAIRS_8B40, 0x0ffff0a8 +.set CYREG_SFLASH_AV_PAIRS_8B41, 0x0ffff0a9 +.set CYREG_SFLASH_AV_PAIRS_8B42, 0x0ffff0aa +.set CYREG_SFLASH_AV_PAIRS_8B43, 0x0ffff0ab +.set CYREG_SFLASH_AV_PAIRS_8B44, 0x0ffff0ac +.set CYREG_SFLASH_AV_PAIRS_8B45, 0x0ffff0ad +.set CYREG_SFLASH_AV_PAIRS_8B46, 0x0ffff0ae +.set CYREG_SFLASH_AV_PAIRS_8B47, 0x0ffff0af +.set CYREG_SFLASH_AV_PAIRS_8B48, 0x0ffff0b0 +.set CYREG_SFLASH_AV_PAIRS_8B49, 0x0ffff0b1 +.set CYREG_SFLASH_AV_PAIRS_8B50, 0x0ffff0b2 +.set CYREG_SFLASH_AV_PAIRS_8B51, 0x0ffff0b3 +.set CYREG_SFLASH_AV_PAIRS_8B52, 0x0ffff0b4 +.set CYREG_SFLASH_AV_PAIRS_8B53, 0x0ffff0b5 +.set CYREG_SFLASH_AV_PAIRS_8B54, 0x0ffff0b6 +.set CYREG_SFLASH_AV_PAIRS_8B55, 0x0ffff0b7 +.set CYREG_SFLASH_AV_PAIRS_8B56, 0x0ffff0b8 +.set CYREG_SFLASH_AV_PAIRS_8B57, 0x0ffff0b9 +.set CYREG_SFLASH_AV_PAIRS_8B58, 0x0ffff0ba +.set CYREG_SFLASH_AV_PAIRS_8B59, 0x0ffff0bb +.set CYREG_SFLASH_AV_PAIRS_8B60, 0x0ffff0bc +.set CYREG_SFLASH_AV_PAIRS_8B61, 0x0ffff0bd +.set CYREG_SFLASH_AV_PAIRS_8B62, 0x0ffff0be +.set CYREG_SFLASH_AV_PAIRS_8B63, 0x0ffff0bf +.set CYREG_SFLASH_AV_PAIRS_8B64, 0x0ffff0c0 +.set CYREG_SFLASH_AV_PAIRS_8B65, 0x0ffff0c1 +.set CYREG_SFLASH_AV_PAIRS_8B66, 0x0ffff0c2 +.set CYREG_SFLASH_AV_PAIRS_8B67, 0x0ffff0c3 +.set CYREG_SFLASH_AV_PAIRS_8B68, 0x0ffff0c4 +.set CYREG_SFLASH_AV_PAIRS_8B69, 0x0ffff0c5 +.set CYREG_SFLASH_AV_PAIRS_8B70, 0x0ffff0c6 +.set CYREG_SFLASH_AV_PAIRS_8B71, 0x0ffff0c7 +.set CYREG_SFLASH_AV_PAIRS_8B72, 0x0ffff0c8 +.set CYREG_SFLASH_AV_PAIRS_8B73, 0x0ffff0c9 +.set CYREG_SFLASH_AV_PAIRS_8B74, 0x0ffff0ca +.set CYREG_SFLASH_AV_PAIRS_8B75, 0x0ffff0cb +.set CYREG_SFLASH_AV_PAIRS_8B76, 0x0ffff0cc +.set CYREG_SFLASH_AV_PAIRS_8B77, 0x0ffff0cd +.set CYREG_SFLASH_AV_PAIRS_8B78, 0x0ffff0ce +.set CYREG_SFLASH_AV_PAIRS_8B79, 0x0ffff0cf +.set CYREG_SFLASH_AV_PAIRS_8B80, 0x0ffff0d0 +.set CYREG_SFLASH_AV_PAIRS_8B81, 0x0ffff0d1 +.set CYREG_SFLASH_AV_PAIRS_8B82, 0x0ffff0d2 +.set CYREG_SFLASH_AV_PAIRS_8B83, 0x0ffff0d3 +.set CYREG_SFLASH_AV_PAIRS_8B84, 0x0ffff0d4 +.set CYREG_SFLASH_AV_PAIRS_8B85, 0x0ffff0d5 +.set CYREG_SFLASH_AV_PAIRS_8B86, 0x0ffff0d6 +.set CYREG_SFLASH_AV_PAIRS_8B87, 0x0ffff0d7 +.set CYREG_SFLASH_BLESS_BB_BUMP2, 0x0ffff0d8 .set CYFLD_SFLASH_V2I_RCAL__OFFSET, 0x00000000 .set CYFLD_SFLASH_V2I_RCAL__SIZE, 0x00000005 .set CYFLD_SFLASH_V2I__OFFSET, 0x00000005 @@ -190,9 +190,9 @@ .set CYFLD_SFLASH_VBG_TRIM__SIZE, 0x00000003 .set CYFLD_SFLASH_SY_IBIAS__OFFSET, 0x0000000d .set CYFLD_SFLASH_SY_IBIAS__SIZE, 0x00000003 -.set CYREG_SFLASH_AV_PAIRS_8B88, 0x0ffff158 -.set CYREG_SFLASH_AV_PAIRS_8B89, 0x0ffff159 -.set CYREG_SFLASH_BLESS_BB_XO, 0x0ffff15a +.set CYREG_SFLASH_AV_PAIRS_8B88, 0x0ffff0d8 +.set CYREG_SFLASH_AV_PAIRS_8B89, 0x0ffff0d9 +.set CYREG_SFLASH_BLESS_BB_XO, 0x0ffff0da .set CYFLD_SFLASH_DIS_XOCORE_SUPFILT__OFFSET, 0x00000000 .set CYFLD_SFLASH_DIS_XOCORE_SUPFILT__SIZE, 0x00000001 .set CYFLD_SFLASH_EN_RE_FASTSTART__OFFSET, 0x00000001 @@ -213,10 +213,10 @@ .set CYFLD_SFLASH_CTRL_RPREF__SIZE, 0x00000002 .set CYFLD_SFLASH_rev_bb_xo__OFFSET, 0x0000000f .set CYFLD_SFLASH_rev_bb_xo__SIZE, 0x00000001 -.set CYREG_SFLASH_AV_PAIRS_8B90, 0x0ffff15a -.set CYREG_SFLASH_AV_PAIRS_8B91, 0x0ffff15b -.set CYREG_SFLASH_AV_PAIRS_8B92, 0x0ffff15c -.set CYREG_SFLASH_BLESS_SY_BUMP1, 0x0ffff15c +.set CYREG_SFLASH_AV_PAIRS_8B90, 0x0ffff0da +.set CYREG_SFLASH_AV_PAIRS_8B91, 0x0ffff0db +.set CYREG_SFLASH_AV_PAIRS_8B92, 0x0ffff0dc +.set CYREG_SFLASH_BLESS_SY_BUMP1, 0x0ffff0dc .set CYFLD_SFLASH_VCO__OFFSET, 0x00000000 .set CYFLD_SFLASH_VCO__SIZE, 0x00000004 .set CYFLD_SFLASH_LOFB_POWERSAVE__OFFSET, 0x00000004 @@ -229,9 +229,9 @@ .set CYFLD_SFLASH_LOPATH__SIZE, 0x00000004 .set CYFLD_SFLASH_PDCPLPF__OFFSET, 0x0000000c .set CYFLD_SFLASH_PDCPLPF__SIZE, 0x00000004 -.set CYREG_SFLASH_AV_PAIRS_8B93, 0x0ffff15d -.set CYREG_SFLASH_AV_PAIRS_8B94, 0x0ffff15e -.set CYREG_SFLASH_BLESS_LDO, 0x0ffff15e +.set CYREG_SFLASH_AV_PAIRS_8B93, 0x0ffff0dd +.set CYREG_SFLASH_AV_PAIRS_8B94, 0x0ffff0de +.set CYREG_SFLASH_BLESS_LDO, 0x0ffff0de .set CYFLD_SFLASH_BUMP_BALUM_HF__OFFSET, 0x00000000 .set CYFLD_SFLASH_BUMP_BALUM_HF__SIZE, 0x00000003 .set CYFLD_SFLASH_BUMP_SY_VCO__OFFSET, 0x00000003 @@ -244,161 +244,115 @@ .set CYFLD_SFLASH_BUMP_SY_FFFB__SIZE, 0x00000003 .set CYFLD_SFLASH_REV_LDO__OFFSET, 0x0000000c .set CYFLD_SFLASH_REV_LDO__SIZE, 0x00000004 -.set CYREG_SFLASH_AV_PAIRS_8B95, 0x0ffff15f -.set CYREG_SFLASH_AV_PAIRS_8B96, 0x0ffff160 -.set CYREG_SFLASH_AV_PAIRS_8B97, 0x0ffff161 -.set CYREG_SFLASH_AV_PAIRS_8B98, 0x0ffff162 -.set CYREG_SFLASH_AV_PAIRS_8B99, 0x0ffff163 -.set CYREG_SFLASH_AV_PAIRS_8B100, 0x0ffff164 -.set CYREG_SFLASH_AV_PAIRS_8B101, 0x0ffff165 -.set CYREG_SFLASH_AV_PAIRS_8B102, 0x0ffff166 -.set CYREG_SFLASH_AV_PAIRS_8B103, 0x0ffff167 -.set CYREG_SFLASH_AV_PAIRS_8B104, 0x0ffff168 -.set CYREG_SFLASH_AV_PAIRS_8B105, 0x0ffff169 -.set CYREG_SFLASH_AV_PAIRS_8B106, 0x0ffff16a -.set CYREG_SFLASH_AV_PAIRS_8B107, 0x0ffff16b -.set CYREG_SFLASH_AV_PAIRS_8B108, 0x0ffff16c -.set CYREG_SFLASH_AV_PAIRS_8B109, 0x0ffff16d -.set CYREG_SFLASH_AV_PAIRS_8B110, 0x0ffff16e -.set CYREG_SFLASH_AV_PAIRS_8B111, 0x0ffff16f -.set CYREG_SFLASH_AV_PAIRS_8B112, 0x0ffff170 -.set CYREG_SFLASH_AV_PAIRS_8B113, 0x0ffff171 -.set CYREG_SFLASH_AV_PAIRS_8B114, 0x0ffff172 -.set CYREG_SFLASH_AV_PAIRS_8B115, 0x0ffff173 -.set CYREG_SFLASH_AV_PAIRS_8B116, 0x0ffff174 -.set CYREG_SFLASH_AV_PAIRS_8B117, 0x0ffff175 -.set CYREG_SFLASH_AV_PAIRS_8B118, 0x0ffff176 -.set CYREG_SFLASH_AV_PAIRS_8B119, 0x0ffff177 -.set CYREG_SFLASH_AV_PAIRS_8B120, 0x0ffff178 -.set CYREG_SFLASH_AV_PAIRS_8B121, 0x0ffff179 -.set CYREG_SFLASH_AV_PAIRS_8B122, 0x0ffff17a -.set CYREG_SFLASH_AV_PAIRS_8B123, 0x0ffff17b -.set CYREG_SFLASH_AV_PAIRS_8B124, 0x0ffff17c -.set CYREG_SFLASH_AV_PAIRS_8B125, 0x0ffff17d -.set CYREG_SFLASH_AV_PAIRS_8B126, 0x0ffff17e -.set CYREG_SFLASH_AV_PAIRS_8B127, 0x0ffff17f -.set CYREG_SFLASH_AV_PAIRS_32B0, 0x0ffff200 +.set CYREG_SFLASH_AV_PAIRS_8B95, 0x0ffff0df +.set CYREG_SFLASH_AV_PAIRS_8B96, 0x0ffff0e0 +.set CYREG_SFLASH_AV_PAIRS_8B97, 0x0ffff0e1 +.set CYREG_SFLASH_AV_PAIRS_8B98, 0x0ffff0e2 +.set CYREG_SFLASH_AV_PAIRS_8B99, 0x0ffff0e3 +.set CYREG_SFLASH_AV_PAIRS_8B100, 0x0ffff0e4 +.set CYREG_SFLASH_AV_PAIRS_8B101, 0x0ffff0e5 +.set CYREG_SFLASH_AV_PAIRS_8B102, 0x0ffff0e6 +.set CYREG_SFLASH_AV_PAIRS_8B103, 0x0ffff0e7 +.set CYREG_SFLASH_AV_PAIRS_8B104, 0x0ffff0e8 +.set CYREG_SFLASH_AV_PAIRS_8B105, 0x0ffff0e9 +.set CYREG_SFLASH_AV_PAIRS_8B106, 0x0ffff0ea +.set CYREG_SFLASH_AV_PAIRS_8B107, 0x0ffff0eb +.set CYREG_SFLASH_AV_PAIRS_8B108, 0x0ffff0ec +.set CYREG_SFLASH_AV_PAIRS_8B109, 0x0ffff0ed +.set CYREG_SFLASH_AV_PAIRS_8B110, 0x0ffff0ee +.set CYREG_SFLASH_AV_PAIRS_8B111, 0x0ffff0ef +.set CYREG_SFLASH_AV_PAIRS_8B112, 0x0ffff0f0 +.set CYREG_SFLASH_AV_PAIRS_8B113, 0x0ffff0f1 +.set CYREG_SFLASH_AV_PAIRS_8B114, 0x0ffff0f2 +.set CYREG_SFLASH_AV_PAIRS_8B115, 0x0ffff0f3 +.set CYREG_SFLASH_AV_PAIRS_8B116, 0x0ffff0f4 +.set CYREG_SFLASH_AV_PAIRS_8B117, 0x0ffff0f5 +.set CYREG_SFLASH_AV_PAIRS_8B118, 0x0ffff0f6 +.set CYREG_SFLASH_AV_PAIRS_8B119, 0x0ffff0f7 +.set CYREG_SFLASH_AV_PAIRS_8B120, 0x0ffff0f8 +.set CYREG_SFLASH_AV_PAIRS_8B121, 0x0ffff0f9 +.set CYREG_SFLASH_AV_PAIRS_8B122, 0x0ffff0fa +.set CYREG_SFLASH_AV_PAIRS_8B123, 0x0ffff0fb +.set CYREG_SFLASH_AV_PAIRS_8B124, 0x0ffff0fc +.set CYREG_SFLASH_AV_PAIRS_8B125, 0x0ffff0fd +.set CYREG_SFLASH_AV_PAIRS_8B126, 0x0ffff0fe +.set CYREG_SFLASH_AV_PAIRS_8B127, 0x0ffff0ff +.set CYREG_SFLASH_AV_PAIRS_32B0, 0x0ffff100 .set CYFLD_SFLASH_DATA32__OFFSET, 0x00000000 .set CYFLD_SFLASH_DATA32__SIZE, 0x00000020 -.set CYREG_SFLASH_AV_PAIRS_32B1, 0x0ffff204 -.set CYREG_SFLASH_AV_PAIRS_32B2, 0x0ffff208 -.set CYREG_SFLASH_AV_PAIRS_32B3, 0x0ffff20c -.set CYREG_SFLASH_AV_PAIRS_32B4, 0x0ffff210 -.set CYREG_SFLASH_AV_PAIRS_32B5, 0x0ffff214 -.set CYREG_SFLASH_AV_PAIRS_32B6, 0x0ffff218 -.set CYREG_SFLASH_AV_PAIRS_32B7, 0x0ffff21c -.set CYREG_SFLASH_AV_PAIRS_32B8, 0x0ffff220 -.set CYREG_SFLASH_AV_PAIRS_32B9, 0x0ffff224 -.set CYREG_SFLASH_AV_PAIRS_32B10, 0x0ffff228 -.set CYREG_SFLASH_AV_PAIRS_32B11, 0x0ffff22c -.set CYREG_SFLASH_AV_PAIRS_32B12, 0x0ffff230 -.set CYREG_SFLASH_AV_PAIRS_32B13, 0x0ffff234 -.set CYREG_SFLASH_AV_PAIRS_32B14, 0x0ffff238 -.set CYREG_SFLASH_AV_PAIRS_32B15, 0x0ffff23c -.set CYREG_SFLASH_SILICON_ID, 0x0ffff244 +.set CYREG_SFLASH_AV_PAIRS_32B1, 0x0ffff104 +.set CYREG_SFLASH_AV_PAIRS_32B2, 0x0ffff108 +.set CYREG_SFLASH_AV_PAIRS_32B3, 0x0ffff10c +.set CYREG_SFLASH_AV_PAIRS_32B4, 0x0ffff110 +.set CYREG_SFLASH_AV_PAIRS_32B5, 0x0ffff114 +.set CYREG_SFLASH_AV_PAIRS_32B6, 0x0ffff118 +.set CYREG_SFLASH_AV_PAIRS_32B7, 0x0ffff11c +.set CYREG_SFLASH_AV_PAIRS_32B8, 0x0ffff120 +.set CYREG_SFLASH_AV_PAIRS_32B9, 0x0ffff124 +.set CYREG_SFLASH_AV_PAIRS_32B10, 0x0ffff128 +.set CYREG_SFLASH_AV_PAIRS_32B11, 0x0ffff12c +.set CYREG_SFLASH_AV_PAIRS_32B12, 0x0ffff130 +.set CYREG_SFLASH_AV_PAIRS_32B13, 0x0ffff134 +.set CYREG_SFLASH_AV_PAIRS_32B14, 0x0ffff138 +.set CYREG_SFLASH_AV_PAIRS_32B15, 0x0ffff13c +.set CYREG_SFLASH_SILICON_ID, 0x0ffff144 .set CYFLD_SFLASH_ID__OFFSET, 0x00000000 .set CYFLD_SFLASH_ID__SIZE, 0x00000010 -.set CYREG_SFLASH_HIB_KEY_DELAY, 0x0ffff250 +.set CYREG_SFLASH_HIB_KEY_DELAY, 0x0ffff150 .set CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET, 0x00000000 .set CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE, 0x0000000a -.set CYREG_SFLASH_DPSLP_KEY_DELAY, 0x0ffff252 -.set CYREG_SFLASH_SWD_CONFIG, 0x0ffff254 +.set CYREG_SFLASH_DPSLP_KEY_DELAY, 0x0ffff152 +.set CYREG_SFLASH_SWD_CONFIG, 0x0ffff154 .set CYFLD_SFLASH_SWD_SELECT__OFFSET, 0x00000000 .set CYFLD_SFLASH_SWD_SELECT__SIZE, 0x00000001 -.set CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0, 0x0ffff255 +.set CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0, 0x0ffff155 .set CYFLD_SFLASH_IDAC__OFFSET, 0x00000000 .set CYFLD_SFLASH_IDAC__SIZE, 0x00000005 .set CYFLD_SFLASH_SLOPE__OFFSET, 0x00000005 .set CYFLD_SFLASH_SLOPE__SIZE, 0x00000003 -.set CYREG_SFLASH_SWD_LISTEN, 0x0ffff258 +.set CYREG_SFLASH_SWD_LISTEN, 0x0ffff158 .set CYFLD_SFLASH_CYCLES__OFFSET, 0x00000000 .set CYFLD_SFLASH_CYCLES__SIZE, 0x00000020 -.set CYREG_SFLASH_FLASH_START, 0x0ffff25c +.set CYREG_SFLASH_FLASH_START, 0x0ffff15c .set CYFLD_SFLASH_ADDRESS__OFFSET, 0x00000000 .set CYFLD_SFLASH_ADDRESS__SIZE, 0x00000020 -.set CYREG_SFLASH_CSD_TRIM1_HVIDAC, 0x0ffff260 +.set CYREG_SFLASH_CSD_TRIM1_HVIDAC, 0x0ffff160 .set CYFLD_SFLASH_TRIM8__OFFSET, 0x00000000 .set CYFLD_SFLASH_TRIM8__SIZE, 0x00000008 -.set CYREG_SFLASH_CSD_TRIM2_HVIDAC, 0x0ffff261 -.set CYREG_SFLASH_CSD_TRIM1_CSD, 0x0ffff262 -.set CYREG_SFLASH_CSD_TRIM2_CSD, 0x0ffff263 -.set CYREG_SFLASH_SAR_TEMP_MULTIPLIER, 0x0ffff264 +.set CYREG_SFLASH_CSD_TRIM2_HVIDAC, 0x0ffff161 +.set CYREG_SFLASH_CSD_TRIM1_CSD, 0x0ffff162 +.set CYREG_SFLASH_CSD_TRIM2_CSD, 0x0ffff163 +.set CYREG_SFLASH_SAR_TEMP_MULTIPLIER, 0x0ffff164 .set CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET, 0x00000000 .set CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE, 0x00000010 -.set CYREG_SFLASH_SAR_TEMP_OFFSET, 0x0ffff266 +.set CYREG_SFLASH_SAR_TEMP_OFFSET, 0x0ffff166 .set CYFLD_SFLASH_TEMP_OFFSET__OFFSET, 0x00000000 .set CYFLD_SFLASH_TEMP_OFFSET__SIZE, 0x00000010 -.set CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0, 0x0ffff26c -.set CYFLD_SFLASH_FCAL_BIAS_SEL__OFFSET, 0x00000000 -.set CYFLD_SFLASH_FCAL_BIAS_SEL__SIZE, 0x00000002 -.set CYFLD_SFLASH_ACAP_BIAS_SEL__OFFSET, 0x00000002 -.set CYFLD_SFLASH_ACAP_BIAS_SEL__SIZE, 0x00000002 -.set CYFLD_SFLASH_ICP_XFACTOR__OFFSET, 0x00000004 -.set CYFLD_SFLASH_ICP_XFACTOR__SIZE, 0x00000002 -.set CYFLD_SFLASH_ICP_OFFSET__OFFSET, 0x00000006 -.set CYFLD_SFLASH_ICP_OFFSET__SIZE, 0x00000002 -.set CYFLD_SFLASH_CLKNC_MODE__OFFSET, 0x00000008 -.set CYFLD_SFLASH_CLKNC_MODE__SIZE, 0x00000001 -.set CYFLD_SFLASH_PUP_MON__OFFSET, 0x00000009 -.set CYFLD_SFLASH_PUP_MON__SIZE, 0x00000001 -.set CYFLD_SFLASH_VCTRL_PULLDN__OFFSET, 0x0000000a -.set CYFLD_SFLASH_VCTRL_PULLDN__SIZE, 0x00000001 -.set CYFLD_SFLASH_VMOD_PULLDN__OFFSET, 0x0000000b -.set CYFLD_SFLASH_VMOD_PULLDN__SIZE, 0x00000001 -.set CYFLD_SFLASH_RST_DLY__OFFSET, 0x0000000c -.set CYFLD_SFLASH_RST_DLY__SIZE, 0x00000002 -.set CYFLD_SFLASH_PDCP_OFFSET__OFFSET, 0x0000000e -.set CYFLD_SFLASH_PDCP_OFFSET__SIZE, 0x00000002 -.set CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1, 0x0ffff26d -.set CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0, 0x0ffff26e -.set CYFLD_SFLASH_LNA_IBIAS__OFFSET, 0x00000000 -.set CYFLD_SFLASH_LNA_IBIAS__SIZE, 0x00000002 -.set CYFLD_SFLASH_TIA_IBIAS__OFFSET, 0x00000002 -.set CYFLD_SFLASH_TIA_IBIAS__SIZE, 0x00000002 -.set CYFLD_SFLASH_CBPF_IBIAS__OFFSET, 0x00000004 -.set CYFLD_SFLASH_CBPF_IBIAS__SIZE, 0x00000002 -.set CYFLD_SFLASH_IF_CM_IBIAS__OFFSET, 0x00000006 -.set CYFLD_SFLASH_IF_CM_IBIAS__SIZE, 0x00000002 -.set CYFLD_SFLASH_CBPF_HIZ_ENABLE__OFFSET, 0x00000008 -.set CYFLD_SFLASH_CBPF_HIZ_ENABLE__SIZE, 0x00000001 -.set CYFLD_SFLASH_COMPLEX_DISABLE__OFFSET, 0x00000009 -.set CYFLD_SFLASH_COMPLEX_DISABLE__SIZE, 0x00000001 -.set CYFLD_SFLASH_SY_R2HIGHMODE__OFFSET, 0x0000000a -.set CYFLD_SFLASH_SY_R2HIGHMODE__SIZE, 0x00000001 -.set CYFLD_SFLASH_SY_HILINEARITYR2_MODE__OFFSET, 0x0000000b -.set CYFLD_SFLASH_SY_HILINEARITYR2_MODE__SIZE, 0x00000001 -.set CYFLD_SFLASH_SY_LOWKVAMODE__OFFSET, 0x0000000c -.set CYFLD_SFLASH_SY_LOWKVAMODE__SIZE, 0x00000001 -.set CYFLD_SFLASH_SY_LOWKVMMODE__OFFSET, 0x0000000d -.set CYFLD_SFLASH_SY_LOWKVMMODE__SIZE, 0x00000001 -.set CYFLD_SFLASH_REV_RX_BUMP2__OFFSET, 0x0000000e -.set CYFLD_SFLASH_REV_RX_BUMP2__SIZE, 0x00000002 -.set CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1, 0x0ffff26f -.set CYREG_SFLASH_PROT_VIRGINKEY0, 0x0ffff270 +.set CYREG_SFLASH_PROT_VIRGINKEY0, 0x0ffff170 .set CYFLD_SFLASH_KEY8__OFFSET, 0x00000000 .set CYFLD_SFLASH_KEY8__SIZE, 0x00000008 -.set CYREG_SFLASH_PROT_VIRGINKEY1, 0x0ffff271 -.set CYREG_SFLASH_PROT_VIRGINKEY2, 0x0ffff272 -.set CYREG_SFLASH_PROT_VIRGINKEY3, 0x0ffff273 -.set CYREG_SFLASH_PROT_VIRGINKEY4, 0x0ffff274 -.set CYREG_SFLASH_PROT_VIRGINKEY5, 0x0ffff275 -.set CYREG_SFLASH_PROT_VIRGINKEY6, 0x0ffff276 -.set CYREG_SFLASH_PROT_VIRGINKEY7, 0x0ffff277 -.set CYREG_SFLASH_DIE_LOT0, 0x0ffff278 +.set CYREG_SFLASH_PROT_VIRGINKEY1, 0x0ffff171 +.set CYREG_SFLASH_PROT_VIRGINKEY2, 0x0ffff172 +.set CYREG_SFLASH_PROT_VIRGINKEY3, 0x0ffff173 +.set CYREG_SFLASH_PROT_VIRGINKEY4, 0x0ffff174 +.set CYREG_SFLASH_PROT_VIRGINKEY5, 0x0ffff175 +.set CYREG_SFLASH_PROT_VIRGINKEY6, 0x0ffff176 +.set CYREG_SFLASH_PROT_VIRGINKEY7, 0x0ffff177 +.set CYREG_SFLASH_DIE_LOT0, 0x0ffff178 .set CYFLD_SFLASH_LOT__OFFSET, 0x00000000 .set CYFLD_SFLASH_LOT__SIZE, 0x00000008 -.set CYREG_SFLASH_DIE_LOT1, 0x0ffff279 -.set CYREG_SFLASH_DIE_LOT2, 0x0ffff27a -.set CYREG_SFLASH_DIE_WAFER, 0x0ffff27b +.set CYREG_SFLASH_DIE_LOT1, 0x0ffff179 +.set CYREG_SFLASH_DIE_LOT2, 0x0ffff17a +.set CYREG_SFLASH_DIE_WAFER, 0x0ffff17b .set CYFLD_SFLASH_WAFER__OFFSET, 0x00000000 .set CYFLD_SFLASH_WAFER__SIZE, 0x00000008 -.set CYREG_SFLASH_DIE_X, 0x0ffff27c +.set CYREG_SFLASH_DIE_X, 0x0ffff17c .set CYFLD_SFLASH_X__OFFSET, 0x00000000 .set CYFLD_SFLASH_X__SIZE, 0x00000008 -.set CYREG_SFLASH_DIE_Y, 0x0ffff27d +.set CYREG_SFLASH_DIE_Y, 0x0ffff17d .set CYFLD_SFLASH_Y__OFFSET, 0x00000000 .set CYFLD_SFLASH_Y__SIZE, 0x00000008 -.set CYREG_SFLASH_DIE_SORT, 0x0ffff27e +.set CYREG_SFLASH_DIE_SORT, 0x0ffff17e .set CYFLD_SFLASH_S1_PASS__OFFSET, 0x00000000 .set CYFLD_SFLASH_S1_PASS__SIZE, 0x00000001 .set CYFLD_SFLASH_S2_PASS__OFFSET, 0x00000001 @@ -411,1392 +365,880 @@ .set CYFLD_SFLASH_CHI_PASS__SIZE, 0x00000001 .set CYFLD_SFLASH_ENG_PASS__OFFSET, 0x00000005 .set CYFLD_SFLASH_ENG_PASS__SIZE, 0x00000001 -.set CYREG_SFLASH_DIE_MINOR, 0x0ffff27f +.set CYREG_SFLASH_DIE_MINOR, 0x0ffff17f .set CYFLD_SFLASH_MINOR__OFFSET, 0x00000000 .set CYFLD_SFLASH_MINOR__SIZE, 0x00000008 -.set CYREG_SFLASH_IMO_TRIM_USBMODE_24, 0x0ffff33e +.set CYREG_SFLASH_IMO_TRIM_USBMODE_24, 0x0ffff1be .set CYFLD_SFLASH_TRIM_24__OFFSET, 0x00000000 .set CYFLD_SFLASH_TRIM_24__SIZE, 0x00000008 -.set CYREG_SFLASH_IMO_TRIM_USBMODE_48, 0x0ffff33f -.set CYREG_SFLASH_IMO_MAXF0, 0x0ffff340 +.set CYREG_SFLASH_IMO_TRIM_USBMODE_48, 0x0ffff1bf +.set CYREG_SFLASH_IMO_MAXF0, 0x0ffff1c0 .set CYFLD_SFLASH_MAXFREQ__OFFSET, 0x00000000 .set CYFLD_SFLASH_MAXFREQ__SIZE, 0x00000006 -.set CYREG_SFLASH_IMO_ABS0, 0x0ffff341 +.set CYREG_SFLASH_IMO_ABS0, 0x0ffff1c1 .set CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET, 0x00000000 .set CYFLD_SFLASH_ABS_TRIM_IMO__SIZE, 0x00000006 -.set CYREG_SFLASH_IMO_TMPCO0, 0x0ffff342 +.set CYREG_SFLASH_IMO_TMPCO0, 0x0ffff1c2 .set CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET, 0x00000000 .set CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE, 0x00000006 -.set CYREG_SFLASH_IMO_MAXF1, 0x0ffff343 -.set CYREG_SFLASH_IMO_ABS1, 0x0ffff344 -.set CYREG_SFLASH_IMO_TMPCO1, 0x0ffff345 -.set CYREG_SFLASH_IMO_MAXF2, 0x0ffff346 -.set CYREG_SFLASH_IMO_ABS2, 0x0ffff347 -.set CYREG_SFLASH_IMO_TMPCO2, 0x0ffff348 -.set CYREG_SFLASH_IMO_MAXF3, 0x0ffff349 -.set CYREG_SFLASH_IMO_ABS3, 0x0ffff34a -.set CYREG_SFLASH_IMO_TMPCO3, 0x0ffff34b -.set CYREG_SFLASH_IMO_ABS4, 0x0ffff34c -.set CYREG_SFLASH_IMO_TMPCO4, 0x0ffff34d -.set CYREG_SFLASH_IMO_TRIM0, 0x0ffff350 +.set CYREG_SFLASH_IMO_MAXF1, 0x0ffff1c3 +.set CYREG_SFLASH_IMO_ABS1, 0x0ffff1c4 +.set CYREG_SFLASH_IMO_TMPCO1, 0x0ffff1c5 +.set CYREG_SFLASH_IMO_MAXF2, 0x0ffff1c6 +.set CYREG_SFLASH_IMO_ABS2, 0x0ffff1c7 +.set CYREG_SFLASH_IMO_TMPCO2, 0x0ffff1c8 +.set CYREG_SFLASH_IMO_MAXF3, 0x0ffff1c9 +.set CYREG_SFLASH_IMO_ABS3, 0x0ffff1ca +.set CYREG_SFLASH_IMO_TMPCO3, 0x0ffff1cb +.set CYREG_SFLASH_IMO_ABS4, 0x0ffff1cc +.set CYREG_SFLASH_IMO_TMPCO4, 0x0ffff1cd +.set CYREG_SFLASH_IMO_TRIM0, 0x0ffff1d0 .set CYFLD_SFLASH_OFFSET__OFFSET, 0x00000000 .set CYFLD_SFLASH_OFFSET__SIZE, 0x00000008 -.set CYREG_SFLASH_IMO_TRIM1, 0x0ffff351 -.set CYREG_SFLASH_IMO_TRIM2, 0x0ffff352 -.set CYREG_SFLASH_IMO_TRIM3, 0x0ffff353 -.set CYREG_SFLASH_IMO_TRIM4, 0x0ffff354 -.set CYREG_SFLASH_IMO_TRIM5, 0x0ffff355 -.set CYREG_SFLASH_IMO_TRIM6, 0x0ffff356 -.set CYREG_SFLASH_IMO_TRIM7, 0x0ffff357 -.set CYREG_SFLASH_IMO_TRIM8, 0x0ffff358 -.set CYREG_SFLASH_IMO_TRIM9, 0x0ffff359 -.set CYREG_SFLASH_IMO_TRIM10, 0x0ffff35a -.set CYREG_SFLASH_IMO_TRIM11, 0x0ffff35b -.set CYREG_SFLASH_IMO_TRIM12, 0x0ffff35c -.set CYREG_SFLASH_IMO_TRIM13, 0x0ffff35d -.set CYREG_SFLASH_IMO_TRIM14, 0x0ffff35e -.set CYREG_SFLASH_IMO_TRIM15, 0x0ffff35f -.set CYREG_SFLASH_IMO_TRIM16, 0x0ffff360 -.set CYREG_SFLASH_IMO_TRIM17, 0x0ffff361 -.set CYREG_SFLASH_IMO_TRIM18, 0x0ffff362 -.set CYREG_SFLASH_IMO_TRIM19, 0x0ffff363 -.set CYREG_SFLASH_IMO_TRIM20, 0x0ffff364 -.set CYREG_SFLASH_IMO_TRIM21, 0x0ffff365 -.set CYREG_SFLASH_IMO_TRIM22, 0x0ffff366 -.set CYREG_SFLASH_IMO_TRIM23, 0x0ffff367 -.set CYREG_SFLASH_IMO_TRIM24, 0x0ffff368 -.set CYREG_SFLASH_IMO_TRIM25, 0x0ffff369 -.set CYREG_SFLASH_IMO_TRIM26, 0x0ffff36a -.set CYREG_SFLASH_IMO_TRIM27, 0x0ffff36b -.set CYREG_SFLASH_IMO_TRIM28, 0x0ffff36c -.set CYREG_SFLASH_IMO_TRIM29, 0x0ffff36d -.set CYREG_SFLASH_IMO_TRIM30, 0x0ffff36e -.set CYREG_SFLASH_IMO_TRIM31, 0x0ffff36f -.set CYREG_SFLASH_IMO_TRIM32, 0x0ffff370 -.set CYREG_SFLASH_IMO_TRIM33, 0x0ffff371 -.set CYREG_SFLASH_IMO_TRIM34, 0x0ffff372 -.set CYREG_SFLASH_IMO_TRIM35, 0x0ffff373 -.set CYREG_SFLASH_IMO_TRIM36, 0x0ffff374 -.set CYREG_SFLASH_IMO_TRIM37, 0x0ffff375 -.set CYREG_SFLASH_IMO_TRIM38, 0x0ffff376 -.set CYREG_SFLASH_IMO_TRIM39, 0x0ffff377 -.set CYREG_SFLASH_IMO_TRIM40, 0x0ffff378 -.set CYREG_SFLASH_IMO_TRIM41, 0x0ffff379 -.set CYREG_SFLASH_IMO_TRIM42, 0x0ffff37a -.set CYREG_SFLASH_IMO_TRIM43, 0x0ffff37b -.set CYREG_SFLASH_IMO_TRIM44, 0x0ffff37c -.set CYREG_SFLASH_IMO_TRIM45, 0x0ffff37d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH0, 0x0ffff400 +.set CYREG_SFLASH_IMO_TRIM1, 0x0ffff1d1 +.set CYREG_SFLASH_IMO_TRIM2, 0x0ffff1d2 +.set CYREG_SFLASH_IMO_TRIM3, 0x0ffff1d3 +.set CYREG_SFLASH_IMO_TRIM4, 0x0ffff1d4 +.set CYREG_SFLASH_IMO_TRIM5, 0x0ffff1d5 +.set CYREG_SFLASH_IMO_TRIM6, 0x0ffff1d6 +.set CYREG_SFLASH_IMO_TRIM7, 0x0ffff1d7 +.set CYREG_SFLASH_IMO_TRIM8, 0x0ffff1d8 +.set CYREG_SFLASH_IMO_TRIM9, 0x0ffff1d9 +.set CYREG_SFLASH_IMO_TRIM10, 0x0ffff1da +.set CYREG_SFLASH_IMO_TRIM11, 0x0ffff1db +.set CYREG_SFLASH_IMO_TRIM12, 0x0ffff1dc +.set CYREG_SFLASH_IMO_TRIM13, 0x0ffff1dd +.set CYREG_SFLASH_IMO_TRIM14, 0x0ffff1de +.set CYREG_SFLASH_IMO_TRIM15, 0x0ffff1df +.set CYREG_SFLASH_IMO_TRIM16, 0x0ffff1e0 +.set CYREG_SFLASH_IMO_TRIM17, 0x0ffff1e1 +.set CYREG_SFLASH_IMO_TRIM18, 0x0ffff1e2 +.set CYREG_SFLASH_IMO_TRIM19, 0x0ffff1e3 +.set CYREG_SFLASH_IMO_TRIM20, 0x0ffff1e4 +.set CYREG_SFLASH_IMO_TRIM21, 0x0ffff1e5 +.set CYREG_SFLASH_IMO_TRIM22, 0x0ffff1e6 +.set CYREG_SFLASH_IMO_TRIM23, 0x0ffff1e7 +.set CYREG_SFLASH_IMO_TRIM24, 0x0ffff1e8 +.set CYREG_SFLASH_IMO_TRIM25, 0x0ffff1e9 +.set CYREG_SFLASH_IMO_TRIM26, 0x0ffff1ea +.set CYREG_SFLASH_IMO_TRIM27, 0x0ffff1eb +.set CYREG_SFLASH_IMO_TRIM28, 0x0ffff1ec +.set CYREG_SFLASH_IMO_TRIM29, 0x0ffff1ed +.set CYREG_SFLASH_IMO_TRIM30, 0x0ffff1ee +.set CYREG_SFLASH_IMO_TRIM31, 0x0ffff1ef +.set CYREG_SFLASH_IMO_TRIM32, 0x0ffff1f0 +.set CYREG_SFLASH_IMO_TRIM33, 0x0ffff1f1 +.set CYREG_SFLASH_IMO_TRIM34, 0x0ffff1f2 +.set CYREG_SFLASH_IMO_TRIM35, 0x0ffff1f3 +.set CYREG_SFLASH_IMO_TRIM36, 0x0ffff1f4 +.set CYREG_SFLASH_IMO_TRIM37, 0x0ffff1f5 +.set CYREG_SFLASH_IMO_TRIM38, 0x0ffff1f6 +.set CYREG_SFLASH_IMO_TRIM39, 0x0ffff1f7 +.set CYREG_SFLASH_IMO_TRIM40, 0x0ffff1f8 +.set CYREG_SFLASH_IMO_TRIM41, 0x0ffff1f9 +.set CYREG_SFLASH_IMO_TRIM42, 0x0ffff1fa +.set CYREG_SFLASH_IMO_TRIM43, 0x0ffff1fb +.set CYREG_SFLASH_IMO_TRIM44, 0x0ffff1fc +.set CYREG_SFLASH_IMO_TRIM45, 0x0ffff1fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH0, 0x0ffff200 .set CYFLD_SFLASH_BYTE_MEM__OFFSET, 0x00000000 .set CYFLD_SFLASH_BYTE_MEM__SIZE, 0x00000008 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1, 0x0ffff401 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH2, 0x0ffff402 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH3, 0x0ffff403 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH4, 0x0ffff404 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH5, 0x0ffff405 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH6, 0x0ffff406 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH7, 0x0ffff407 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH8, 0x0ffff408 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH9, 0x0ffff409 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH10, 0x0ffff40a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH11, 0x0ffff40b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH12, 0x0ffff40c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH13, 0x0ffff40d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH14, 0x0ffff40e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH15, 0x0ffff40f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH16, 0x0ffff410 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH17, 0x0ffff411 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH18, 0x0ffff412 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH19, 0x0ffff413 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH20, 0x0ffff414 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH21, 0x0ffff415 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH22, 0x0ffff416 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH23, 0x0ffff417 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH24, 0x0ffff418 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH25, 0x0ffff419 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH26, 0x0ffff41a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH27, 0x0ffff41b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH28, 0x0ffff41c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH29, 0x0ffff41d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH30, 0x0ffff41e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH31, 0x0ffff41f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH32, 0x0ffff420 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH33, 0x0ffff421 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH34, 0x0ffff422 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH35, 0x0ffff423 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH36, 0x0ffff424 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH37, 0x0ffff425 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH38, 0x0ffff426 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH39, 0x0ffff427 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH40, 0x0ffff428 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH41, 0x0ffff429 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH42, 0x0ffff42a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH43, 0x0ffff42b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH44, 0x0ffff42c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH45, 0x0ffff42d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH46, 0x0ffff42e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH47, 0x0ffff42f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH48, 0x0ffff430 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH49, 0x0ffff431 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH50, 0x0ffff432 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH51, 0x0ffff433 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH52, 0x0ffff434 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH53, 0x0ffff435 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH54, 0x0ffff436 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH55, 0x0ffff437 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH56, 0x0ffff438 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH57, 0x0ffff439 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH58, 0x0ffff43a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH59, 0x0ffff43b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH60, 0x0ffff43c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH61, 0x0ffff43d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH62, 0x0ffff43e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH63, 0x0ffff43f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH64, 0x0ffff440 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH65, 0x0ffff441 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH66, 0x0ffff442 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH67, 0x0ffff443 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH68, 0x0ffff444 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH69, 0x0ffff445 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH70, 0x0ffff446 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH71, 0x0ffff447 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH72, 0x0ffff448 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH73, 0x0ffff449 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH74, 0x0ffff44a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH75, 0x0ffff44b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH76, 0x0ffff44c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH77, 0x0ffff44d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH78, 0x0ffff44e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH79, 0x0ffff44f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH80, 0x0ffff450 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH81, 0x0ffff451 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH82, 0x0ffff452 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH83, 0x0ffff453 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH84, 0x0ffff454 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH85, 0x0ffff455 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH86, 0x0ffff456 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH87, 0x0ffff457 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH88, 0x0ffff458 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH89, 0x0ffff459 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH90, 0x0ffff45a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH91, 0x0ffff45b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH92, 0x0ffff45c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH93, 0x0ffff45d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH94, 0x0ffff45e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH95, 0x0ffff45f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH96, 0x0ffff460 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH97, 0x0ffff461 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH98, 0x0ffff462 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH99, 0x0ffff463 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH100, 0x0ffff464 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH101, 0x0ffff465 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH102, 0x0ffff466 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH103, 0x0ffff467 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH104, 0x0ffff468 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH105, 0x0ffff469 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH106, 0x0ffff46a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH107, 0x0ffff46b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH108, 0x0ffff46c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH109, 0x0ffff46d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH110, 0x0ffff46e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH111, 0x0ffff46f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH112, 0x0ffff470 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH113, 0x0ffff471 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH114, 0x0ffff472 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH115, 0x0ffff473 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH116, 0x0ffff474 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH117, 0x0ffff475 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH118, 0x0ffff476 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH119, 0x0ffff477 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH120, 0x0ffff478 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH121, 0x0ffff479 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH122, 0x0ffff47a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH123, 0x0ffff47b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH124, 0x0ffff47c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH125, 0x0ffff47d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH126, 0x0ffff47e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH127, 0x0ffff47f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH128, 0x0ffff480 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH129, 0x0ffff481 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH130, 0x0ffff482 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH131, 0x0ffff483 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH132, 0x0ffff484 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH133, 0x0ffff485 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH134, 0x0ffff486 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH135, 0x0ffff487 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH136, 0x0ffff488 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH137, 0x0ffff489 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH138, 0x0ffff48a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH139, 0x0ffff48b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH140, 0x0ffff48c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH141, 0x0ffff48d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH142, 0x0ffff48e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH143, 0x0ffff48f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH144, 0x0ffff490 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH145, 0x0ffff491 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH146, 0x0ffff492 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH147, 0x0ffff493 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH148, 0x0ffff494 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH149, 0x0ffff495 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH150, 0x0ffff496 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH151, 0x0ffff497 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH152, 0x0ffff498 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH153, 0x0ffff499 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH154, 0x0ffff49a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH155, 0x0ffff49b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH156, 0x0ffff49c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH157, 0x0ffff49d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH158, 0x0ffff49e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH159, 0x0ffff49f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH160, 0x0ffff4a0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH161, 0x0ffff4a1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH162, 0x0ffff4a2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH163, 0x0ffff4a3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH164, 0x0ffff4a4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH165, 0x0ffff4a5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH166, 0x0ffff4a6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH167, 0x0ffff4a7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH168, 0x0ffff4a8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH169, 0x0ffff4a9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH170, 0x0ffff4aa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH171, 0x0ffff4ab -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH172, 0x0ffff4ac -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH173, 0x0ffff4ad -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH174, 0x0ffff4ae -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH175, 0x0ffff4af -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH176, 0x0ffff4b0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH177, 0x0ffff4b1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH178, 0x0ffff4b2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH179, 0x0ffff4b3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH180, 0x0ffff4b4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH181, 0x0ffff4b5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH182, 0x0ffff4b6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH183, 0x0ffff4b7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH184, 0x0ffff4b8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH185, 0x0ffff4b9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH186, 0x0ffff4ba -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH187, 0x0ffff4bb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH188, 0x0ffff4bc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH189, 0x0ffff4bd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH190, 0x0ffff4be -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH191, 0x0ffff4bf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH192, 0x0ffff4c0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH193, 0x0ffff4c1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH194, 0x0ffff4c2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH195, 0x0ffff4c3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH196, 0x0ffff4c4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH197, 0x0ffff4c5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH198, 0x0ffff4c6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH199, 0x0ffff4c7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH200, 0x0ffff4c8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH201, 0x0ffff4c9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH202, 0x0ffff4ca -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH203, 0x0ffff4cb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH204, 0x0ffff4cc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH205, 0x0ffff4cd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH206, 0x0ffff4ce -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH207, 0x0ffff4cf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH208, 0x0ffff4d0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH209, 0x0ffff4d1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH210, 0x0ffff4d2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH211, 0x0ffff4d3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH212, 0x0ffff4d4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH213, 0x0ffff4d5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH214, 0x0ffff4d6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH215, 0x0ffff4d7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH216, 0x0ffff4d8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH217, 0x0ffff4d9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH218, 0x0ffff4da -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH219, 0x0ffff4db -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH220, 0x0ffff4dc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH221, 0x0ffff4dd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH222, 0x0ffff4de -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH223, 0x0ffff4df -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH224, 0x0ffff4e0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH225, 0x0ffff4e1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH226, 0x0ffff4e2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH227, 0x0ffff4e3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH228, 0x0ffff4e4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH229, 0x0ffff4e5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH230, 0x0ffff4e6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH231, 0x0ffff4e7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH232, 0x0ffff4e8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH233, 0x0ffff4e9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH234, 0x0ffff4ea -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH235, 0x0ffff4eb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH236, 0x0ffff4ec -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH237, 0x0ffff4ed -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH238, 0x0ffff4ee -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH239, 0x0ffff4ef -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH240, 0x0ffff4f0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH241, 0x0ffff4f1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH242, 0x0ffff4f2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH243, 0x0ffff4f3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH244, 0x0ffff4f4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH245, 0x0ffff4f5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH246, 0x0ffff4f6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH247, 0x0ffff4f7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH248, 0x0ffff4f8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH249, 0x0ffff4f9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH250, 0x0ffff4fa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH251, 0x0ffff4fb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH252, 0x0ffff4fc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH253, 0x0ffff4fd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH254, 0x0ffff4fe -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH255, 0x0ffff4ff -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH256, 0x0ffff500 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH257, 0x0ffff501 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH258, 0x0ffff502 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH259, 0x0ffff503 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH260, 0x0ffff504 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH261, 0x0ffff505 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH262, 0x0ffff506 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH263, 0x0ffff507 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH264, 0x0ffff508 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH265, 0x0ffff509 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH266, 0x0ffff50a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH267, 0x0ffff50b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH268, 0x0ffff50c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH269, 0x0ffff50d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH270, 0x0ffff50e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH271, 0x0ffff50f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH272, 0x0ffff510 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH273, 0x0ffff511 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH274, 0x0ffff512 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH275, 0x0ffff513 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH276, 0x0ffff514 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH277, 0x0ffff515 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH278, 0x0ffff516 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH279, 0x0ffff517 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH280, 0x0ffff518 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH281, 0x0ffff519 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH282, 0x0ffff51a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH283, 0x0ffff51b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH284, 0x0ffff51c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH285, 0x0ffff51d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH286, 0x0ffff51e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH287, 0x0ffff51f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH288, 0x0ffff520 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH289, 0x0ffff521 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH290, 0x0ffff522 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH291, 0x0ffff523 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH292, 0x0ffff524 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH293, 0x0ffff525 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH294, 0x0ffff526 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH295, 0x0ffff527 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH296, 0x0ffff528 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH297, 0x0ffff529 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH298, 0x0ffff52a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH299, 0x0ffff52b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH300, 0x0ffff52c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH301, 0x0ffff52d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH302, 0x0ffff52e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH303, 0x0ffff52f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH304, 0x0ffff530 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH305, 0x0ffff531 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH306, 0x0ffff532 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH307, 0x0ffff533 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH308, 0x0ffff534 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH309, 0x0ffff535 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH310, 0x0ffff536 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH311, 0x0ffff537 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH312, 0x0ffff538 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH313, 0x0ffff539 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH314, 0x0ffff53a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH315, 0x0ffff53b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH316, 0x0ffff53c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH317, 0x0ffff53d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH318, 0x0ffff53e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH319, 0x0ffff53f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH320, 0x0ffff540 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH321, 0x0ffff541 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH322, 0x0ffff542 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH323, 0x0ffff543 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH324, 0x0ffff544 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH325, 0x0ffff545 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH326, 0x0ffff546 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH327, 0x0ffff547 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH328, 0x0ffff548 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH329, 0x0ffff549 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH330, 0x0ffff54a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH331, 0x0ffff54b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH332, 0x0ffff54c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH333, 0x0ffff54d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH334, 0x0ffff54e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH335, 0x0ffff54f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH336, 0x0ffff550 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH337, 0x0ffff551 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH338, 0x0ffff552 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH339, 0x0ffff553 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH340, 0x0ffff554 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH341, 0x0ffff555 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH342, 0x0ffff556 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH343, 0x0ffff557 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH344, 0x0ffff558 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH345, 0x0ffff559 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH346, 0x0ffff55a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH347, 0x0ffff55b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH348, 0x0ffff55c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH349, 0x0ffff55d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH350, 0x0ffff55e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH351, 0x0ffff55f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH352, 0x0ffff560 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH353, 0x0ffff561 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH354, 0x0ffff562 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH355, 0x0ffff563 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH356, 0x0ffff564 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH357, 0x0ffff565 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH358, 0x0ffff566 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH359, 0x0ffff567 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH360, 0x0ffff568 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH361, 0x0ffff569 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH362, 0x0ffff56a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH363, 0x0ffff56b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH364, 0x0ffff56c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH365, 0x0ffff56d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH366, 0x0ffff56e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH367, 0x0ffff56f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH368, 0x0ffff570 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH369, 0x0ffff571 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH370, 0x0ffff572 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH371, 0x0ffff573 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH372, 0x0ffff574 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH373, 0x0ffff575 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH374, 0x0ffff576 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH375, 0x0ffff577 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH376, 0x0ffff578 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH377, 0x0ffff579 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH378, 0x0ffff57a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH379, 0x0ffff57b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH380, 0x0ffff57c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH381, 0x0ffff57d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH382, 0x0ffff57e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH383, 0x0ffff57f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH384, 0x0ffff580 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH385, 0x0ffff581 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH386, 0x0ffff582 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH387, 0x0ffff583 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH388, 0x0ffff584 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH389, 0x0ffff585 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH390, 0x0ffff586 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH391, 0x0ffff587 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH392, 0x0ffff588 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH393, 0x0ffff589 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH394, 0x0ffff58a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH395, 0x0ffff58b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH396, 0x0ffff58c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH397, 0x0ffff58d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH398, 0x0ffff58e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH399, 0x0ffff58f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH400, 0x0ffff590 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH401, 0x0ffff591 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH402, 0x0ffff592 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH403, 0x0ffff593 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH404, 0x0ffff594 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH405, 0x0ffff595 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH406, 0x0ffff596 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH407, 0x0ffff597 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH408, 0x0ffff598 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH409, 0x0ffff599 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH410, 0x0ffff59a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH411, 0x0ffff59b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH412, 0x0ffff59c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH413, 0x0ffff59d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH414, 0x0ffff59e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH415, 0x0ffff59f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH416, 0x0ffff5a0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH417, 0x0ffff5a1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH418, 0x0ffff5a2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH419, 0x0ffff5a3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH420, 0x0ffff5a4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH421, 0x0ffff5a5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH422, 0x0ffff5a6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH423, 0x0ffff5a7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH424, 0x0ffff5a8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH425, 0x0ffff5a9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH426, 0x0ffff5aa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH427, 0x0ffff5ab -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH428, 0x0ffff5ac -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH429, 0x0ffff5ad -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH430, 0x0ffff5ae -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH431, 0x0ffff5af -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH432, 0x0ffff5b0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH433, 0x0ffff5b1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH434, 0x0ffff5b2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH435, 0x0ffff5b3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH436, 0x0ffff5b4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH437, 0x0ffff5b5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH438, 0x0ffff5b6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH439, 0x0ffff5b7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH440, 0x0ffff5b8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH441, 0x0ffff5b9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH442, 0x0ffff5ba -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH443, 0x0ffff5bb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH444, 0x0ffff5bc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH445, 0x0ffff5bd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH446, 0x0ffff5be -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH447, 0x0ffff5bf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH448, 0x0ffff5c0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH449, 0x0ffff5c1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH450, 0x0ffff5c2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH451, 0x0ffff5c3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH452, 0x0ffff5c4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH453, 0x0ffff5c5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH454, 0x0ffff5c6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH455, 0x0ffff5c7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH456, 0x0ffff5c8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH457, 0x0ffff5c9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH458, 0x0ffff5ca -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH459, 0x0ffff5cb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH460, 0x0ffff5cc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH461, 0x0ffff5cd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH462, 0x0ffff5ce -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH463, 0x0ffff5cf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH464, 0x0ffff5d0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH465, 0x0ffff5d1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH466, 0x0ffff5d2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH467, 0x0ffff5d3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH468, 0x0ffff5d4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH469, 0x0ffff5d5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH470, 0x0ffff5d6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH471, 0x0ffff5d7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH472, 0x0ffff5d8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH473, 0x0ffff5d9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH474, 0x0ffff5da -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH475, 0x0ffff5db -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH476, 0x0ffff5dc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH477, 0x0ffff5dd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH478, 0x0ffff5de -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH479, 0x0ffff5df -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH480, 0x0ffff5e0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH481, 0x0ffff5e1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH482, 0x0ffff5e2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH483, 0x0ffff5e3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH484, 0x0ffff5e4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH485, 0x0ffff5e5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH486, 0x0ffff5e6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH487, 0x0ffff5e7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH488, 0x0ffff5e8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH489, 0x0ffff5e9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH490, 0x0ffff5ea -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH491, 0x0ffff5eb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH492, 0x0ffff5ec -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH493, 0x0ffff5ed -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH494, 0x0ffff5ee -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH495, 0x0ffff5ef -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH496, 0x0ffff5f0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH497, 0x0ffff5f1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH498, 0x0ffff5f2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH499, 0x0ffff5f3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH500, 0x0ffff5f4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH501, 0x0ffff5f5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH502, 0x0ffff5f6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH503, 0x0ffff5f7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH504, 0x0ffff5f8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH505, 0x0ffff5f9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH506, 0x0ffff5fa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH507, 0x0ffff5fb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH508, 0x0ffff5fc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH509, 0x0ffff5fd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH510, 0x0ffff5fe -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH511, 0x0ffff5ff -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH512, 0x0ffff600 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH513, 0x0ffff601 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH514, 0x0ffff602 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH515, 0x0ffff603 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH516, 0x0ffff604 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH517, 0x0ffff605 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH518, 0x0ffff606 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH519, 0x0ffff607 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH520, 0x0ffff608 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH521, 0x0ffff609 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH522, 0x0ffff60a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH523, 0x0ffff60b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH524, 0x0ffff60c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH525, 0x0ffff60d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH526, 0x0ffff60e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH527, 0x0ffff60f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH528, 0x0ffff610 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH529, 0x0ffff611 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH530, 0x0ffff612 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH531, 0x0ffff613 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH532, 0x0ffff614 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH533, 0x0ffff615 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH534, 0x0ffff616 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH535, 0x0ffff617 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH536, 0x0ffff618 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH537, 0x0ffff619 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH538, 0x0ffff61a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH539, 0x0ffff61b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH540, 0x0ffff61c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH541, 0x0ffff61d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH542, 0x0ffff61e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH543, 0x0ffff61f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH544, 0x0ffff620 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH545, 0x0ffff621 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH546, 0x0ffff622 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH547, 0x0ffff623 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH548, 0x0ffff624 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH549, 0x0ffff625 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH550, 0x0ffff626 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH551, 0x0ffff627 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH552, 0x0ffff628 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH553, 0x0ffff629 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH554, 0x0ffff62a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH555, 0x0ffff62b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH556, 0x0ffff62c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH557, 0x0ffff62d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH558, 0x0ffff62e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH559, 0x0ffff62f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH560, 0x0ffff630 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH561, 0x0ffff631 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH562, 0x0ffff632 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH563, 0x0ffff633 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH564, 0x0ffff634 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH565, 0x0ffff635 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH566, 0x0ffff636 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH567, 0x0ffff637 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH568, 0x0ffff638 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH569, 0x0ffff639 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH570, 0x0ffff63a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH571, 0x0ffff63b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH572, 0x0ffff63c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH573, 0x0ffff63d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH574, 0x0ffff63e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH575, 0x0ffff63f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH576, 0x0ffff640 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH577, 0x0ffff641 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH578, 0x0ffff642 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH579, 0x0ffff643 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH580, 0x0ffff644 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH581, 0x0ffff645 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH582, 0x0ffff646 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH583, 0x0ffff647 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH584, 0x0ffff648 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH585, 0x0ffff649 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH586, 0x0ffff64a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH587, 0x0ffff64b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH588, 0x0ffff64c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH589, 0x0ffff64d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH590, 0x0ffff64e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH591, 0x0ffff64f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH592, 0x0ffff650 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH593, 0x0ffff651 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH594, 0x0ffff652 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH595, 0x0ffff653 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH596, 0x0ffff654 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH597, 0x0ffff655 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH598, 0x0ffff656 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH599, 0x0ffff657 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH600, 0x0ffff658 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH601, 0x0ffff659 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH602, 0x0ffff65a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH603, 0x0ffff65b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH604, 0x0ffff65c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH605, 0x0ffff65d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH606, 0x0ffff65e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH607, 0x0ffff65f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH608, 0x0ffff660 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH609, 0x0ffff661 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH610, 0x0ffff662 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH611, 0x0ffff663 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH612, 0x0ffff664 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH613, 0x0ffff665 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH614, 0x0ffff666 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH615, 0x0ffff667 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH616, 0x0ffff668 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH617, 0x0ffff669 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH618, 0x0ffff66a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH619, 0x0ffff66b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH620, 0x0ffff66c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH621, 0x0ffff66d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH622, 0x0ffff66e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH623, 0x0ffff66f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH624, 0x0ffff670 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH625, 0x0ffff671 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH626, 0x0ffff672 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH627, 0x0ffff673 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH628, 0x0ffff674 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH629, 0x0ffff675 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH630, 0x0ffff676 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH631, 0x0ffff677 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH632, 0x0ffff678 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH633, 0x0ffff679 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH634, 0x0ffff67a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH635, 0x0ffff67b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH636, 0x0ffff67c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH637, 0x0ffff67d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH638, 0x0ffff67e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH639, 0x0ffff67f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH640, 0x0ffff680 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH641, 0x0ffff681 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH642, 0x0ffff682 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH643, 0x0ffff683 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH644, 0x0ffff684 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH645, 0x0ffff685 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH646, 0x0ffff686 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH647, 0x0ffff687 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH648, 0x0ffff688 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH649, 0x0ffff689 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH650, 0x0ffff68a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH651, 0x0ffff68b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH652, 0x0ffff68c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH653, 0x0ffff68d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH654, 0x0ffff68e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH655, 0x0ffff68f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH656, 0x0ffff690 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH657, 0x0ffff691 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH658, 0x0ffff692 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH659, 0x0ffff693 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH660, 0x0ffff694 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH661, 0x0ffff695 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH662, 0x0ffff696 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH663, 0x0ffff697 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH664, 0x0ffff698 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH665, 0x0ffff699 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH666, 0x0ffff69a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH667, 0x0ffff69b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH668, 0x0ffff69c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH669, 0x0ffff69d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH670, 0x0ffff69e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH671, 0x0ffff69f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH672, 0x0ffff6a0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH673, 0x0ffff6a1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH674, 0x0ffff6a2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH675, 0x0ffff6a3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH676, 0x0ffff6a4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH677, 0x0ffff6a5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH678, 0x0ffff6a6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH679, 0x0ffff6a7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH680, 0x0ffff6a8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH681, 0x0ffff6a9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH682, 0x0ffff6aa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH683, 0x0ffff6ab -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH684, 0x0ffff6ac -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH685, 0x0ffff6ad -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH686, 0x0ffff6ae -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH687, 0x0ffff6af -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH688, 0x0ffff6b0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH689, 0x0ffff6b1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH690, 0x0ffff6b2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH691, 0x0ffff6b3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH692, 0x0ffff6b4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH693, 0x0ffff6b5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH694, 0x0ffff6b6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH695, 0x0ffff6b7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH696, 0x0ffff6b8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH697, 0x0ffff6b9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH698, 0x0ffff6ba -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH699, 0x0ffff6bb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH700, 0x0ffff6bc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH701, 0x0ffff6bd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH702, 0x0ffff6be -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH703, 0x0ffff6bf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH704, 0x0ffff6c0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH705, 0x0ffff6c1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH706, 0x0ffff6c2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH707, 0x0ffff6c3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH708, 0x0ffff6c4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH709, 0x0ffff6c5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH710, 0x0ffff6c6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH711, 0x0ffff6c7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH712, 0x0ffff6c8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH713, 0x0ffff6c9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH714, 0x0ffff6ca -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH715, 0x0ffff6cb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH716, 0x0ffff6cc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH717, 0x0ffff6cd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH718, 0x0ffff6ce -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH719, 0x0ffff6cf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH720, 0x0ffff6d0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH721, 0x0ffff6d1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH722, 0x0ffff6d2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH723, 0x0ffff6d3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH724, 0x0ffff6d4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH725, 0x0ffff6d5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH726, 0x0ffff6d6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH727, 0x0ffff6d7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH728, 0x0ffff6d8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH729, 0x0ffff6d9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH730, 0x0ffff6da -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH731, 0x0ffff6db -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH732, 0x0ffff6dc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH733, 0x0ffff6dd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH734, 0x0ffff6de -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH735, 0x0ffff6df -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH736, 0x0ffff6e0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH737, 0x0ffff6e1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH738, 0x0ffff6e2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH739, 0x0ffff6e3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH740, 0x0ffff6e4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH741, 0x0ffff6e5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH742, 0x0ffff6e6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH743, 0x0ffff6e7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH744, 0x0ffff6e8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH745, 0x0ffff6e9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH746, 0x0ffff6ea -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH747, 0x0ffff6eb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH748, 0x0ffff6ec -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH749, 0x0ffff6ed -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH750, 0x0ffff6ee -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH751, 0x0ffff6ef -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH752, 0x0ffff6f0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH753, 0x0ffff6f1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH754, 0x0ffff6f2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH755, 0x0ffff6f3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH756, 0x0ffff6f4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH757, 0x0ffff6f5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH758, 0x0ffff6f6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH759, 0x0ffff6f7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH760, 0x0ffff6f8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH761, 0x0ffff6f9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH762, 0x0ffff6fa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH763, 0x0ffff6fb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH764, 0x0ffff6fc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH765, 0x0ffff6fd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH766, 0x0ffff6fe -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH767, 0x0ffff6ff -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH768, 0x0ffff700 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH769, 0x0ffff701 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH770, 0x0ffff702 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH771, 0x0ffff703 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH772, 0x0ffff704 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH773, 0x0ffff705 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH774, 0x0ffff706 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH775, 0x0ffff707 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH776, 0x0ffff708 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH777, 0x0ffff709 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH778, 0x0ffff70a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH779, 0x0ffff70b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH780, 0x0ffff70c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH781, 0x0ffff70d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH782, 0x0ffff70e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH783, 0x0ffff70f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH784, 0x0ffff710 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH785, 0x0ffff711 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH786, 0x0ffff712 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH787, 0x0ffff713 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH788, 0x0ffff714 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH789, 0x0ffff715 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH790, 0x0ffff716 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH791, 0x0ffff717 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH792, 0x0ffff718 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH793, 0x0ffff719 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH794, 0x0ffff71a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH795, 0x0ffff71b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH796, 0x0ffff71c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH797, 0x0ffff71d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH798, 0x0ffff71e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH799, 0x0ffff71f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH800, 0x0ffff720 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH801, 0x0ffff721 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH802, 0x0ffff722 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH803, 0x0ffff723 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH804, 0x0ffff724 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH805, 0x0ffff725 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH806, 0x0ffff726 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH807, 0x0ffff727 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH808, 0x0ffff728 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH809, 0x0ffff729 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH810, 0x0ffff72a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH811, 0x0ffff72b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH812, 0x0ffff72c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH813, 0x0ffff72d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH814, 0x0ffff72e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH815, 0x0ffff72f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH816, 0x0ffff730 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH817, 0x0ffff731 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH818, 0x0ffff732 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH819, 0x0ffff733 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH820, 0x0ffff734 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH821, 0x0ffff735 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH822, 0x0ffff736 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH823, 0x0ffff737 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH824, 0x0ffff738 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH825, 0x0ffff739 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH826, 0x0ffff73a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH827, 0x0ffff73b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH828, 0x0ffff73c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH829, 0x0ffff73d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH830, 0x0ffff73e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH831, 0x0ffff73f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH832, 0x0ffff740 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH833, 0x0ffff741 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH834, 0x0ffff742 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH835, 0x0ffff743 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH836, 0x0ffff744 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH837, 0x0ffff745 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH838, 0x0ffff746 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH839, 0x0ffff747 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH840, 0x0ffff748 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH841, 0x0ffff749 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH842, 0x0ffff74a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH843, 0x0ffff74b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH844, 0x0ffff74c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH845, 0x0ffff74d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH846, 0x0ffff74e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH847, 0x0ffff74f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH848, 0x0ffff750 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH849, 0x0ffff751 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH850, 0x0ffff752 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH851, 0x0ffff753 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH852, 0x0ffff754 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH853, 0x0ffff755 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH854, 0x0ffff756 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH855, 0x0ffff757 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH856, 0x0ffff758 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH857, 0x0ffff759 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH858, 0x0ffff75a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH859, 0x0ffff75b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH860, 0x0ffff75c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH861, 0x0ffff75d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH862, 0x0ffff75e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH863, 0x0ffff75f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH864, 0x0ffff760 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH865, 0x0ffff761 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH866, 0x0ffff762 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH867, 0x0ffff763 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH868, 0x0ffff764 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH869, 0x0ffff765 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH870, 0x0ffff766 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH871, 0x0ffff767 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH872, 0x0ffff768 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH873, 0x0ffff769 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH874, 0x0ffff76a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH875, 0x0ffff76b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH876, 0x0ffff76c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH877, 0x0ffff76d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH878, 0x0ffff76e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH879, 0x0ffff76f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH880, 0x0ffff770 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH881, 0x0ffff771 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH882, 0x0ffff772 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH883, 0x0ffff773 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH884, 0x0ffff774 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH885, 0x0ffff775 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH886, 0x0ffff776 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH887, 0x0ffff777 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH888, 0x0ffff778 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH889, 0x0ffff779 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH890, 0x0ffff77a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH891, 0x0ffff77b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH892, 0x0ffff77c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH893, 0x0ffff77d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH894, 0x0ffff77e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH895, 0x0ffff77f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH896, 0x0ffff780 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH897, 0x0ffff781 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH898, 0x0ffff782 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH899, 0x0ffff783 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH900, 0x0ffff784 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH901, 0x0ffff785 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH902, 0x0ffff786 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH903, 0x0ffff787 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH904, 0x0ffff788 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH905, 0x0ffff789 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH906, 0x0ffff78a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH907, 0x0ffff78b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH908, 0x0ffff78c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH909, 0x0ffff78d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH910, 0x0ffff78e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH911, 0x0ffff78f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH912, 0x0ffff790 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH913, 0x0ffff791 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH914, 0x0ffff792 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH915, 0x0ffff793 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH916, 0x0ffff794 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH917, 0x0ffff795 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH918, 0x0ffff796 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH919, 0x0ffff797 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH920, 0x0ffff798 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH921, 0x0ffff799 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH922, 0x0ffff79a -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH923, 0x0ffff79b -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH924, 0x0ffff79c -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH925, 0x0ffff79d -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH926, 0x0ffff79e -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH927, 0x0ffff79f -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH928, 0x0ffff7a0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH929, 0x0ffff7a1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH930, 0x0ffff7a2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH931, 0x0ffff7a3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH932, 0x0ffff7a4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH933, 0x0ffff7a5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH934, 0x0ffff7a6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH935, 0x0ffff7a7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH936, 0x0ffff7a8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH937, 0x0ffff7a9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH938, 0x0ffff7aa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH939, 0x0ffff7ab -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH940, 0x0ffff7ac -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH941, 0x0ffff7ad -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH942, 0x0ffff7ae -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH943, 0x0ffff7af -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH944, 0x0ffff7b0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH945, 0x0ffff7b1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH946, 0x0ffff7b2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH947, 0x0ffff7b3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH948, 0x0ffff7b4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH949, 0x0ffff7b5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH950, 0x0ffff7b6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH951, 0x0ffff7b7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH952, 0x0ffff7b8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH953, 0x0ffff7b9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH954, 0x0ffff7ba -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH955, 0x0ffff7bb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH956, 0x0ffff7bc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH957, 0x0ffff7bd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH958, 0x0ffff7be -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH959, 0x0ffff7bf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH960, 0x0ffff7c0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH961, 0x0ffff7c1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH962, 0x0ffff7c2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH963, 0x0ffff7c3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH964, 0x0ffff7c4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH965, 0x0ffff7c5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH966, 0x0ffff7c6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH967, 0x0ffff7c7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH968, 0x0ffff7c8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH969, 0x0ffff7c9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH970, 0x0ffff7ca -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH971, 0x0ffff7cb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH972, 0x0ffff7cc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH973, 0x0ffff7cd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH974, 0x0ffff7ce -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH975, 0x0ffff7cf -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH976, 0x0ffff7d0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH977, 0x0ffff7d1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH978, 0x0ffff7d2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH979, 0x0ffff7d3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH980, 0x0ffff7d4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH981, 0x0ffff7d5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH982, 0x0ffff7d6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH983, 0x0ffff7d7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH984, 0x0ffff7d8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH985, 0x0ffff7d9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH986, 0x0ffff7da -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH987, 0x0ffff7db -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH988, 0x0ffff7dc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH989, 0x0ffff7dd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH990, 0x0ffff7de -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH991, 0x0ffff7df -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH992, 0x0ffff7e0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH993, 0x0ffff7e1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH994, 0x0ffff7e2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH995, 0x0ffff7e3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH996, 0x0ffff7e4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH997, 0x0ffff7e5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH998, 0x0ffff7e6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH999, 0x0ffff7e7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1000, 0x0ffff7e8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1001, 0x0ffff7e9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1002, 0x0ffff7ea -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1003, 0x0ffff7eb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1004, 0x0ffff7ec -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1005, 0x0ffff7ed -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1006, 0x0ffff7ee -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1007, 0x0ffff7ef -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1008, 0x0ffff7f0 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1009, 0x0ffff7f1 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1010, 0x0ffff7f2 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1011, 0x0ffff7f3 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1012, 0x0ffff7f4 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1013, 0x0ffff7f5 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1014, 0x0ffff7f6 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1015, 0x0ffff7f7 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1016, 0x0ffff7f8 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1017, 0x0ffff7f9 -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1018, 0x0ffff7fa -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1019, 0x0ffff7fb -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1020, 0x0ffff7fc -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1021, 0x0ffff7fd -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1022, 0x0ffff7fe -.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1023, 0x0ffff7ff -.set CYREG_SFLASH_ALT_PROT_ROW0, 0x0ffff800 -.set CYREG_SFLASH_ALT_PROT_ROW1, 0x0ffff801 -.set CYREG_SFLASH_ALT_PROT_ROW2, 0x0ffff802 -.set CYREG_SFLASH_ALT_PROT_ROW3, 0x0ffff803 -.set CYREG_SFLASH_ALT_PROT_ROW4, 0x0ffff804 -.set CYREG_SFLASH_ALT_PROT_ROW5, 0x0ffff805 -.set CYREG_SFLASH_ALT_PROT_ROW6, 0x0ffff806 -.set CYREG_SFLASH_ALT_PROT_ROW7, 0x0ffff807 -.set CYREG_SFLASH_ALT_PROT_ROW8, 0x0ffff808 -.set CYREG_SFLASH_ALT_PROT_ROW9, 0x0ffff809 -.set CYREG_SFLASH_ALT_PROT_ROW10, 0x0ffff80a -.set CYREG_SFLASH_ALT_PROT_ROW11, 0x0ffff80b -.set CYREG_SFLASH_ALT_PROT_ROW12, 0x0ffff80c -.set CYREG_SFLASH_ALT_PROT_ROW13, 0x0ffff80d -.set CYREG_SFLASH_ALT_PROT_ROW14, 0x0ffff80e -.set CYREG_SFLASH_ALT_PROT_ROW15, 0x0ffff80f -.set CYREG_SFLASH_ALT_PROT_ROW16, 0x0ffff810 -.set CYREG_SFLASH_ALT_PROT_ROW17, 0x0ffff811 -.set CYREG_SFLASH_ALT_PROT_ROW18, 0x0ffff812 -.set CYREG_SFLASH_ALT_PROT_ROW19, 0x0ffff813 -.set CYREG_SFLASH_ALT_PROT_ROW20, 0x0ffff814 -.set CYREG_SFLASH_ALT_PROT_ROW21, 0x0ffff815 -.set CYREG_SFLASH_ALT_PROT_ROW22, 0x0ffff816 -.set CYREG_SFLASH_ALT_PROT_ROW23, 0x0ffff817 -.set CYREG_SFLASH_ALT_PROT_ROW24, 0x0ffff818 -.set CYREG_SFLASH_ALT_PROT_ROW25, 0x0ffff819 -.set CYREG_SFLASH_ALT_PROT_ROW26, 0x0ffff81a -.set CYREG_SFLASH_ALT_PROT_ROW27, 0x0ffff81b -.set CYREG_SFLASH_ALT_PROT_ROW28, 0x0ffff81c -.set CYREG_SFLASH_ALT_PROT_ROW29, 0x0ffff81d -.set CYREG_SFLASH_ALT_PROT_ROW30, 0x0ffff81e -.set CYREG_SFLASH_ALT_PROT_ROW31, 0x0ffff81f -.set CYREG_SFLASH_ALT_PROT_ROW32, 0x0ffff820 -.set CYREG_SFLASH_ALT_PROT_ROW33, 0x0ffff821 -.set CYREG_SFLASH_ALT_PROT_ROW34, 0x0ffff822 -.set CYREG_SFLASH_ALT_PROT_ROW35, 0x0ffff823 -.set CYREG_SFLASH_ALT_PROT_ROW36, 0x0ffff824 -.set CYREG_SFLASH_ALT_PROT_ROW37, 0x0ffff825 -.set CYREG_SFLASH_ALT_PROT_ROW38, 0x0ffff826 -.set CYREG_SFLASH_ALT_PROT_ROW39, 0x0ffff827 -.set CYREG_SFLASH_ALT_PROT_ROW40, 0x0ffff828 -.set CYREG_SFLASH_ALT_PROT_ROW41, 0x0ffff829 -.set CYREG_SFLASH_ALT_PROT_ROW42, 0x0ffff82a -.set CYREG_SFLASH_ALT_PROT_ROW43, 0x0ffff82b -.set CYREG_SFLASH_ALT_PROT_ROW44, 0x0ffff82c -.set CYREG_SFLASH_ALT_PROT_ROW45, 0x0ffff82d -.set CYREG_SFLASH_ALT_PROT_ROW46, 0x0ffff82e -.set CYREG_SFLASH_ALT_PROT_ROW47, 0x0ffff82f -.set CYREG_SFLASH_ALT_PROT_ROW48, 0x0ffff830 -.set CYREG_SFLASH_ALT_PROT_ROW49, 0x0ffff831 -.set CYREG_SFLASH_ALT_PROT_ROW50, 0x0ffff832 -.set CYREG_SFLASH_ALT_PROT_ROW51, 0x0ffff833 -.set CYREG_SFLASH_ALT_PROT_ROW52, 0x0ffff834 -.set CYREG_SFLASH_ALT_PROT_ROW53, 0x0ffff835 -.set CYREG_SFLASH_ALT_PROT_ROW54, 0x0ffff836 -.set CYREG_SFLASH_ALT_PROT_ROW55, 0x0ffff837 -.set CYREG_SFLASH_ALT_PROT_ROW56, 0x0ffff838 -.set CYREG_SFLASH_ALT_PROT_ROW57, 0x0ffff839 -.set CYREG_SFLASH_ALT_PROT_ROW58, 0x0ffff83a -.set CYREG_SFLASH_ALT_PROT_ROW59, 0x0ffff83b -.set CYREG_SFLASH_ALT_PROT_ROW60, 0x0ffff83c -.set CYREG_SFLASH_ALT_PROT_ROW61, 0x0ffff83d -.set CYREG_SFLASH_ALT_PROT_ROW62, 0x0ffff83e -.set CYREG_SFLASH_ALT_PROT_ROW63, 0x0ffff83f -.set CYREG_SFLASH_ALT_PROT_ROW64, 0x0ffff840 -.set CYREG_SFLASH_ALT_PROT_ROW65, 0x0ffff841 -.set CYREG_SFLASH_ALT_PROT_ROW66, 0x0ffff842 -.set CYREG_SFLASH_ALT_PROT_ROW67, 0x0ffff843 -.set CYREG_SFLASH_ALT_PROT_ROW68, 0x0ffff844 -.set CYREG_SFLASH_ALT_PROT_ROW69, 0x0ffff845 -.set CYREG_SFLASH_ALT_PROT_ROW70, 0x0ffff846 -.set CYREG_SFLASH_ALT_PROT_ROW71, 0x0ffff847 -.set CYREG_SFLASH_ALT_PROT_ROW72, 0x0ffff848 -.set CYREG_SFLASH_ALT_PROT_ROW73, 0x0ffff849 -.set CYREG_SFLASH_ALT_PROT_ROW74, 0x0ffff84a -.set CYREG_SFLASH_ALT_PROT_ROW75, 0x0ffff84b -.set CYREG_SFLASH_ALT_PROT_ROW76, 0x0ffff84c -.set CYREG_SFLASH_ALT_PROT_ROW77, 0x0ffff84d -.set CYREG_SFLASH_ALT_PROT_ROW78, 0x0ffff84e -.set CYREG_SFLASH_ALT_PROT_ROW79, 0x0ffff84f -.set CYREG_SFLASH_ALT_PROT_ROW80, 0x0ffff850 -.set CYREG_SFLASH_ALT_PROT_ROW81, 0x0ffff851 -.set CYREG_SFLASH_ALT_PROT_ROW82, 0x0ffff852 -.set CYREG_SFLASH_ALT_PROT_ROW83, 0x0ffff853 -.set CYREG_SFLASH_ALT_PROT_ROW84, 0x0ffff854 -.set CYREG_SFLASH_ALT_PROT_ROW85, 0x0ffff855 -.set CYREG_SFLASH_ALT_PROT_ROW86, 0x0ffff856 -.set CYREG_SFLASH_ALT_PROT_ROW87, 0x0ffff857 -.set CYREG_SFLASH_ALT_PROT_ROW88, 0x0ffff858 -.set CYREG_SFLASH_ALT_PROT_ROW89, 0x0ffff859 -.set CYREG_SFLASH_ALT_PROT_ROW90, 0x0ffff85a -.set CYREG_SFLASH_ALT_PROT_ROW91, 0x0ffff85b -.set CYREG_SFLASH_ALT_PROT_ROW92, 0x0ffff85c -.set CYREG_SFLASH_ALT_PROT_ROW93, 0x0ffff85d -.set CYREG_SFLASH_ALT_PROT_ROW94, 0x0ffff85e -.set CYREG_SFLASH_ALT_PROT_ROW95, 0x0ffff85f -.set CYREG_SFLASH_ALT_PROT_ROW96, 0x0ffff860 -.set CYREG_SFLASH_ALT_PROT_ROW97, 0x0ffff861 -.set CYREG_SFLASH_ALT_PROT_ROW98, 0x0ffff862 -.set CYREG_SFLASH_ALT_PROT_ROW99, 0x0ffff863 -.set CYREG_SFLASH_ALT_PROT_ROW100, 0x0ffff864 -.set CYREG_SFLASH_ALT_PROT_ROW101, 0x0ffff865 -.set CYREG_SFLASH_ALT_PROT_ROW102, 0x0ffff866 -.set CYREG_SFLASH_ALT_PROT_ROW103, 0x0ffff867 -.set CYREG_SFLASH_ALT_PROT_ROW104, 0x0ffff868 -.set CYREG_SFLASH_ALT_PROT_ROW105, 0x0ffff869 -.set CYREG_SFLASH_ALT_PROT_ROW106, 0x0ffff86a -.set CYREG_SFLASH_ALT_PROT_ROW107, 0x0ffff86b -.set CYREG_SFLASH_ALT_PROT_ROW108, 0x0ffff86c -.set CYREG_SFLASH_ALT_PROT_ROW109, 0x0ffff86d -.set CYREG_SFLASH_ALT_PROT_ROW110, 0x0ffff86e -.set CYREG_SFLASH_ALT_PROT_ROW111, 0x0ffff86f -.set CYREG_SFLASH_ALT_PROT_ROW112, 0x0ffff870 -.set CYREG_SFLASH_ALT_PROT_ROW113, 0x0ffff871 -.set CYREG_SFLASH_ALT_PROT_ROW114, 0x0ffff872 -.set CYREG_SFLASH_ALT_PROT_ROW115, 0x0ffff873 -.set CYREG_SFLASH_ALT_PROT_ROW116, 0x0ffff874 -.set CYREG_SFLASH_ALT_PROT_ROW117, 0x0ffff875 -.set CYREG_SFLASH_ALT_PROT_ROW118, 0x0ffff876 -.set CYREG_SFLASH_ALT_PROT_ROW119, 0x0ffff877 -.set CYREG_SFLASH_ALT_PROT_ROW120, 0x0ffff878 -.set CYREG_SFLASH_ALT_PROT_ROW121, 0x0ffff879 -.set CYREG_SFLASH_ALT_PROT_ROW122, 0x0ffff87a -.set CYREG_SFLASH_ALT_PROT_ROW123, 0x0ffff87b -.set CYREG_SFLASH_ALT_PROT_ROW124, 0x0ffff87c -.set CYREG_SFLASH_ALT_PROT_ROW125, 0x0ffff87d -.set CYREG_SFLASH_ALT_PROT_ROW126, 0x0ffff87e -.set CYREG_SFLASH_ALT_PROT_ROW127, 0x0ffff87f -.set CYREG_SFLASH_ALT_PROT_ROW128, 0x0ffff880 -.set CYREG_SFLASH_ALT_PROT_ROW129, 0x0ffff881 -.set CYREG_SFLASH_ALT_PROT_ROW130, 0x0ffff882 -.set CYREG_SFLASH_ALT_PROT_ROW131, 0x0ffff883 -.set CYREG_SFLASH_ALT_PROT_ROW132, 0x0ffff884 -.set CYREG_SFLASH_ALT_PROT_ROW133, 0x0ffff885 -.set CYREG_SFLASH_ALT_PROT_ROW134, 0x0ffff886 -.set CYREG_SFLASH_ALT_PROT_ROW135, 0x0ffff887 -.set CYREG_SFLASH_ALT_PROT_ROW136, 0x0ffff888 -.set CYREG_SFLASH_ALT_PROT_ROW137, 0x0ffff889 -.set CYREG_SFLASH_ALT_PROT_ROW138, 0x0ffff88a -.set CYREG_SFLASH_ALT_PROT_ROW139, 0x0ffff88b -.set CYREG_SFLASH_ALT_PROT_ROW140, 0x0ffff88c -.set CYREG_SFLASH_ALT_PROT_ROW141, 0x0ffff88d -.set CYREG_SFLASH_ALT_PROT_ROW142, 0x0ffff88e -.set CYREG_SFLASH_ALT_PROT_ROW143, 0x0ffff88f -.set CYREG_SFLASH_ALT_PROT_ROW144, 0x0ffff890 -.set CYREG_SFLASH_ALT_PROT_ROW145, 0x0ffff891 -.set CYREG_SFLASH_ALT_PROT_ROW146, 0x0ffff892 -.set CYREG_SFLASH_ALT_PROT_ROW147, 0x0ffff893 -.set CYREG_SFLASH_ALT_PROT_ROW148, 0x0ffff894 -.set CYREG_SFLASH_ALT_PROT_ROW149, 0x0ffff895 -.set CYREG_SFLASH_ALT_PROT_ROW150, 0x0ffff896 -.set CYREG_SFLASH_ALT_PROT_ROW151, 0x0ffff897 -.set CYREG_SFLASH_ALT_PROT_ROW152, 0x0ffff898 -.set CYREG_SFLASH_ALT_PROT_ROW153, 0x0ffff899 -.set CYREG_SFLASH_ALT_PROT_ROW154, 0x0ffff89a -.set CYREG_SFLASH_ALT_PROT_ROW155, 0x0ffff89b -.set CYREG_SFLASH_ALT_PROT_ROW156, 0x0ffff89c -.set CYREG_SFLASH_ALT_PROT_ROW157, 0x0ffff89d -.set CYREG_SFLASH_ALT_PROT_ROW158, 0x0ffff89e -.set CYREG_SFLASH_ALT_PROT_ROW159, 0x0ffff89f -.set CYREG_SFLASH_ALT_PROT_ROW160, 0x0ffff8a0 -.set CYREG_SFLASH_ALT_PROT_ROW161, 0x0ffff8a1 -.set CYREG_SFLASH_ALT_PROT_ROW162, 0x0ffff8a2 -.set CYREG_SFLASH_ALT_PROT_ROW163, 0x0ffff8a3 -.set CYREG_SFLASH_ALT_PROT_ROW164, 0x0ffff8a4 -.set CYREG_SFLASH_ALT_PROT_ROW165, 0x0ffff8a5 -.set CYREG_SFLASH_ALT_PROT_ROW166, 0x0ffff8a6 -.set CYREG_SFLASH_ALT_PROT_ROW167, 0x0ffff8a7 -.set CYREG_SFLASH_ALT_PROT_ROW168, 0x0ffff8a8 -.set CYREG_SFLASH_ALT_PROT_ROW169, 0x0ffff8a9 -.set CYREG_SFLASH_ALT_PROT_ROW170, 0x0ffff8aa -.set CYREG_SFLASH_ALT_PROT_ROW171, 0x0ffff8ab -.set CYREG_SFLASH_ALT_PROT_ROW172, 0x0ffff8ac -.set CYREG_SFLASH_ALT_PROT_ROW173, 0x0ffff8ad -.set CYREG_SFLASH_ALT_PROT_ROW174, 0x0ffff8ae -.set CYREG_SFLASH_ALT_PROT_ROW175, 0x0ffff8af -.set CYREG_SFLASH_ALT_PROT_ROW176, 0x0ffff8b0 -.set CYREG_SFLASH_ALT_PROT_ROW177, 0x0ffff8b1 -.set CYREG_SFLASH_ALT_PROT_ROW178, 0x0ffff8b2 -.set CYREG_SFLASH_ALT_PROT_ROW179, 0x0ffff8b3 -.set CYREG_SFLASH_ALT_PROT_ROW180, 0x0ffff8b4 -.set CYREG_SFLASH_ALT_PROT_ROW181, 0x0ffff8b5 -.set CYREG_SFLASH_ALT_PROT_ROW182, 0x0ffff8b6 -.set CYREG_SFLASH_ALT_PROT_ROW183, 0x0ffff8b7 -.set CYREG_SFLASH_ALT_PROT_ROW184, 0x0ffff8b8 -.set CYREG_SFLASH_ALT_PROT_ROW185, 0x0ffff8b9 -.set CYREG_SFLASH_ALT_PROT_ROW186, 0x0ffff8ba -.set CYREG_SFLASH_ALT_PROT_ROW187, 0x0ffff8bb -.set CYREG_SFLASH_ALT_PROT_ROW188, 0x0ffff8bc -.set CYREG_SFLASH_ALT_PROT_ROW189, 0x0ffff8bd -.set CYREG_SFLASH_ALT_PROT_ROW190, 0x0ffff8be -.set CYREG_SFLASH_ALT_PROT_ROW191, 0x0ffff8bf -.set CYREG_SFLASH_ALT_PROT_ROW192, 0x0ffff8c0 -.set CYREG_SFLASH_ALT_PROT_ROW193, 0x0ffff8c1 -.set CYREG_SFLASH_ALT_PROT_ROW194, 0x0ffff8c2 -.set CYREG_SFLASH_ALT_PROT_ROW195, 0x0ffff8c3 -.set CYREG_SFLASH_ALT_PROT_ROW196, 0x0ffff8c4 -.set CYREG_SFLASH_ALT_PROT_ROW197, 0x0ffff8c5 -.set CYREG_SFLASH_ALT_PROT_ROW198, 0x0ffff8c6 -.set CYREG_SFLASH_ALT_PROT_ROW199, 0x0ffff8c7 -.set CYREG_SFLASH_ALT_PROT_ROW200, 0x0ffff8c8 -.set CYREG_SFLASH_ALT_PROT_ROW201, 0x0ffff8c9 -.set CYREG_SFLASH_ALT_PROT_ROW202, 0x0ffff8ca -.set CYREG_SFLASH_ALT_PROT_ROW203, 0x0ffff8cb -.set CYREG_SFLASH_ALT_PROT_ROW204, 0x0ffff8cc -.set CYREG_SFLASH_ALT_PROT_ROW205, 0x0ffff8cd -.set CYREG_SFLASH_ALT_PROT_ROW206, 0x0ffff8ce -.set CYREG_SFLASH_ALT_PROT_ROW207, 0x0ffff8cf -.set CYREG_SFLASH_ALT_PROT_ROW208, 0x0ffff8d0 -.set CYREG_SFLASH_ALT_PROT_ROW209, 0x0ffff8d1 -.set CYREG_SFLASH_ALT_PROT_ROW210, 0x0ffff8d2 -.set CYREG_SFLASH_ALT_PROT_ROW211, 0x0ffff8d3 -.set CYREG_SFLASH_ALT_PROT_ROW212, 0x0ffff8d4 -.set CYREG_SFLASH_ALT_PROT_ROW213, 0x0ffff8d5 -.set CYREG_SFLASH_ALT_PROT_ROW214, 0x0ffff8d6 -.set CYREG_SFLASH_ALT_PROT_ROW215, 0x0ffff8d7 -.set CYREG_SFLASH_ALT_PROT_ROW216, 0x0ffff8d8 -.set CYREG_SFLASH_ALT_PROT_ROW217, 0x0ffff8d9 -.set CYREG_SFLASH_ALT_PROT_ROW218, 0x0ffff8da -.set CYREG_SFLASH_ALT_PROT_ROW219, 0x0ffff8db -.set CYREG_SFLASH_ALT_PROT_ROW220, 0x0ffff8dc -.set CYREG_SFLASH_ALT_PROT_ROW221, 0x0ffff8dd -.set CYREG_SFLASH_ALT_PROT_ROW222, 0x0ffff8de -.set CYREG_SFLASH_ALT_PROT_ROW223, 0x0ffff8df -.set CYREG_SFLASH_ALT_PROT_ROW224, 0x0ffff8e0 -.set CYREG_SFLASH_ALT_PROT_ROW225, 0x0ffff8e1 -.set CYREG_SFLASH_ALT_PROT_ROW226, 0x0ffff8e2 -.set CYREG_SFLASH_ALT_PROT_ROW227, 0x0ffff8e3 -.set CYREG_SFLASH_ALT_PROT_ROW228, 0x0ffff8e4 -.set CYREG_SFLASH_ALT_PROT_ROW229, 0x0ffff8e5 -.set CYREG_SFLASH_ALT_PROT_ROW230, 0x0ffff8e6 -.set CYREG_SFLASH_ALT_PROT_ROW231, 0x0ffff8e7 -.set CYREG_SFLASH_ALT_PROT_ROW232, 0x0ffff8e8 -.set CYREG_SFLASH_ALT_PROT_ROW233, 0x0ffff8e9 -.set CYREG_SFLASH_ALT_PROT_ROW234, 0x0ffff8ea -.set CYREG_SFLASH_ALT_PROT_ROW235, 0x0ffff8eb -.set CYREG_SFLASH_ALT_PROT_ROW236, 0x0ffff8ec -.set CYREG_SFLASH_ALT_PROT_ROW237, 0x0ffff8ed -.set CYREG_SFLASH_ALT_PROT_ROW238, 0x0ffff8ee -.set CYREG_SFLASH_ALT_PROT_ROW239, 0x0ffff8ef -.set CYREG_SFLASH_ALT_PROT_ROW240, 0x0ffff8f0 -.set CYREG_SFLASH_ALT_PROT_ROW241, 0x0ffff8f1 -.set CYREG_SFLASH_ALT_PROT_ROW242, 0x0ffff8f2 -.set CYREG_SFLASH_ALT_PROT_ROW243, 0x0ffff8f3 -.set CYREG_SFLASH_ALT_PROT_ROW244, 0x0ffff8f4 -.set CYREG_SFLASH_ALT_PROT_ROW245, 0x0ffff8f5 -.set CYREG_SFLASH_ALT_PROT_ROW246, 0x0ffff8f6 -.set CYREG_SFLASH_ALT_PROT_ROW247, 0x0ffff8f7 -.set CYREG_SFLASH_ALT_PROT_ROW248, 0x0ffff8f8 -.set CYREG_SFLASH_ALT_PROT_ROW249, 0x0ffff8f9 -.set CYREG_SFLASH_ALT_PROT_ROW250, 0x0ffff8fa -.set CYREG_SFLASH_ALT_PROT_ROW251, 0x0ffff8fb -.set CYREG_SFLASH_ALT_PROT_ROW252, 0x0ffff8fc -.set CYREG_SFLASH_ALT_PROT_ROW253, 0x0ffff8fd -.set CYREG_SFLASH_ALT_PROT_ROW254, 0x0ffff8fe -.set CYREG_SFLASH_ALT_PROT_ROW255, 0x0ffff8ff -.set CYREG_SFLASH_ALT_PP, 0x0ffffb20 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH1, 0x0ffff201 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH2, 0x0ffff202 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH3, 0x0ffff203 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH4, 0x0ffff204 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH5, 0x0ffff205 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH6, 0x0ffff206 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH7, 0x0ffff207 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH8, 0x0ffff208 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH9, 0x0ffff209 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH10, 0x0ffff20a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH11, 0x0ffff20b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH12, 0x0ffff20c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH13, 0x0ffff20d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH14, 0x0ffff20e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH15, 0x0ffff20f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH16, 0x0ffff210 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH17, 0x0ffff211 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH18, 0x0ffff212 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH19, 0x0ffff213 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH20, 0x0ffff214 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH21, 0x0ffff215 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH22, 0x0ffff216 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH23, 0x0ffff217 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH24, 0x0ffff218 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH25, 0x0ffff219 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH26, 0x0ffff21a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH27, 0x0ffff21b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH28, 0x0ffff21c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH29, 0x0ffff21d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH30, 0x0ffff21e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH31, 0x0ffff21f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH32, 0x0ffff220 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH33, 0x0ffff221 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH34, 0x0ffff222 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH35, 0x0ffff223 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH36, 0x0ffff224 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH37, 0x0ffff225 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH38, 0x0ffff226 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH39, 0x0ffff227 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH40, 0x0ffff228 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH41, 0x0ffff229 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH42, 0x0ffff22a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH43, 0x0ffff22b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH44, 0x0ffff22c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH45, 0x0ffff22d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH46, 0x0ffff22e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH47, 0x0ffff22f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH48, 0x0ffff230 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH49, 0x0ffff231 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH50, 0x0ffff232 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH51, 0x0ffff233 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH52, 0x0ffff234 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH53, 0x0ffff235 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH54, 0x0ffff236 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH55, 0x0ffff237 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH56, 0x0ffff238 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH57, 0x0ffff239 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH58, 0x0ffff23a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH59, 0x0ffff23b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH60, 0x0ffff23c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH61, 0x0ffff23d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH62, 0x0ffff23e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH63, 0x0ffff23f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH64, 0x0ffff240 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH65, 0x0ffff241 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH66, 0x0ffff242 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH67, 0x0ffff243 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH68, 0x0ffff244 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH69, 0x0ffff245 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH70, 0x0ffff246 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH71, 0x0ffff247 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH72, 0x0ffff248 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH73, 0x0ffff249 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH74, 0x0ffff24a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH75, 0x0ffff24b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH76, 0x0ffff24c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH77, 0x0ffff24d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH78, 0x0ffff24e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH79, 0x0ffff24f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH80, 0x0ffff250 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH81, 0x0ffff251 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH82, 0x0ffff252 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH83, 0x0ffff253 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH84, 0x0ffff254 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH85, 0x0ffff255 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH86, 0x0ffff256 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH87, 0x0ffff257 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH88, 0x0ffff258 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH89, 0x0ffff259 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH90, 0x0ffff25a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH91, 0x0ffff25b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH92, 0x0ffff25c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH93, 0x0ffff25d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH94, 0x0ffff25e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH95, 0x0ffff25f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH96, 0x0ffff260 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH97, 0x0ffff261 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH98, 0x0ffff262 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH99, 0x0ffff263 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH100, 0x0ffff264 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH101, 0x0ffff265 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH102, 0x0ffff266 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH103, 0x0ffff267 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH104, 0x0ffff268 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH105, 0x0ffff269 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH106, 0x0ffff26a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH107, 0x0ffff26b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH108, 0x0ffff26c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH109, 0x0ffff26d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH110, 0x0ffff26e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH111, 0x0ffff26f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH112, 0x0ffff270 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH113, 0x0ffff271 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH114, 0x0ffff272 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH115, 0x0ffff273 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH116, 0x0ffff274 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH117, 0x0ffff275 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH118, 0x0ffff276 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH119, 0x0ffff277 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH120, 0x0ffff278 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH121, 0x0ffff279 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH122, 0x0ffff27a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH123, 0x0ffff27b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH124, 0x0ffff27c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH125, 0x0ffff27d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH126, 0x0ffff27e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH127, 0x0ffff27f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH128, 0x0ffff280 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH129, 0x0ffff281 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH130, 0x0ffff282 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH131, 0x0ffff283 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH132, 0x0ffff284 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH133, 0x0ffff285 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH134, 0x0ffff286 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH135, 0x0ffff287 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH136, 0x0ffff288 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH137, 0x0ffff289 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH138, 0x0ffff28a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH139, 0x0ffff28b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH140, 0x0ffff28c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH141, 0x0ffff28d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH142, 0x0ffff28e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH143, 0x0ffff28f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH144, 0x0ffff290 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH145, 0x0ffff291 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH146, 0x0ffff292 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH147, 0x0ffff293 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH148, 0x0ffff294 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH149, 0x0ffff295 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH150, 0x0ffff296 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH151, 0x0ffff297 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH152, 0x0ffff298 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH153, 0x0ffff299 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH154, 0x0ffff29a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH155, 0x0ffff29b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH156, 0x0ffff29c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH157, 0x0ffff29d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH158, 0x0ffff29e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH159, 0x0ffff29f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH160, 0x0ffff2a0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH161, 0x0ffff2a1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH162, 0x0ffff2a2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH163, 0x0ffff2a3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH164, 0x0ffff2a4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH165, 0x0ffff2a5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH166, 0x0ffff2a6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH167, 0x0ffff2a7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH168, 0x0ffff2a8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH169, 0x0ffff2a9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH170, 0x0ffff2aa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH171, 0x0ffff2ab +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH172, 0x0ffff2ac +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH173, 0x0ffff2ad +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH174, 0x0ffff2ae +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH175, 0x0ffff2af +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH176, 0x0ffff2b0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH177, 0x0ffff2b1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH178, 0x0ffff2b2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH179, 0x0ffff2b3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH180, 0x0ffff2b4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH181, 0x0ffff2b5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH182, 0x0ffff2b6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH183, 0x0ffff2b7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH184, 0x0ffff2b8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH185, 0x0ffff2b9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH186, 0x0ffff2ba +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH187, 0x0ffff2bb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH188, 0x0ffff2bc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH189, 0x0ffff2bd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH190, 0x0ffff2be +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH191, 0x0ffff2bf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH192, 0x0ffff2c0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH193, 0x0ffff2c1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH194, 0x0ffff2c2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH195, 0x0ffff2c3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH196, 0x0ffff2c4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH197, 0x0ffff2c5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH198, 0x0ffff2c6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH199, 0x0ffff2c7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH200, 0x0ffff2c8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH201, 0x0ffff2c9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH202, 0x0ffff2ca +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH203, 0x0ffff2cb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH204, 0x0ffff2cc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH205, 0x0ffff2cd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH206, 0x0ffff2ce +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH207, 0x0ffff2cf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH208, 0x0ffff2d0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH209, 0x0ffff2d1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH210, 0x0ffff2d2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH211, 0x0ffff2d3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH212, 0x0ffff2d4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH213, 0x0ffff2d5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH214, 0x0ffff2d6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH215, 0x0ffff2d7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH216, 0x0ffff2d8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH217, 0x0ffff2d9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH218, 0x0ffff2da +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH219, 0x0ffff2db +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH220, 0x0ffff2dc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH221, 0x0ffff2dd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH222, 0x0ffff2de +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH223, 0x0ffff2df +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH224, 0x0ffff2e0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH225, 0x0ffff2e1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH226, 0x0ffff2e2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH227, 0x0ffff2e3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH228, 0x0ffff2e4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH229, 0x0ffff2e5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH230, 0x0ffff2e6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH231, 0x0ffff2e7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH232, 0x0ffff2e8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH233, 0x0ffff2e9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH234, 0x0ffff2ea +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH235, 0x0ffff2eb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH236, 0x0ffff2ec +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH237, 0x0ffff2ed +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH238, 0x0ffff2ee +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH239, 0x0ffff2ef +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH240, 0x0ffff2f0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH241, 0x0ffff2f1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH242, 0x0ffff2f2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH243, 0x0ffff2f3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH244, 0x0ffff2f4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH245, 0x0ffff2f5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH246, 0x0ffff2f6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH247, 0x0ffff2f7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH248, 0x0ffff2f8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH249, 0x0ffff2f9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH250, 0x0ffff2fa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH251, 0x0ffff2fb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH252, 0x0ffff2fc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH253, 0x0ffff2fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH254, 0x0ffff2fe +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH255, 0x0ffff2ff +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH256, 0x0ffff300 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH257, 0x0ffff301 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH258, 0x0ffff302 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH259, 0x0ffff303 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH260, 0x0ffff304 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH261, 0x0ffff305 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH262, 0x0ffff306 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH263, 0x0ffff307 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH264, 0x0ffff308 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH265, 0x0ffff309 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH266, 0x0ffff30a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH267, 0x0ffff30b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH268, 0x0ffff30c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH269, 0x0ffff30d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH270, 0x0ffff30e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH271, 0x0ffff30f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH272, 0x0ffff310 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH273, 0x0ffff311 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH274, 0x0ffff312 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH275, 0x0ffff313 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH276, 0x0ffff314 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH277, 0x0ffff315 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH278, 0x0ffff316 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH279, 0x0ffff317 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH280, 0x0ffff318 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH281, 0x0ffff319 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH282, 0x0ffff31a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH283, 0x0ffff31b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH284, 0x0ffff31c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH285, 0x0ffff31d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH286, 0x0ffff31e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH287, 0x0ffff31f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH288, 0x0ffff320 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH289, 0x0ffff321 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH290, 0x0ffff322 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH291, 0x0ffff323 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH292, 0x0ffff324 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH293, 0x0ffff325 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH294, 0x0ffff326 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH295, 0x0ffff327 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH296, 0x0ffff328 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH297, 0x0ffff329 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH298, 0x0ffff32a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH299, 0x0ffff32b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH300, 0x0ffff32c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH301, 0x0ffff32d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH302, 0x0ffff32e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH303, 0x0ffff32f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH304, 0x0ffff330 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH305, 0x0ffff331 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH306, 0x0ffff332 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH307, 0x0ffff333 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH308, 0x0ffff334 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH309, 0x0ffff335 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH310, 0x0ffff336 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH311, 0x0ffff337 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH312, 0x0ffff338 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH313, 0x0ffff339 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH314, 0x0ffff33a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH315, 0x0ffff33b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH316, 0x0ffff33c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH317, 0x0ffff33d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH318, 0x0ffff33e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH319, 0x0ffff33f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH320, 0x0ffff340 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH321, 0x0ffff341 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH322, 0x0ffff342 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH323, 0x0ffff343 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH324, 0x0ffff344 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH325, 0x0ffff345 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH326, 0x0ffff346 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH327, 0x0ffff347 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH328, 0x0ffff348 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH329, 0x0ffff349 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH330, 0x0ffff34a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH331, 0x0ffff34b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH332, 0x0ffff34c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH333, 0x0ffff34d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH334, 0x0ffff34e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH335, 0x0ffff34f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH336, 0x0ffff350 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH337, 0x0ffff351 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH338, 0x0ffff352 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH339, 0x0ffff353 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH340, 0x0ffff354 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH341, 0x0ffff355 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH342, 0x0ffff356 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH343, 0x0ffff357 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH344, 0x0ffff358 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH345, 0x0ffff359 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH346, 0x0ffff35a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH347, 0x0ffff35b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH348, 0x0ffff35c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH349, 0x0ffff35d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH350, 0x0ffff35e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH351, 0x0ffff35f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH352, 0x0ffff360 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH353, 0x0ffff361 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH354, 0x0ffff362 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH355, 0x0ffff363 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH356, 0x0ffff364 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH357, 0x0ffff365 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH358, 0x0ffff366 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH359, 0x0ffff367 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH360, 0x0ffff368 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH361, 0x0ffff369 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH362, 0x0ffff36a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH363, 0x0ffff36b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH364, 0x0ffff36c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH365, 0x0ffff36d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH366, 0x0ffff36e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH367, 0x0ffff36f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH368, 0x0ffff370 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH369, 0x0ffff371 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH370, 0x0ffff372 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH371, 0x0ffff373 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH372, 0x0ffff374 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH373, 0x0ffff375 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH374, 0x0ffff376 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH375, 0x0ffff377 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH376, 0x0ffff378 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH377, 0x0ffff379 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH378, 0x0ffff37a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH379, 0x0ffff37b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH380, 0x0ffff37c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH381, 0x0ffff37d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH382, 0x0ffff37e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH383, 0x0ffff37f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH384, 0x0ffff380 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH385, 0x0ffff381 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH386, 0x0ffff382 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH387, 0x0ffff383 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH388, 0x0ffff384 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH389, 0x0ffff385 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH390, 0x0ffff386 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH391, 0x0ffff387 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH392, 0x0ffff388 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH393, 0x0ffff389 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH394, 0x0ffff38a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH395, 0x0ffff38b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH396, 0x0ffff38c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH397, 0x0ffff38d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH398, 0x0ffff38e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH399, 0x0ffff38f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH400, 0x0ffff390 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH401, 0x0ffff391 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH402, 0x0ffff392 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH403, 0x0ffff393 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH404, 0x0ffff394 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH405, 0x0ffff395 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH406, 0x0ffff396 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH407, 0x0ffff397 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH408, 0x0ffff398 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH409, 0x0ffff399 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH410, 0x0ffff39a +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH411, 0x0ffff39b +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH412, 0x0ffff39c +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH413, 0x0ffff39d +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH414, 0x0ffff39e +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH415, 0x0ffff39f +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH416, 0x0ffff3a0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH417, 0x0ffff3a1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH418, 0x0ffff3a2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH419, 0x0ffff3a3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH420, 0x0ffff3a4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH421, 0x0ffff3a5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH422, 0x0ffff3a6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH423, 0x0ffff3a7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH424, 0x0ffff3a8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH425, 0x0ffff3a9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH426, 0x0ffff3aa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH427, 0x0ffff3ab +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH428, 0x0ffff3ac +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH429, 0x0ffff3ad +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH430, 0x0ffff3ae +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH431, 0x0ffff3af +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH432, 0x0ffff3b0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH433, 0x0ffff3b1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH434, 0x0ffff3b2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH435, 0x0ffff3b3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH436, 0x0ffff3b4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH437, 0x0ffff3b5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH438, 0x0ffff3b6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH439, 0x0ffff3b7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH440, 0x0ffff3b8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH441, 0x0ffff3b9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH442, 0x0ffff3ba +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH443, 0x0ffff3bb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH444, 0x0ffff3bc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH445, 0x0ffff3bd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH446, 0x0ffff3be +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH447, 0x0ffff3bf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH448, 0x0ffff3c0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH449, 0x0ffff3c1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH450, 0x0ffff3c2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH451, 0x0ffff3c3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH452, 0x0ffff3c4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH453, 0x0ffff3c5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH454, 0x0ffff3c6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH455, 0x0ffff3c7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH456, 0x0ffff3c8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH457, 0x0ffff3c9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH458, 0x0ffff3ca +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH459, 0x0ffff3cb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH460, 0x0ffff3cc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH461, 0x0ffff3cd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH462, 0x0ffff3ce +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH463, 0x0ffff3cf +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH464, 0x0ffff3d0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH465, 0x0ffff3d1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH466, 0x0ffff3d2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH467, 0x0ffff3d3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH468, 0x0ffff3d4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH469, 0x0ffff3d5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH470, 0x0ffff3d6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH471, 0x0ffff3d7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH472, 0x0ffff3d8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH473, 0x0ffff3d9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH474, 0x0ffff3da +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH475, 0x0ffff3db +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH476, 0x0ffff3dc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH477, 0x0ffff3dd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH478, 0x0ffff3de +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH479, 0x0ffff3df +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH480, 0x0ffff3e0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH481, 0x0ffff3e1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH482, 0x0ffff3e2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH483, 0x0ffff3e3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH484, 0x0ffff3e4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH485, 0x0ffff3e5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH486, 0x0ffff3e6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH487, 0x0ffff3e7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH488, 0x0ffff3e8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH489, 0x0ffff3e9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH490, 0x0ffff3ea +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH491, 0x0ffff3eb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH492, 0x0ffff3ec +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH493, 0x0ffff3ed +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH494, 0x0ffff3ee +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH495, 0x0ffff3ef +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH496, 0x0ffff3f0 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH497, 0x0ffff3f1 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH498, 0x0ffff3f2 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH499, 0x0ffff3f3 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH500, 0x0ffff3f4 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH501, 0x0ffff3f5 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH502, 0x0ffff3f6 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH503, 0x0ffff3f7 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH504, 0x0ffff3f8 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH505, 0x0ffff3f9 +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH506, 0x0ffff3fa +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH507, 0x0ffff3fb +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH508, 0x0ffff3fc +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH509, 0x0ffff3fd +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH510, 0x0ffff3fe +.set CYREG_SFLASH_MACRO_0_FREE_SFLASH511, 0x0ffff3ff +.set CYREG_SFLASH_ALT_PROT_ROW0, 0x0ffff400 +.set CYREG_SFLASH_ALT_PROT_ROW1, 0x0ffff401 +.set CYREG_SFLASH_ALT_PROT_ROW2, 0x0ffff402 +.set CYREG_SFLASH_ALT_PROT_ROW3, 0x0ffff403 +.set CYREG_SFLASH_ALT_PROT_ROW4, 0x0ffff404 +.set CYREG_SFLASH_ALT_PROT_ROW5, 0x0ffff405 +.set CYREG_SFLASH_ALT_PROT_ROW6, 0x0ffff406 +.set CYREG_SFLASH_ALT_PROT_ROW7, 0x0ffff407 +.set CYREG_SFLASH_ALT_PROT_ROW8, 0x0ffff408 +.set CYREG_SFLASH_ALT_PROT_ROW9, 0x0ffff409 +.set CYREG_SFLASH_ALT_PROT_ROW10, 0x0ffff40a +.set CYREG_SFLASH_ALT_PROT_ROW11, 0x0ffff40b +.set CYREG_SFLASH_ALT_PROT_ROW12, 0x0ffff40c +.set CYREG_SFLASH_ALT_PROT_ROW13, 0x0ffff40d +.set CYREG_SFLASH_ALT_PROT_ROW14, 0x0ffff40e +.set CYREG_SFLASH_ALT_PROT_ROW15, 0x0ffff40f +.set CYREG_SFLASH_ALT_PROT_ROW16, 0x0ffff410 +.set CYREG_SFLASH_ALT_PROT_ROW17, 0x0ffff411 +.set CYREG_SFLASH_ALT_PROT_ROW18, 0x0ffff412 +.set CYREG_SFLASH_ALT_PROT_ROW19, 0x0ffff413 +.set CYREG_SFLASH_ALT_PROT_ROW20, 0x0ffff414 +.set CYREG_SFLASH_ALT_PROT_ROW21, 0x0ffff415 +.set CYREG_SFLASH_ALT_PROT_ROW22, 0x0ffff416 +.set CYREG_SFLASH_ALT_PROT_ROW23, 0x0ffff417 +.set CYREG_SFLASH_ALT_PROT_ROW24, 0x0ffff418 +.set CYREG_SFLASH_ALT_PROT_ROW25, 0x0ffff419 +.set CYREG_SFLASH_ALT_PROT_ROW26, 0x0ffff41a +.set CYREG_SFLASH_ALT_PROT_ROW27, 0x0ffff41b +.set CYREG_SFLASH_ALT_PROT_ROW28, 0x0ffff41c +.set CYREG_SFLASH_ALT_PROT_ROW29, 0x0ffff41d +.set CYREG_SFLASH_ALT_PROT_ROW30, 0x0ffff41e +.set CYREG_SFLASH_ALT_PROT_ROW31, 0x0ffff41f +.set CYREG_SFLASH_ALT_PROT_ROW32, 0x0ffff420 +.set CYREG_SFLASH_ALT_PROT_ROW33, 0x0ffff421 +.set CYREG_SFLASH_ALT_PROT_ROW34, 0x0ffff422 +.set CYREG_SFLASH_ALT_PROT_ROW35, 0x0ffff423 +.set CYREG_SFLASH_ALT_PROT_ROW36, 0x0ffff424 +.set CYREG_SFLASH_ALT_PROT_ROW37, 0x0ffff425 +.set CYREG_SFLASH_ALT_PROT_ROW38, 0x0ffff426 +.set CYREG_SFLASH_ALT_PROT_ROW39, 0x0ffff427 +.set CYREG_SFLASH_ALT_PROT_ROW40, 0x0ffff428 +.set CYREG_SFLASH_ALT_PROT_ROW41, 0x0ffff429 +.set CYREG_SFLASH_ALT_PROT_ROW42, 0x0ffff42a +.set CYREG_SFLASH_ALT_PROT_ROW43, 0x0ffff42b +.set CYREG_SFLASH_ALT_PROT_ROW44, 0x0ffff42c +.set CYREG_SFLASH_ALT_PROT_ROW45, 0x0ffff42d +.set CYREG_SFLASH_ALT_PROT_ROW46, 0x0ffff42e +.set CYREG_SFLASH_ALT_PROT_ROW47, 0x0ffff42f +.set CYREG_SFLASH_ALT_PROT_ROW48, 0x0ffff430 +.set CYREG_SFLASH_ALT_PROT_ROW49, 0x0ffff431 +.set CYREG_SFLASH_ALT_PROT_ROW50, 0x0ffff432 +.set CYREG_SFLASH_ALT_PROT_ROW51, 0x0ffff433 +.set CYREG_SFLASH_ALT_PROT_ROW52, 0x0ffff434 +.set CYREG_SFLASH_ALT_PROT_ROW53, 0x0ffff435 +.set CYREG_SFLASH_ALT_PROT_ROW54, 0x0ffff436 +.set CYREG_SFLASH_ALT_PROT_ROW55, 0x0ffff437 +.set CYREG_SFLASH_ALT_PROT_ROW56, 0x0ffff438 +.set CYREG_SFLASH_ALT_PROT_ROW57, 0x0ffff439 +.set CYREG_SFLASH_ALT_PROT_ROW58, 0x0ffff43a +.set CYREG_SFLASH_ALT_PROT_ROW59, 0x0ffff43b +.set CYREG_SFLASH_ALT_PROT_ROW60, 0x0ffff43c +.set CYREG_SFLASH_ALT_PROT_ROW61, 0x0ffff43d +.set CYREG_SFLASH_ALT_PROT_ROW62, 0x0ffff43e +.set CYREG_SFLASH_ALT_PROT_ROW63, 0x0ffff43f +.set CYREG_SFLASH_ALT_PROT_ROW64, 0x0ffff440 +.set CYREG_SFLASH_ALT_PROT_ROW65, 0x0ffff441 +.set CYREG_SFLASH_ALT_PROT_ROW66, 0x0ffff442 +.set CYREG_SFLASH_ALT_PROT_ROW67, 0x0ffff443 +.set CYREG_SFLASH_ALT_PROT_ROW68, 0x0ffff444 +.set CYREG_SFLASH_ALT_PROT_ROW69, 0x0ffff445 +.set CYREG_SFLASH_ALT_PROT_ROW70, 0x0ffff446 +.set CYREG_SFLASH_ALT_PROT_ROW71, 0x0ffff447 +.set CYREG_SFLASH_ALT_PROT_ROW72, 0x0ffff448 +.set CYREG_SFLASH_ALT_PROT_ROW73, 0x0ffff449 +.set CYREG_SFLASH_ALT_PROT_ROW74, 0x0ffff44a +.set CYREG_SFLASH_ALT_PROT_ROW75, 0x0ffff44b +.set CYREG_SFLASH_ALT_PROT_ROW76, 0x0ffff44c +.set CYREG_SFLASH_ALT_PROT_ROW77, 0x0ffff44d +.set CYREG_SFLASH_ALT_PROT_ROW78, 0x0ffff44e +.set CYREG_SFLASH_ALT_PROT_ROW79, 0x0ffff44f +.set CYREG_SFLASH_ALT_PROT_ROW80, 0x0ffff450 +.set CYREG_SFLASH_ALT_PROT_ROW81, 0x0ffff451 +.set CYREG_SFLASH_ALT_PROT_ROW82, 0x0ffff452 +.set CYREG_SFLASH_ALT_PROT_ROW83, 0x0ffff453 +.set CYREG_SFLASH_ALT_PROT_ROW84, 0x0ffff454 +.set CYREG_SFLASH_ALT_PROT_ROW85, 0x0ffff455 +.set CYREG_SFLASH_ALT_PROT_ROW86, 0x0ffff456 +.set CYREG_SFLASH_ALT_PROT_ROW87, 0x0ffff457 +.set CYREG_SFLASH_ALT_PROT_ROW88, 0x0ffff458 +.set CYREG_SFLASH_ALT_PROT_ROW89, 0x0ffff459 +.set CYREG_SFLASH_ALT_PROT_ROW90, 0x0ffff45a +.set CYREG_SFLASH_ALT_PROT_ROW91, 0x0ffff45b +.set CYREG_SFLASH_ALT_PROT_ROW92, 0x0ffff45c +.set CYREG_SFLASH_ALT_PROT_ROW93, 0x0ffff45d +.set CYREG_SFLASH_ALT_PROT_ROW94, 0x0ffff45e +.set CYREG_SFLASH_ALT_PROT_ROW95, 0x0ffff45f +.set CYREG_SFLASH_ALT_PROT_ROW96, 0x0ffff460 +.set CYREG_SFLASH_ALT_PROT_ROW97, 0x0ffff461 +.set CYREG_SFLASH_ALT_PROT_ROW98, 0x0ffff462 +.set CYREG_SFLASH_ALT_PROT_ROW99, 0x0ffff463 +.set CYREG_SFLASH_ALT_PROT_ROW100, 0x0ffff464 +.set CYREG_SFLASH_ALT_PROT_ROW101, 0x0ffff465 +.set CYREG_SFLASH_ALT_PROT_ROW102, 0x0ffff466 +.set CYREG_SFLASH_ALT_PROT_ROW103, 0x0ffff467 +.set CYREG_SFLASH_ALT_PROT_ROW104, 0x0ffff468 +.set CYREG_SFLASH_ALT_PROT_ROW105, 0x0ffff469 +.set CYREG_SFLASH_ALT_PROT_ROW106, 0x0ffff46a +.set CYREG_SFLASH_ALT_PROT_ROW107, 0x0ffff46b +.set CYREG_SFLASH_ALT_PROT_ROW108, 0x0ffff46c +.set CYREG_SFLASH_ALT_PROT_ROW109, 0x0ffff46d +.set CYREG_SFLASH_ALT_PROT_ROW110, 0x0ffff46e +.set CYREG_SFLASH_ALT_PROT_ROW111, 0x0ffff46f +.set CYREG_SFLASH_ALT_PROT_ROW112, 0x0ffff470 +.set CYREG_SFLASH_ALT_PROT_ROW113, 0x0ffff471 +.set CYREG_SFLASH_ALT_PROT_ROW114, 0x0ffff472 +.set CYREG_SFLASH_ALT_PROT_ROW115, 0x0ffff473 +.set CYREG_SFLASH_ALT_PROT_ROW116, 0x0ffff474 +.set CYREG_SFLASH_ALT_PROT_ROW117, 0x0ffff475 +.set CYREG_SFLASH_ALT_PROT_ROW118, 0x0ffff476 +.set CYREG_SFLASH_ALT_PROT_ROW119, 0x0ffff477 +.set CYREG_SFLASH_ALT_PROT_ROW120, 0x0ffff478 +.set CYREG_SFLASH_ALT_PROT_ROW121, 0x0ffff479 +.set CYREG_SFLASH_ALT_PROT_ROW122, 0x0ffff47a +.set CYREG_SFLASH_ALT_PROT_ROW123, 0x0ffff47b +.set CYREG_SFLASH_ALT_PROT_ROW124, 0x0ffff47c +.set CYREG_SFLASH_ALT_PROT_ROW125, 0x0ffff47d +.set CYREG_SFLASH_ALT_PROT_ROW126, 0x0ffff47e +.set CYREG_SFLASH_ALT_PROT_ROW127, 0x0ffff47f +.set CYREG_SFLASH_ALT_PROT_ROW128, 0x0ffff480 +.set CYREG_SFLASH_ALT_PROT_ROW129, 0x0ffff481 +.set CYREG_SFLASH_ALT_PROT_ROW130, 0x0ffff482 +.set CYREG_SFLASH_ALT_PROT_ROW131, 0x0ffff483 +.set CYREG_SFLASH_ALT_PROT_ROW132, 0x0ffff484 +.set CYREG_SFLASH_ALT_PROT_ROW133, 0x0ffff485 +.set CYREG_SFLASH_ALT_PROT_ROW134, 0x0ffff486 +.set CYREG_SFLASH_ALT_PROT_ROW135, 0x0ffff487 +.set CYREG_SFLASH_ALT_PROT_ROW136, 0x0ffff488 +.set CYREG_SFLASH_ALT_PROT_ROW137, 0x0ffff489 +.set CYREG_SFLASH_ALT_PROT_ROW138, 0x0ffff48a +.set CYREG_SFLASH_ALT_PROT_ROW139, 0x0ffff48b +.set CYREG_SFLASH_ALT_PROT_ROW140, 0x0ffff48c +.set CYREG_SFLASH_ALT_PROT_ROW141, 0x0ffff48d +.set CYREG_SFLASH_ALT_PROT_ROW142, 0x0ffff48e +.set CYREG_SFLASH_ALT_PROT_ROW143, 0x0ffff48f +.set CYREG_SFLASH_ALT_PROT_ROW144, 0x0ffff490 +.set CYREG_SFLASH_ALT_PROT_ROW145, 0x0ffff491 +.set CYREG_SFLASH_ALT_PROT_ROW146, 0x0ffff492 +.set CYREG_SFLASH_ALT_PROT_ROW147, 0x0ffff493 +.set CYREG_SFLASH_ALT_PROT_ROW148, 0x0ffff494 +.set CYREG_SFLASH_ALT_PROT_ROW149, 0x0ffff495 +.set CYREG_SFLASH_ALT_PROT_ROW150, 0x0ffff496 +.set CYREG_SFLASH_ALT_PROT_ROW151, 0x0ffff497 +.set CYREG_SFLASH_ALT_PROT_ROW152, 0x0ffff498 +.set CYREG_SFLASH_ALT_PROT_ROW153, 0x0ffff499 +.set CYREG_SFLASH_ALT_PROT_ROW154, 0x0ffff49a +.set CYREG_SFLASH_ALT_PROT_ROW155, 0x0ffff49b +.set CYREG_SFLASH_ALT_PROT_ROW156, 0x0ffff49c +.set CYREG_SFLASH_ALT_PROT_ROW157, 0x0ffff49d +.set CYREG_SFLASH_ALT_PROT_ROW158, 0x0ffff49e +.set CYREG_SFLASH_ALT_PROT_ROW159, 0x0ffff49f +.set CYREG_SFLASH_ALT_PROT_ROW160, 0x0ffff4a0 +.set CYREG_SFLASH_ALT_PROT_ROW161, 0x0ffff4a1 +.set CYREG_SFLASH_ALT_PROT_ROW162, 0x0ffff4a2 +.set CYREG_SFLASH_ALT_PROT_ROW163, 0x0ffff4a3 +.set CYREG_SFLASH_ALT_PROT_ROW164, 0x0ffff4a4 +.set CYREG_SFLASH_ALT_PROT_ROW165, 0x0ffff4a5 +.set CYREG_SFLASH_ALT_PROT_ROW166, 0x0ffff4a6 +.set CYREG_SFLASH_ALT_PROT_ROW167, 0x0ffff4a7 +.set CYREG_SFLASH_ALT_PROT_ROW168, 0x0ffff4a8 +.set CYREG_SFLASH_ALT_PROT_ROW169, 0x0ffff4a9 +.set CYREG_SFLASH_ALT_PROT_ROW170, 0x0ffff4aa +.set CYREG_SFLASH_ALT_PROT_ROW171, 0x0ffff4ab +.set CYREG_SFLASH_ALT_PROT_ROW172, 0x0ffff4ac +.set CYREG_SFLASH_ALT_PROT_ROW173, 0x0ffff4ad +.set CYREG_SFLASH_ALT_PROT_ROW174, 0x0ffff4ae +.set CYREG_SFLASH_ALT_PROT_ROW175, 0x0ffff4af +.set CYREG_SFLASH_ALT_PROT_ROW176, 0x0ffff4b0 +.set CYREG_SFLASH_ALT_PROT_ROW177, 0x0ffff4b1 +.set CYREG_SFLASH_ALT_PROT_ROW178, 0x0ffff4b2 +.set CYREG_SFLASH_ALT_PROT_ROW179, 0x0ffff4b3 +.set CYREG_SFLASH_ALT_PROT_ROW180, 0x0ffff4b4 +.set CYREG_SFLASH_ALT_PROT_ROW181, 0x0ffff4b5 +.set CYREG_SFLASH_ALT_PROT_ROW182, 0x0ffff4b6 +.set CYREG_SFLASH_ALT_PROT_ROW183, 0x0ffff4b7 +.set CYREG_SFLASH_ALT_PROT_ROW184, 0x0ffff4b8 +.set CYREG_SFLASH_ALT_PROT_ROW185, 0x0ffff4b9 +.set CYREG_SFLASH_ALT_PROT_ROW186, 0x0ffff4ba +.set CYREG_SFLASH_ALT_PROT_ROW187, 0x0ffff4bb +.set CYREG_SFLASH_ALT_PROT_ROW188, 0x0ffff4bc +.set CYREG_SFLASH_ALT_PROT_ROW189, 0x0ffff4bd +.set CYREG_SFLASH_ALT_PROT_ROW190, 0x0ffff4be +.set CYREG_SFLASH_ALT_PROT_ROW191, 0x0ffff4bf +.set CYREG_SFLASH_ALT_PROT_ROW192, 0x0ffff4c0 +.set CYREG_SFLASH_ALT_PROT_ROW193, 0x0ffff4c1 +.set CYREG_SFLASH_ALT_PROT_ROW194, 0x0ffff4c2 +.set CYREG_SFLASH_ALT_PROT_ROW195, 0x0ffff4c3 +.set CYREG_SFLASH_ALT_PROT_ROW196, 0x0ffff4c4 +.set CYREG_SFLASH_ALT_PROT_ROW197, 0x0ffff4c5 +.set CYREG_SFLASH_ALT_PROT_ROW198, 0x0ffff4c6 +.set CYREG_SFLASH_ALT_PROT_ROW199, 0x0ffff4c7 +.set CYREG_SFLASH_ALT_PROT_ROW200, 0x0ffff4c8 +.set CYREG_SFLASH_ALT_PROT_ROW201, 0x0ffff4c9 +.set CYREG_SFLASH_ALT_PROT_ROW202, 0x0ffff4ca +.set CYREG_SFLASH_ALT_PROT_ROW203, 0x0ffff4cb +.set CYREG_SFLASH_ALT_PROT_ROW204, 0x0ffff4cc +.set CYREG_SFLASH_ALT_PROT_ROW205, 0x0ffff4cd +.set CYREG_SFLASH_ALT_PROT_ROW206, 0x0ffff4ce +.set CYREG_SFLASH_ALT_PROT_ROW207, 0x0ffff4cf +.set CYREG_SFLASH_ALT_PROT_ROW208, 0x0ffff4d0 +.set CYREG_SFLASH_ALT_PROT_ROW209, 0x0ffff4d1 +.set CYREG_SFLASH_ALT_PROT_ROW210, 0x0ffff4d2 +.set CYREG_SFLASH_ALT_PROT_ROW211, 0x0ffff4d3 +.set CYREG_SFLASH_ALT_PROT_ROW212, 0x0ffff4d4 +.set CYREG_SFLASH_ALT_PROT_ROW213, 0x0ffff4d5 +.set CYREG_SFLASH_ALT_PROT_ROW214, 0x0ffff4d6 +.set CYREG_SFLASH_ALT_PROT_ROW215, 0x0ffff4d7 +.set CYREG_SFLASH_ALT_PROT_ROW216, 0x0ffff4d8 +.set CYREG_SFLASH_ALT_PROT_ROW217, 0x0ffff4d9 +.set CYREG_SFLASH_ALT_PROT_ROW218, 0x0ffff4da +.set CYREG_SFLASH_ALT_PROT_ROW219, 0x0ffff4db +.set CYREG_SFLASH_ALT_PROT_ROW220, 0x0ffff4dc +.set CYREG_SFLASH_ALT_PROT_ROW221, 0x0ffff4dd +.set CYREG_SFLASH_ALT_PROT_ROW222, 0x0ffff4de +.set CYREG_SFLASH_ALT_PROT_ROW223, 0x0ffff4df +.set CYREG_SFLASH_ALT_PROT_ROW224, 0x0ffff4e0 +.set CYREG_SFLASH_ALT_PROT_ROW225, 0x0ffff4e1 +.set CYREG_SFLASH_ALT_PROT_ROW226, 0x0ffff4e2 +.set CYREG_SFLASH_ALT_PROT_ROW227, 0x0ffff4e3 +.set CYREG_SFLASH_ALT_PROT_ROW228, 0x0ffff4e4 +.set CYREG_SFLASH_ALT_PROT_ROW229, 0x0ffff4e5 +.set CYREG_SFLASH_ALT_PROT_ROW230, 0x0ffff4e6 +.set CYREG_SFLASH_ALT_PROT_ROW231, 0x0ffff4e7 +.set CYREG_SFLASH_ALT_PROT_ROW232, 0x0ffff4e8 +.set CYREG_SFLASH_ALT_PROT_ROW233, 0x0ffff4e9 +.set CYREG_SFLASH_ALT_PROT_ROW234, 0x0ffff4ea +.set CYREG_SFLASH_ALT_PROT_ROW235, 0x0ffff4eb +.set CYREG_SFLASH_ALT_PROT_ROW236, 0x0ffff4ec +.set CYREG_SFLASH_ALT_PROT_ROW237, 0x0ffff4ed +.set CYREG_SFLASH_ALT_PROT_ROW238, 0x0ffff4ee +.set CYREG_SFLASH_ALT_PROT_ROW239, 0x0ffff4ef +.set CYREG_SFLASH_ALT_PROT_ROW240, 0x0ffff4f0 +.set CYREG_SFLASH_ALT_PROT_ROW241, 0x0ffff4f1 +.set CYREG_SFLASH_ALT_PROT_ROW242, 0x0ffff4f2 +.set CYREG_SFLASH_ALT_PROT_ROW243, 0x0ffff4f3 +.set CYREG_SFLASH_ALT_PROT_ROW244, 0x0ffff4f4 +.set CYREG_SFLASH_ALT_PROT_ROW245, 0x0ffff4f5 +.set CYREG_SFLASH_ALT_PROT_ROW246, 0x0ffff4f6 +.set CYREG_SFLASH_ALT_PROT_ROW247, 0x0ffff4f7 +.set CYREG_SFLASH_ALT_PROT_ROW248, 0x0ffff4f8 +.set CYREG_SFLASH_ALT_PROT_ROW249, 0x0ffff4f9 +.set CYREG_SFLASH_ALT_PROT_ROW250, 0x0ffff4fa +.set CYREG_SFLASH_ALT_PROT_ROW251, 0x0ffff4fb +.set CYREG_SFLASH_ALT_PROT_ROW252, 0x0ffff4fc +.set CYREG_SFLASH_ALT_PROT_ROW253, 0x0ffff4fd +.set CYREG_SFLASH_ALT_PROT_ROW254, 0x0ffff4fe +.set CYREG_SFLASH_ALT_PROT_ROW255, 0x0ffff4ff +.set CYREG_SFLASH_ALT_PP, 0x0ffff5a0 .set CYFLD_SFLASH_PERIOD__OFFSET, 0x00000000 .set CYFLD_SFLASH_PERIOD__SIZE, 0x00000018 .set CYFLD_SFLASH_PDAC__OFFSET, 0x00000018 .set CYFLD_SFLASH_PDAC__SIZE, 0x00000004 .set CYFLD_SFLASH_NDAC__OFFSET, 0x0000001c .set CYFLD_SFLASH_NDAC__SIZE, 0x00000004 -.set CYREG_SFLASH_ALT_E, 0x0ffffb24 -.set CYREG_SFLASH_ALT_P, 0x0ffffb28 -.set CYREG_SFLASH_ALT_EA_E, 0x0ffffb2c -.set CYREG_SFLASH_ALT_EA_P, 0x0ffffb30 -.set CYREG_SFLASH_ALT_ES_E, 0x0ffffb34 -.set CYREG_SFLASH_ALT_ES_P_EO, 0x0ffffb38 -.set CYREG_SFLASH_ALT_E_VCTAT, 0x0ffffb3c +.set CYREG_SFLASH_ALT_E, 0x0ffff5a4 +.set CYREG_SFLASH_ALT_P, 0x0ffff5a8 +.set CYREG_SFLASH_ALT_EA_E, 0x0ffff5ac +.set CYREG_SFLASH_ALT_EA_P, 0x0ffff5b0 +.set CYREG_SFLASH_ALT_ES_E, 0x0ffff5b4 +.set CYREG_SFLASH_ALT_ES_P_EO, 0x0ffff5b8 +.set CYREG_SFLASH_ALT_E_VCTAT, 0x0ffff5bc .set CYFLD_SFLASH_VCTAT_SLOPE__OFFSET, 0x00000000 .set CYFLD_SFLASH_VCTAT_SLOPE__SIZE, 0x00000004 .set CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET, 0x00000004 .set CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE, 0x00000002 .set CYFLD_SFLASH_VCTAT_ENABLE__OFFSET, 0x00000006 .set CYFLD_SFLASH_VCTAT_ENABLE__SIZE, 0x00000001 -.set CYREG_SFLASH_ALT_P_VCTAT, 0x0ffffb3d +.set CYREG_SFLASH_ALT_P_VCTAT, 0x0ffff5bd .set CYDEV_ROM_BASE, 0x10000000 .set CYDEV_ROM_SIZE, 0x00002000 .set CYREG_ROM_DATA_MBASE, 0x10000000 .set CYREG_ROM_DATA_MSIZE, 0x00002000 .set CYDEV_SRAM_BASE, 0x20000000 -.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYDEV_SRAM_SIZE, 0x00004000 .set CYREG_SRAM_DATA_MBASE, 0x20000000 -.set CYREG_SRAM_DATA_MSIZE, 0x00008000 +.set CYREG_SRAM_DATA_MSIZE, 0x00004000 .set CYDEV_PERI_BASE, 0x40010000 .set CYDEV_PERI_SIZE, 0x00010000 .set CYREG_PERI_DIV_CMD, 0x40010000 @@ -1846,29 +1288,6 @@ .set CYFLD_PERI_FRAC5_DIV__OFFSET, 0x00000003 .set CYFLD_PERI_FRAC5_DIV__SIZE, 0x00000005 .set CYREG_PERI_DIV_16_5_CTL1, 0x40010404 -.set CYREG_PERI_TR_CTL, 0x40010600 -.set CYFLD_PERI_TR_SEL__OFFSET, 0x00000000 -.set CYFLD_PERI_TR_SEL__SIZE, 0x00000007 -.set CYFLD_PERI_TR_GROUP__OFFSET, 0x00000008 -.set CYFLD_PERI_TR_GROUP__SIZE, 0x00000004 -.set CYFLD_PERI_TR_COUNT__OFFSET, 0x00000010 -.set CYFLD_PERI_TR_COUNT__SIZE, 0x00000008 -.set CYFLD_PERI_TR_OUT__OFFSET, 0x0000001e -.set CYFLD_PERI_TR_OUT__SIZE, 0x00000001 -.set CYFLD_PERI_TR_ACT__OFFSET, 0x0000001f -.set CYFLD_PERI_TR_ACT__SIZE, 0x00000001 -.set CYDEV_PERI_TR_GROUP_BASE, 0x40012000 -.set CYDEV_PERI_TR_GROUP_SIZE, 0x00000200 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL0, 0x40012000 -.set CYFLD_PERI_TR_GROUP_SEL__OFFSET, 0x00000000 -.set CYFLD_PERI_TR_GROUP_SEL__SIZE, 0x00000005 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL1, 0x40012004 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL2, 0x40012008 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL3, 0x4001200c -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL4, 0x40012010 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL5, 0x40012014 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL6, 0x40012018 -.set CYREG_PERI_TR_GROUP_TR_OUT_CTL7, 0x4001201c .set CYDEV_HSIOM_BASE, 0x40020000 .set CYDEV_HSIOM_SIZE, 0x00004000 .set CYREG_HSIOM_PORT_SEL0, 0x40020000 @@ -6251,165 +5670,9 @@ .set CYFLD_CPUSS_PREF_EN__SIZE, 0x00000001 .set CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET, 0x00000008 .set CYFLD_CPUSS_FLASH_INVALIDATE__SIZE, 0x00000001 -.set CYFLD_CPUSS_ARB__OFFSET, 0x00000010 -.set CYFLD_CPUSS_ARB__SIZE, 0x00000002 .set CYREG_CPUSS_ROM_CTL, 0x40100034 .set CYFLD_CPUSS_ROM_WS__OFFSET, 0x00000000 .set CYFLD_CPUSS_ROM_WS__SIZE, 0x00000001 -.set CYREG_CPUSS_RAM_CTL, 0x40100038 -.set CYREG_CPUSS_DMAC_CTL, 0x4010003c -.set CYREG_CPUSS_SL_CTL0, 0x40100100 -.set CYREG_CPUSS_SL_CTL1, 0x40100104 -.set CYREG_CPUSS_SL_CTL2, 0x40100108 -.set CYDEV_DMAC_BASE, 0x40101000 -.set CYDEV_DMAC_SIZE, 0x00001000 -.set CYREG_DMAC_CTL, 0x40101000 -.set CYFLD_DMAC_ENABLED__OFFSET, 0x0000001f -.set CYFLD_DMAC_ENABLED__SIZE, 0x00000001 -.set CYREG_DMAC_STATUS, 0x40101010 -.set CYFLD_DMAC_DATA_NR__OFFSET, 0x00000000 -.set CYFLD_DMAC_DATA_NR__SIZE, 0x00000010 -.set CYFLD_DMAC_CH_ADDR__OFFSET, 0x00000010 -.set CYFLD_DMAC_CH_ADDR__SIZE, 0x00000003 -.set CYFLD_DMAC_STATE__OFFSET, 0x00000018 -.set CYFLD_DMAC_STATE__SIZE, 0x00000003 -.set CYFLD_DMAC_PRIO__OFFSET, 0x0000001c -.set CYFLD_DMAC_PRIO__SIZE, 0x00000002 -.set CYFLD_DMAC_PING_PONG__OFFSET, 0x0000001e -.set CYFLD_DMAC_PING_PONG__SIZE, 0x00000001 -.set CYFLD_DMAC_ACTIVE__OFFSET, 0x0000001f -.set CYFLD_DMAC_ACTIVE__SIZE, 0x00000001 -.set CYREG_DMAC_STATUS_SRC_ADDR, 0x40101014 -.set CYFLD_DMAC_ADDR__OFFSET, 0x00000000 -.set CYFLD_DMAC_ADDR__SIZE, 0x00000020 -.set CYREG_DMAC_STATUS_DST_ADDR, 0x40101018 -.set CYREG_DMAC_STATUS_CH_ACT, 0x4010101c -.set CYFLD_DMAC_CH__OFFSET, 0x00000000 -.set CYFLD_DMAC_CH__SIZE, 0x00000008 -.set CYREG_DMAC_CH_CTL0, 0x40101080 -.set CYREG_DMAC_CH_CTL1, 0x40101084 -.set CYREG_DMAC_CH_CTL2, 0x40101088 -.set CYREG_DMAC_CH_CTL3, 0x4010108c -.set CYREG_DMAC_CH_CTL4, 0x40101090 -.set CYREG_DMAC_CH_CTL5, 0x40101094 -.set CYREG_DMAC_CH_CTL6, 0x40101098 -.set CYREG_DMAC_CH_CTL7, 0x4010109c -.set CYREG_DMAC_INTR, 0x401017f0 -.set CYREG_DMAC_INTR_SET, 0x401017f4 -.set CYREG_DMAC_INTR_MASK, 0x401017f8 -.set CYREG_DMAC_INTR_MASKED, 0x401017fc -.set CYDEV_DMAC_DESCR0_BASE, 0x40101800 -.set CYDEV_DMAC_DESCR0_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR0_PING_SRC, 0x40101800 -.set CYFLD_DMAC_DESCR_ADDR__OFFSET, 0x00000000 -.set CYFLD_DMAC_DESCR_ADDR__SIZE, 0x00000020 -.set CYREG_DMAC_DESCR0_PING_DST, 0x40101804 -.set CYREG_DMAC_DESCR0_PING_CTL, 0x40101808 -.set CYFLD_DMAC_DESCR_DATA_NR__OFFSET, 0x00000000 -.set CYFLD_DMAC_DESCR_DATA_NR__SIZE, 0x00000010 -.set CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET, 0x00000010 -.set CYFLD_DMAC_DESCR_DATA_SIZE__SIZE, 0x00000002 -.set CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET, 0x00000014 -.set CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET, 0x00000015 -.set CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET, 0x00000016 -.set CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET, 0x00000017 -.set CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET, 0x00000018 -.set CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE, 0x00000002 -.set CYFLD_DMAC_DESCR_INV_DESCR__OFFSET, 0x0000001a -.set CYFLD_DMAC_DESCR_INV_DESCR__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET, 0x0000001b -.set CYFLD_DMAC_DESCR_SET_CAUSE__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET, 0x0000001c -.set CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_FLIPPING__OFFSET, 0x0000001d -.set CYFLD_DMAC_DESCR_FLIPPING__SIZE, 0x00000001 -.set CYFLD_DMAC_DESCR_OPCODE__OFFSET, 0x0000001e -.set CYFLD_DMAC_DESCR_OPCODE__SIZE, 0x00000002 -.set CYREG_DMAC_DESCR0_PING_STATUS, 0x4010180c -.set CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET, 0x00000000 -.set CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE, 0x00000010 -.set CYFLD_DMAC_DESCR_RESPONSE__OFFSET, 0x00000010 -.set CYFLD_DMAC_DESCR_RESPONSE__SIZE, 0x00000003 -.set CYFLD_DMAC_DESCR_VALID__OFFSET, 0x0000001f -.set CYFLD_DMAC_DESCR_VALID__SIZE, 0x00000001 -.set CYREG_DMAC_DESCR0_PONG_SRC, 0x40101810 -.set CYREG_DMAC_DESCR0_PONG_DST, 0x40101814 -.set CYREG_DMAC_DESCR0_PONG_CTL, 0x40101818 -.set CYREG_DMAC_DESCR0_PONG_STATUS, 0x4010181c -.set CYDEV_DMAC_DESCR1_BASE, 0x40101820 -.set CYDEV_DMAC_DESCR1_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR1_PING_SRC, 0x40101820 -.set CYREG_DMAC_DESCR1_PING_DST, 0x40101824 -.set CYREG_DMAC_DESCR1_PING_CTL, 0x40101828 -.set CYREG_DMAC_DESCR1_PING_STATUS, 0x4010182c -.set CYREG_DMAC_DESCR1_PONG_SRC, 0x40101830 -.set CYREG_DMAC_DESCR1_PONG_DST, 0x40101834 -.set CYREG_DMAC_DESCR1_PONG_CTL, 0x40101838 -.set CYREG_DMAC_DESCR1_PONG_STATUS, 0x4010183c -.set CYDEV_DMAC_DESCR2_BASE, 0x40101840 -.set CYDEV_DMAC_DESCR2_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR2_PING_SRC, 0x40101840 -.set CYREG_DMAC_DESCR2_PING_DST, 0x40101844 -.set CYREG_DMAC_DESCR2_PING_CTL, 0x40101848 -.set CYREG_DMAC_DESCR2_PING_STATUS, 0x4010184c -.set CYREG_DMAC_DESCR2_PONG_SRC, 0x40101850 -.set CYREG_DMAC_DESCR2_PONG_DST, 0x40101854 -.set CYREG_DMAC_DESCR2_PONG_CTL, 0x40101858 -.set CYREG_DMAC_DESCR2_PONG_STATUS, 0x4010185c -.set CYDEV_DMAC_DESCR3_BASE, 0x40101860 -.set CYDEV_DMAC_DESCR3_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR3_PING_SRC, 0x40101860 -.set CYREG_DMAC_DESCR3_PING_DST, 0x40101864 -.set CYREG_DMAC_DESCR3_PING_CTL, 0x40101868 -.set CYREG_DMAC_DESCR3_PING_STATUS, 0x4010186c -.set CYREG_DMAC_DESCR3_PONG_SRC, 0x40101870 -.set CYREG_DMAC_DESCR3_PONG_DST, 0x40101874 -.set CYREG_DMAC_DESCR3_PONG_CTL, 0x40101878 -.set CYREG_DMAC_DESCR3_PONG_STATUS, 0x4010187c -.set CYDEV_DMAC_DESCR4_BASE, 0x40101880 -.set CYDEV_DMAC_DESCR4_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR4_PING_SRC, 0x40101880 -.set CYREG_DMAC_DESCR4_PING_DST, 0x40101884 -.set CYREG_DMAC_DESCR4_PING_CTL, 0x40101888 -.set CYREG_DMAC_DESCR4_PING_STATUS, 0x4010188c -.set CYREG_DMAC_DESCR4_PONG_SRC, 0x40101890 -.set CYREG_DMAC_DESCR4_PONG_DST, 0x40101894 -.set CYREG_DMAC_DESCR4_PONG_CTL, 0x40101898 -.set CYREG_DMAC_DESCR4_PONG_STATUS, 0x4010189c -.set CYDEV_DMAC_DESCR5_BASE, 0x401018a0 -.set CYDEV_DMAC_DESCR5_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR5_PING_SRC, 0x401018a0 -.set CYREG_DMAC_DESCR5_PING_DST, 0x401018a4 -.set CYREG_DMAC_DESCR5_PING_CTL, 0x401018a8 -.set CYREG_DMAC_DESCR5_PING_STATUS, 0x401018ac -.set CYREG_DMAC_DESCR5_PONG_SRC, 0x401018b0 -.set CYREG_DMAC_DESCR5_PONG_DST, 0x401018b4 -.set CYREG_DMAC_DESCR5_PONG_CTL, 0x401018b8 -.set CYREG_DMAC_DESCR5_PONG_STATUS, 0x401018bc -.set CYDEV_DMAC_DESCR6_BASE, 0x401018c0 -.set CYDEV_DMAC_DESCR6_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR6_PING_SRC, 0x401018c0 -.set CYREG_DMAC_DESCR6_PING_DST, 0x401018c4 -.set CYREG_DMAC_DESCR6_PING_CTL, 0x401018c8 -.set CYREG_DMAC_DESCR6_PING_STATUS, 0x401018cc -.set CYREG_DMAC_DESCR6_PONG_SRC, 0x401018d0 -.set CYREG_DMAC_DESCR6_PONG_DST, 0x401018d4 -.set CYREG_DMAC_DESCR6_PONG_CTL, 0x401018d8 -.set CYREG_DMAC_DESCR6_PONG_STATUS, 0x401018dc -.set CYDEV_DMAC_DESCR7_BASE, 0x401018e0 -.set CYDEV_DMAC_DESCR7_SIZE, 0x00000020 -.set CYREG_DMAC_DESCR7_PING_SRC, 0x401018e0 -.set CYREG_DMAC_DESCR7_PING_DST, 0x401018e4 -.set CYREG_DMAC_DESCR7_PING_CTL, 0x401018e8 -.set CYREG_DMAC_DESCR7_PING_STATUS, 0x401018ec -.set CYREG_DMAC_DESCR7_PONG_SRC, 0x401018f0 -.set CYREG_DMAC_DESCR7_PONG_DST, 0x401018f4 -.set CYREG_DMAC_DESCR7_PONG_CTL, 0x401018f8 -.set CYREG_DMAC_DESCR7_PONG_STATUS, 0x401018fc .set CYDEV_SPCIF_BASE, 0x40110000 .set CYDEV_SPCIF_SIZE, 0x00010000 .set CYREG_SPCIF_GEOMETRY, 0x40110000 @@ -8078,33 +7341,8 @@ .set CYREG_BLE_BLERD_READ_IQ_4, 0x402e010c .set CYFLD_BLE_BLERD_ADC_4__OFFSET, 0x00000000 .set CYFLD_BLE_BLERD_ADC_4__SIZE, 0x00000020 -.set CYREG_BLE_BLERD_AGC_GAIN_COMP_1, 0x402e0180 -.set CYFLD_BLE_BLERD_GAIN_5__OFFSET, 0x00000000 -.set CYFLD_BLE_BLERD_GAIN_5__SIZE, 0x00000005 -.set CYFLD_BLE_BLERD_GAIN_4__OFFSET, 0x00000005 -.set CYFLD_BLE_BLERD_GAIN_4__SIZE, 0x00000005 -.set CYFLD_BLE_BLERD_GAIN_3__OFFSET, 0x0000000a -.set CYFLD_BLE_BLERD_GAIN_3__SIZE, 0x00000005 -.set CYREG_BLE_BLERD_AGC_GAIN_COMP_2, 0x402e0184 -.set CYFLD_BLE_BLERD_GAIN_2__OFFSET, 0x00000000 -.set CYFLD_BLE_BLERD_GAIN_2__SIZE, 0x00000005 -.set CYFLD_BLE_BLERD_GAIN_1__OFFSET, 0x00000005 -.set CYFLD_BLE_BLERD_GAIN_1__SIZE, 0x00000005 -.set CYFLD_BLE_BLERD_GAIN_0__OFFSET, 0x0000000a -.set CYFLD_BLE_BLERD_GAIN_0__SIZE, 0x00000005 -.set CYREG_BLE_BLERD_PA_RSSI_NEW, 0x402e0188 -.set CYFLD_BLE_BLERD_PA_RAMP_STEP__OFFSET, 0x00000000 -.set CYFLD_BLE_BLERD_PA_RAMP_STEP__SIZE, 0x00000002 -.set CYFLD_BLE_BLERD_PA_RAMP_NEW__OFFSET, 0x00000003 -.set CYFLD_BLE_BLERD_PA_RAMP_NEW__SIZE, 0x00000001 -.set CYFLD_BLE_BLERD_MIN_RSSI_NEW__OFFSET, 0x00000004 -.set CYFLD_BLE_BLERD_MIN_RSSI_NEW__SIZE, 0x00000001 -.set CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__OFFSET, 0x00000005 -.set CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__OFFSET, 0x00000006 -.set CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__SIZE, 0x00000001 .set CYDEV_BLE_BLELL_BASE, 0x402e1000 -.set CYDEV_BLE_BLELL_SIZE, 0x00003000 +.set CYDEV_BLE_BLELL_SIZE, 0x00001000 .set CYREG_BLE_BLELL_COMMAND_REGISTER, 0x402e1000 .set CYFLD_BLE_BLELL_COMMAND__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_COMMAND__SIZE, 0x00000008 @@ -8151,14 +7389,6 @@ .set CYFLD_BLE_BLELL_RX_ADDR__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__OFFSET, 0x0000000a .set CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INITA_RPA_CHECK__OFFSET, 0x0000000b -.set CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET, 0x0000000c -.set CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__OFFSET, 0x0000000d -.set CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET, 0x0000000e -.set CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET, 0x0000000f .set CYFLD_BLE_BLELL_RCV_TX_ADDR__SIZE, 0x00000001 .set CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT, 0x402e101c @@ -8183,14 +7413,6 @@ .set CYFLD_BLE_BLELL_ADV_TIMEOUT__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_ADV_ON__OFFSET, 0x00000008 .set CYFLD_BLE_BLELL_ADV_ON__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET, 0x0000000a -.set CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET, 0x0000000b -.set CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET, 0x0000000c -.set CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE, 0x00000001 .set CYREG_BLE_BLELL_ADV_NEXT_INSTANT, 0x402e1024 .set CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__SIZE, 0x00000010 @@ -8207,14 +7429,6 @@ .set CYFLD_BLE_BLELL_SCAN_FILT_POLICY__SIZE, 0x00000002 .set CYFLD_BLE_BLELL_DUP_FILT_EN__OFFSET, 0x00000005 .set CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET, 0x00000008 -.set CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE, 0x00000001 .set CYREG_BLE_BLELL_SCAN_INTR, 0x402e1038 .set CYFLD_BLE_BLELL_SCAN_STRT_INTR__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_SCAN_STRT_INTR__SIZE, 0x00000001 @@ -8226,18 +7440,8 @@ .set CYFLD_BLE_BLELL_ADV_RX_INTR__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET, 0x00000004 .set CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__OFFSET, 0x00000005 -.set CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_SCAN_ON__OFFSET, 0x00000008 .set CYFLD_BLE_BLELL_SCAN_ON__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET, 0x0000000a -.set CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE, 0x00000001 .set CYREG_BLE_BLELL_SCAN_NEXT_INSTANT, 0x402e103c .set CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__SIZE, 0x00000010 @@ -8252,8 +7456,6 @@ .set CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_INIT_FILT_POLICY__OFFSET, 0x00000003 .set CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__OFFSET, 0x00000004 -.set CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE, 0x00000001 .set CYREG_BLE_BLELL_INIT_INTR, 0x402e1050 .set CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__SIZE, 0x00000001 @@ -8263,16 +7465,6 @@ .set CYFLD_BLE_BLELL_INIT_TX_START_INTR__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_MASTER_CONN_CREATED__OFFSET, 0x00000004 .set CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__OFFSET, 0x00000005 -.set CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET, 0x00000008 -.set CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE, 0x00000001 .set CYREG_BLE_BLELL_INIT_NEXT_INSTANT, 0x402e1054 .set CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__SIZE, 0x00000010 @@ -8467,7 +7659,7 @@ .set CYFLD_BLE_BLELL_LLID__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_LLID__SIZE, 0x00000002 .set CYFLD_BLE_BLELL_DATA_LENGTH__OFFSET, 0x00000002 -.set CYFLD_BLE_BLELL_DATA_LENGTH__SIZE, 0x00000008 +.set CYFLD_BLE_BLELL_DATA_LENGTH__SIZE, 0x00000005 .set CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1, 0x402e1144 .set CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2, 0x402e1148 .set CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3, 0x402e114c @@ -8490,9 +7682,6 @@ .set CYREG_BLE_BLELL_DTM_RX_PKT_COUNT, 0x402e1174 .set CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT, 0x402e1178 -.set CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_TEST_LENGTH_EXT__SIZE, 0x00000003 .set CYREG_BLE_BLELL_TXRX_HOP, 0x402e1188 .set CYFLD_BLE_BLELL_HOP_CH_TX__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_HOP_CH_TX__SIZE, 0x00000007 @@ -8537,10 +7726,6 @@ .set CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_ADV_RAND_DISABLE__OFFSET, 0x00000008 .set CYFLD_BLE_BLELL_ADV_RAND_DISABLE__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__OFFSET, 0x0000000a -.set CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__OFFSET, 0x0000000b .set CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__SIZE, 0x00000005 .set CYREG_BLE_BLELL_SCAN_CONFIG, 0x402e11d8 @@ -8554,14 +7739,6 @@ .set CYFLD_BLE_BLELL_ADV_RX_EN__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET, 0x00000004 .set CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET, 0x00000005 -.set CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET, 0x00000008 -.set CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET, 0x0000000b .set CYFLD_BLE_BLELL_BACKOFF_ENABLE__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__OFFSET, 0x0000000d @@ -8575,12 +7752,6 @@ .set CYFLD_BLE_BLELL_CONN_REQ_TX_EN__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_CONN_CREATED__OFFSET, 0x00000004 .set CYFLD_BLE_BLELL_CONN_CREATED__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__OFFSET, 0x00000005 -.set CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE, 0x00000001 .set CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__OFFSET, 0x0000000d .set CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__SIZE, 0x00000003 .set CYREG_BLE_BLELL_CONN_CONFIG, 0x402e11e0 @@ -8792,10 +7963,6 @@ .set CYFLD_BLE_BLELL_PAYLOAD_LENGTH__SIZE, 0x00000005 .set CYFLD_BLE_BLELL_DIRECTION__OFFSET, 0x00000007 .set CYFLD_BLE_BLELL_DIRECTION__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__OFFSET, 0x00000008 -.set CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__SIZE, 0x00000003 -.set CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__OFFSET, 0x0000000b -.set CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE, 0x00000001 .set CYREG_BLE_BLELL_ENC_CONFIG, 0x402e1490 .set CYFLD_BLE_BLELL_START_PROC__OFFSET, 0x00000000 .set CYFLD_BLE_BLELL_START_PROC__SIZE, 0x00000001 @@ -8870,97 +8037,6 @@ .set CYFLD_BLE_BLELL_RX_EN_DELAY__SIZE, 0x00000008 .set CYFLD_BLE_BLELL_TX_EN_DELAY__OFFSET, 0x00000008 .set CYFLD_BLE_BLELL_TX_EN_DELAY__SIZE, 0x00000008 -.set CYREG_BLE_BLELL_LL_CONTROL, 0x402e1f00 -.set CYFLD_BLE_BLELL_PRIV_1_2__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_PRIV_1_2__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_DLE__OFFSET, 0x00000001 -.set CYFLD_BLE_BLELL_DLE__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_WL_READ_AS_MEM__OFFSET, 0x00000002 -.set CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__OFFSET, 0x00000003 -.set CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__OFFSET, 0x00000004 -.set CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET, 0x00000005 -.set CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET, 0x00000008 -.set CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET, 0x0000000a -.set CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET, 0x0000000b -.set CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET, 0x0000000c -.set CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__OFFSET, 0x0000000d -.set CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__OFFSET, 0x0000000e -.set CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__OFFSET, 0x0000000f -.set CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE, 0x00000001 -.set CYREG_BLE_BLELL_DEV_PA_ADDR_L, 0x402e1f04 -.set CYFLD_BLE_BLELL_DEV_PA_ADDR_L__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_DEV_PA_ADDR_L__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_DEV_PA_ADDR_M, 0x402e1f08 -.set CYFLD_BLE_BLELL_DEV_PA_ADDR_M__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_DEV_PA_ADDR_M__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_DEV_PA_ADDR_H, 0x402e1f0c -.set CYFLD_BLE_BLELL_DEV_PA_ADDR_H__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_DEV_PA_ADDR_H__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE0, 0x402e1f10 -.set CYFLD_BLE_BLELL_VALID_ENTRY__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_VALID_ENTRY__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET, 0x00000001 -.set CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET, 0x00000002 -.set CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_WHITELISTED_PEER__OFFSET, 0x00000003 -.set CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET, 0x00000004 -.set CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET, 0x00000005 -.set CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET, 0x00000006 -.set CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET, 0x00000007 -.set CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET, 0x00000008 -.set CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE, 0x00000001 -.set CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET, 0x00000009 -.set CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE, 0x00000001 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE1, 0x402e1f14 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE2, 0x402e1f18 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE3, 0x402e1f1c -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE4, 0x402e1f20 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE5, 0x402e1f24 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE6, 0x402e1f28 -.set CYREG_BLE_BLELL_RSLV_LIST_ENABLE7, 0x402e1f2c -.set CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR, 0x402e2000 -.set CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR, 0x402e2060 -.set CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR, 0x402e20c0 -.set CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR, 0x402e2120 -.set CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR, 0x402e2200 -.set CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE, 0x402e2800 -.set CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__SIZE, 0x00000010 -.set CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE, 0x402e3000 -.set CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__OFFSET, 0x00000000 -.set CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__SIZE, 0x00000010 .set CYDEV_BLE_BLESS_BASE, 0x402ef000 .set CYDEV_BLE_BLESS_SIZE, 0x00001000 .set CYREG_BLE_BLESS_WCO_CONFIG, 0x402ef000 @@ -9017,8 +8093,6 @@ .set CYREG_BLE_BLESS_LF_CLK_CTRL, 0x402ef074 .set CYFLD_BLE_BLESS_DISABLE_LF_CLK__OFFSET, 0x00000000 .set CYFLD_BLE_BLESS_DISABLE_LF_CLK__SIZE, 0x00000001 -.set CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__OFFSET, 0x0000001d -.set CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__SIZE, 0x00000003 .set CYREG_BLE_BLESS_WCO_TRIM, 0x402eff00 .set CYFLD_BLE_BLESS_XGM__OFFSET, 0x00000000 .set CYFLD_BLE_BLESS_XGM__SIZE, 0x00000003 @@ -9914,8 +8988,8 @@ .set CYREG_ROMTABLE_CID1, 0xf0000ff4 .set CYREG_ROMTABLE_CID2, 0xf0000ff8 .set CYREG_ROMTABLE_CID3, 0xf0000ffc -.set CYDEV_FLS_SECTOR_SIZE, 0x00020000 -.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000080 .set CYREG_SFLASH_PROT_ROW00, CYREG_SFLASH_PROT_ROW0 .set CYREG_SFLASH_PROT_ROW01, CYREG_SFLASH_PROT_ROW1 .set CYREG_SFLASH_PROT_ROW02, CYREG_SFLASH_PROT_ROW2 diff --git a/BLE.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc b/BLE.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc index 4287bbb..7d00d02 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc +++ b/BLE.cydsn/Generated_Source/PSoC4/cydeviceiar_trm.inc @@ -14,11 +14,11 @@ ;------------------------------------------------------------------------------- #define CYDEV_FLASH_BASE 0x00000000 -#define CYDEV_FLASH_SIZE 0x00040000 +#define CYDEV_FLASH_SIZE 0x00020000 #define CYREG_FLASH_DATA_MBASE 0x00000000 -#define CYREG_FLASH_DATA_MSIZE 0x00040000 +#define CYREG_FLASH_DATA_MSIZE 0x00020000 #define CYDEV_SFLASH_BASE 0x0ffff000 -#define CYDEV_SFLASH_SIZE 0x00001000 +#define CYDEV_SFLASH_SIZE 0x00000800 #define CYREG_SFLASH_PROT_ROW0 0x0ffff000 #define CYFLD_SFLASH_DATA8__OFFSET 0x00000000 #define CYFLD_SFLASH_DATA8__SIZE 0x00000008 @@ -85,102 +85,102 @@ #define CYREG_SFLASH_PROT_ROW61 0x0ffff03d #define CYREG_SFLASH_PROT_ROW62 0x0ffff03e #define CYREG_SFLASH_PROT_ROW63 0x0ffff03f -#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff0ff +#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07f #define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000 #define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002 #define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001 #define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000 #define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002 #define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003 -#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff100 -#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff101 -#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff102 -#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff103 -#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff104 -#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff105 -#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff106 -#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff107 -#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff108 -#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff109 -#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff10a -#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff10b -#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff10c -#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff10d -#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff10e -#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff10f -#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff110 -#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff111 -#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff112 -#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff113 -#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff114 -#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff115 -#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff116 -#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff117 -#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff118 -#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff119 -#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff11a -#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff11b -#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff11c -#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff11d -#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff11e -#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff11f -#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff120 -#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff121 -#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff122 -#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff123 -#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff124 -#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff125 -#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff126 -#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff127 -#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff128 -#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff129 -#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff12a -#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff12b -#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff12c -#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff12d -#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff12e -#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff12f -#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff130 -#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff131 -#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff132 -#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff133 -#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff134 -#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff135 -#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff136 -#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff137 -#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff138 -#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff139 -#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff13a -#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff13b -#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff13c -#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff13d -#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff13e -#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff13f -#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff140 -#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff141 -#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff142 -#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff143 -#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff144 -#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff145 -#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff146 -#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff147 -#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff148 -#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff149 -#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff14a -#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff14b -#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff14c -#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff14d -#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff14e -#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff14f -#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff150 -#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff151 -#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff152 -#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff153 -#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff154 -#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff155 -#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff156 -#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff157 -#define CYREG_SFLASH_BLESS_BB_BUMP2 0x0ffff158 +#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff080 +#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff081 +#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff082 +#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff083 +#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff084 +#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff085 +#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff086 +#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff087 +#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff088 +#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff089 +#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff08a +#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff08b +#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff08c +#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff08d +#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff08e +#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff08f +#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff090 +#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff091 +#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff092 +#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff093 +#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff094 +#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff095 +#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff096 +#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff097 +#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff098 +#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff099 +#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff09a +#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff09b +#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff09c +#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff09d +#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff09e +#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff09f +#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff0a0 +#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff0a1 +#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff0a2 +#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff0a3 +#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff0a4 +#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff0a5 +#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff0a6 +#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff0a7 +#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff0a8 +#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff0a9 +#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff0aa +#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff0ab +#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff0ac +#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff0ad +#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff0ae +#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff0af +#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff0b0 +#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff0b1 +#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff0b2 +#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff0b3 +#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff0b4 +#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff0b5 +#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff0b6 +#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff0b7 +#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff0b8 +#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff0b9 +#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff0ba +#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff0bb +#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff0bc +#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff0bd +#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff0be +#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff0bf +#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff0c0 +#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff0c1 +#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff0c2 +#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff0c3 +#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff0c4 +#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff0c5 +#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff0c6 +#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff0c7 +#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff0c8 +#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff0c9 +#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff0ca +#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff0cb +#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff0cc +#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff0cd +#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff0ce +#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff0cf +#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff0d0 +#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff0d1 +#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff0d2 +#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff0d3 +#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff0d4 +#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff0d5 +#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff0d6 +#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff0d7 +#define CYREG_SFLASH_BLESS_BB_BUMP2 0x0ffff0d8 #define CYFLD_SFLASH_V2I_RCAL__OFFSET 0x00000000 #define CYFLD_SFLASH_V2I_RCAL__SIZE 0x00000005 #define CYFLD_SFLASH_V2I__OFFSET 0x00000005 @@ -189,9 +189,9 @@ #define CYFLD_SFLASH_VBG_TRIM__SIZE 0x00000003 #define CYFLD_SFLASH_SY_IBIAS__OFFSET 0x0000000d #define CYFLD_SFLASH_SY_IBIAS__SIZE 0x00000003 -#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff158 -#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff159 -#define CYREG_SFLASH_BLESS_BB_XO 0x0ffff15a +#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff0d8 +#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff0d9 +#define CYREG_SFLASH_BLESS_BB_XO 0x0ffff0da #define CYFLD_SFLASH_DIS_XOCORE_SUPFILT__OFFSET 0x00000000 #define CYFLD_SFLASH_DIS_XOCORE_SUPFILT__SIZE 0x00000001 #define CYFLD_SFLASH_EN_RE_FASTSTART__OFFSET 0x00000001 @@ -212,10 +212,10 @@ #define CYFLD_SFLASH_CTRL_RPREF__SIZE 0x00000002 #define CYFLD_SFLASH_rev_bb_xo__OFFSET 0x0000000f #define CYFLD_SFLASH_rev_bb_xo__SIZE 0x00000001 -#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff15a -#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff15b -#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff15c -#define CYREG_SFLASH_BLESS_SY_BUMP1 0x0ffff15c +#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff0da +#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff0db +#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff0dc +#define CYREG_SFLASH_BLESS_SY_BUMP1 0x0ffff0dc #define CYFLD_SFLASH_VCO__OFFSET 0x00000000 #define CYFLD_SFLASH_VCO__SIZE 0x00000004 #define CYFLD_SFLASH_LOFB_POWERSAVE__OFFSET 0x00000004 @@ -228,9 +228,9 @@ #define CYFLD_SFLASH_LOPATH__SIZE 0x00000004 #define CYFLD_SFLASH_PDCPLPF__OFFSET 0x0000000c #define CYFLD_SFLASH_PDCPLPF__SIZE 0x00000004 -#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff15d -#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff15e -#define CYREG_SFLASH_BLESS_LDO 0x0ffff15e +#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff0dd +#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff0de +#define CYREG_SFLASH_BLESS_LDO 0x0ffff0de #define CYFLD_SFLASH_BUMP_BALUM_HF__OFFSET 0x00000000 #define CYFLD_SFLASH_BUMP_BALUM_HF__SIZE 0x00000003 #define CYFLD_SFLASH_BUMP_SY_VCO__OFFSET 0x00000003 @@ -243,161 +243,115 @@ #define CYFLD_SFLASH_BUMP_SY_FFFB__SIZE 0x00000003 #define CYFLD_SFLASH_REV_LDO__OFFSET 0x0000000c #define CYFLD_SFLASH_REV_LDO__SIZE 0x00000004 -#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff15f -#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff160 -#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff161 -#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff162 -#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff163 -#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff164 -#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff165 -#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff166 -#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff167 -#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff168 -#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff169 -#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff16a -#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff16b -#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff16c -#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff16d -#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff16e -#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff16f -#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff170 -#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff171 -#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff172 -#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff173 -#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff174 -#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff175 -#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff176 -#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff177 -#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff178 -#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff179 -#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff17a -#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff17b -#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff17c -#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff17d -#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff17e -#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff17f -#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff200 +#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff0df +#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff0e0 +#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff0e1 +#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff0e2 +#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff0e3 +#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4 +#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5 +#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6 +#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7 +#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8 +#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9 +#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0ea +#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0eb +#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ec +#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0ed +#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0ee +#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0ef +#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0 +#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1 +#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2 +#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3 +#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4 +#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5 +#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6 +#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7 +#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8 +#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9 +#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fa +#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fb +#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fc +#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fd +#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0fe +#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ff +#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff100 #define CYFLD_SFLASH_DATA32__OFFSET 0x00000000 #define CYFLD_SFLASH_DATA32__SIZE 0x00000020 -#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff204 -#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff208 -#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff20c -#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff210 -#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff214 -#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff218 -#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff21c -#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff220 -#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff224 -#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff228 -#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff22c -#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff230 -#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff234 -#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff238 -#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff23c -#define CYREG_SFLASH_SILICON_ID 0x0ffff244 +#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff104 +#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff108 +#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff10c +#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff110 +#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff114 +#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff118 +#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff11c +#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff120 +#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff124 +#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128 +#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12c +#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130 +#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134 +#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138 +#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13c +#define CYREG_SFLASH_SILICON_ID 0x0ffff144 #define CYFLD_SFLASH_ID__OFFSET 0x00000000 #define CYFLD_SFLASH_ID__SIZE 0x00000010 -#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff250 +#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150 #define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000 #define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000a -#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff252 -#define CYREG_SFLASH_SWD_CONFIG 0x0ffff254 +#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152 +#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154 #define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000 #define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001 -#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 0x0ffff255 +#define CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 0x0ffff155 #define CYFLD_SFLASH_IDAC__OFFSET 0x00000000 #define CYFLD_SFLASH_IDAC__SIZE 0x00000005 #define CYFLD_SFLASH_SLOPE__OFFSET 0x00000005 #define CYFLD_SFLASH_SLOPE__SIZE 0x00000003 -#define CYREG_SFLASH_SWD_LISTEN 0x0ffff258 +#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158 #define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000 #define CYFLD_SFLASH_CYCLES__SIZE 0x00000020 -#define CYREG_SFLASH_FLASH_START 0x0ffff25c +#define CYREG_SFLASH_FLASH_START 0x0ffff15c #define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000 #define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020 -#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff260 +#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160 #define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000 #define CYFLD_SFLASH_TRIM8__SIZE 0x00000008 -#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff261 -#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff262 -#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff263 -#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff264 +#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161 +#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162 +#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163 +#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164 #define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000 #define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010 -#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff266 +#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166 #define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000 #define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010 -#define CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0 0x0ffff26c -#define CYFLD_SFLASH_FCAL_BIAS_SEL__OFFSET 0x00000000 -#define CYFLD_SFLASH_FCAL_BIAS_SEL__SIZE 0x00000002 -#define CYFLD_SFLASH_ACAP_BIAS_SEL__OFFSET 0x00000002 -#define CYFLD_SFLASH_ACAP_BIAS_SEL__SIZE 0x00000002 -#define CYFLD_SFLASH_ICP_XFACTOR__OFFSET 0x00000004 -#define CYFLD_SFLASH_ICP_XFACTOR__SIZE 0x00000002 -#define CYFLD_SFLASH_ICP_OFFSET__OFFSET 0x00000006 -#define CYFLD_SFLASH_ICP_OFFSET__SIZE 0x00000002 -#define CYFLD_SFLASH_CLKNC_MODE__OFFSET 0x00000008 -#define CYFLD_SFLASH_CLKNC_MODE__SIZE 0x00000001 -#define CYFLD_SFLASH_PUP_MON__OFFSET 0x00000009 -#define CYFLD_SFLASH_PUP_MON__SIZE 0x00000001 -#define CYFLD_SFLASH_VCTRL_PULLDN__OFFSET 0x0000000a -#define CYFLD_SFLASH_VCTRL_PULLDN__SIZE 0x00000001 -#define CYFLD_SFLASH_VMOD_PULLDN__OFFSET 0x0000000b -#define CYFLD_SFLASH_VMOD_PULLDN__SIZE 0x00000001 -#define CYFLD_SFLASH_RST_DLY__OFFSET 0x0000000c -#define CYFLD_SFLASH_RST_DLY__SIZE 0x00000002 -#define CYFLD_SFLASH_PDCP_OFFSET__OFFSET 0x0000000e -#define CYFLD_SFLASH_PDCP_OFFSET__SIZE 0x00000002 -#define CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1 0x0ffff26d -#define CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0 0x0ffff26e -#define CYFLD_SFLASH_LNA_IBIAS__OFFSET 0x00000000 -#define CYFLD_SFLASH_LNA_IBIAS__SIZE 0x00000002 -#define CYFLD_SFLASH_TIA_IBIAS__OFFSET 0x00000002 -#define CYFLD_SFLASH_TIA_IBIAS__SIZE 0x00000002 -#define CYFLD_SFLASH_CBPF_IBIAS__OFFSET 0x00000004 -#define CYFLD_SFLASH_CBPF_IBIAS__SIZE 0x00000002 -#define CYFLD_SFLASH_IF_CM_IBIAS__OFFSET 0x00000006 -#define CYFLD_SFLASH_IF_CM_IBIAS__SIZE 0x00000002 -#define CYFLD_SFLASH_CBPF_HIZ_ENABLE__OFFSET 0x00000008 -#define CYFLD_SFLASH_CBPF_HIZ_ENABLE__SIZE 0x00000001 -#define CYFLD_SFLASH_COMPLEX_DISABLE__OFFSET 0x00000009 -#define CYFLD_SFLASH_COMPLEX_DISABLE__SIZE 0x00000001 -#define CYFLD_SFLASH_SY_R2HIGHMODE__OFFSET 0x0000000a -#define CYFLD_SFLASH_SY_R2HIGHMODE__SIZE 0x00000001 -#define CYFLD_SFLASH_SY_HILINEARITYR2_MODE__OFFSET 0x0000000b -#define CYFLD_SFLASH_SY_HILINEARITYR2_MODE__SIZE 0x00000001 -#define CYFLD_SFLASH_SY_LOWKVAMODE__OFFSET 0x0000000c -#define CYFLD_SFLASH_SY_LOWKVAMODE__SIZE 0x00000001 -#define CYFLD_SFLASH_SY_LOWKVMMODE__OFFSET 0x0000000d -#define CYFLD_SFLASH_SY_LOWKVMMODE__SIZE 0x00000001 -#define CYFLD_SFLASH_REV_RX_BUMP2__OFFSET 0x0000000e -#define CYFLD_SFLASH_REV_RX_BUMP2__SIZE 0x00000002 -#define CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1 0x0ffff26f -#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff270 +#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170 #define CYFLD_SFLASH_KEY8__OFFSET 0x00000000 #define CYFLD_SFLASH_KEY8__SIZE 0x00000008 -#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff271 -#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff272 -#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff273 -#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff274 -#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff275 -#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff276 -#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff277 -#define CYREG_SFLASH_DIE_LOT0 0x0ffff278 +#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171 +#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172 +#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173 +#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174 +#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175 +#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176 +#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177 +#define CYREG_SFLASH_DIE_LOT0 0x0ffff178 #define CYFLD_SFLASH_LOT__OFFSET 0x00000000 #define CYFLD_SFLASH_LOT__SIZE 0x00000008 -#define CYREG_SFLASH_DIE_LOT1 0x0ffff279 -#define CYREG_SFLASH_DIE_LOT2 0x0ffff27a -#define CYREG_SFLASH_DIE_WAFER 0x0ffff27b +#define CYREG_SFLASH_DIE_LOT1 0x0ffff179 +#define CYREG_SFLASH_DIE_LOT2 0x0ffff17a +#define CYREG_SFLASH_DIE_WAFER 0x0ffff17b #define CYFLD_SFLASH_WAFER__OFFSET 0x00000000 #define CYFLD_SFLASH_WAFER__SIZE 0x00000008 -#define CYREG_SFLASH_DIE_X 0x0ffff27c +#define CYREG_SFLASH_DIE_X 0x0ffff17c #define CYFLD_SFLASH_X__OFFSET 0x00000000 #define CYFLD_SFLASH_X__SIZE 0x00000008 -#define CYREG_SFLASH_DIE_Y 0x0ffff27d +#define CYREG_SFLASH_DIE_Y 0x0ffff17d #define CYFLD_SFLASH_Y__OFFSET 0x00000000 #define CYFLD_SFLASH_Y__SIZE 0x00000008 -#define CYREG_SFLASH_DIE_SORT 0x0ffff27e +#define CYREG_SFLASH_DIE_SORT 0x0ffff17e #define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000 #define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001 #define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001 @@ -410,1392 +364,880 @@ #define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001 #define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005 #define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001 -#define CYREG_SFLASH_DIE_MINOR 0x0ffff27f +#define CYREG_SFLASH_DIE_MINOR 0x0ffff17f #define CYFLD_SFLASH_MINOR__OFFSET 0x00000000 #define CYFLD_SFLASH_MINOR__SIZE 0x00000008 -#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff33e +#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff1be #define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000 #define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008 -#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff33f -#define CYREG_SFLASH_IMO_MAXF0 0x0ffff340 +#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff1bf +#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0 #define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000 #define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006 -#define CYREG_SFLASH_IMO_ABS0 0x0ffff341 +#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1 #define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000 #define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006 -#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff342 +#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2 #define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000 #define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006 -#define CYREG_SFLASH_IMO_MAXF1 0x0ffff343 -#define CYREG_SFLASH_IMO_ABS1 0x0ffff344 -#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff345 -#define CYREG_SFLASH_IMO_MAXF2 0x0ffff346 -#define CYREG_SFLASH_IMO_ABS2 0x0ffff347 -#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff348 -#define CYREG_SFLASH_IMO_MAXF3 0x0ffff349 -#define CYREG_SFLASH_IMO_ABS3 0x0ffff34a -#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff34b -#define CYREG_SFLASH_IMO_ABS4 0x0ffff34c -#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff34d -#define CYREG_SFLASH_IMO_TRIM0 0x0ffff350 +#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3 +#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4 +#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5 +#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6 +#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7 +#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8 +#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9 +#define CYREG_SFLASH_IMO_ABS3 0x0ffff1ca +#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cb +#define CYREG_SFLASH_IMO_ABS4 0x0ffff1cc +#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cd +#define CYREG_SFLASH_IMO_TRIM0 0x0ffff1d0 #define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000 #define CYFLD_SFLASH_OFFSET__SIZE 0x00000008 -#define CYREG_SFLASH_IMO_TRIM1 0x0ffff351 -#define CYREG_SFLASH_IMO_TRIM2 0x0ffff352 -#define CYREG_SFLASH_IMO_TRIM3 0x0ffff353 -#define CYREG_SFLASH_IMO_TRIM4 0x0ffff354 -#define CYREG_SFLASH_IMO_TRIM5 0x0ffff355 -#define CYREG_SFLASH_IMO_TRIM6 0x0ffff356 -#define CYREG_SFLASH_IMO_TRIM7 0x0ffff357 -#define CYREG_SFLASH_IMO_TRIM8 0x0ffff358 -#define CYREG_SFLASH_IMO_TRIM9 0x0ffff359 -#define CYREG_SFLASH_IMO_TRIM10 0x0ffff35a -#define CYREG_SFLASH_IMO_TRIM11 0x0ffff35b -#define CYREG_SFLASH_IMO_TRIM12 0x0ffff35c -#define CYREG_SFLASH_IMO_TRIM13 0x0ffff35d -#define CYREG_SFLASH_IMO_TRIM14 0x0ffff35e -#define CYREG_SFLASH_IMO_TRIM15 0x0ffff35f -#define CYREG_SFLASH_IMO_TRIM16 0x0ffff360 -#define CYREG_SFLASH_IMO_TRIM17 0x0ffff361 -#define CYREG_SFLASH_IMO_TRIM18 0x0ffff362 -#define CYREG_SFLASH_IMO_TRIM19 0x0ffff363 -#define CYREG_SFLASH_IMO_TRIM20 0x0ffff364 -#define CYREG_SFLASH_IMO_TRIM21 0x0ffff365 -#define CYREG_SFLASH_IMO_TRIM22 0x0ffff366 -#define CYREG_SFLASH_IMO_TRIM23 0x0ffff367 -#define CYREG_SFLASH_IMO_TRIM24 0x0ffff368 -#define CYREG_SFLASH_IMO_TRIM25 0x0ffff369 -#define CYREG_SFLASH_IMO_TRIM26 0x0ffff36a -#define CYREG_SFLASH_IMO_TRIM27 0x0ffff36b -#define CYREG_SFLASH_IMO_TRIM28 0x0ffff36c -#define CYREG_SFLASH_IMO_TRIM29 0x0ffff36d -#define CYREG_SFLASH_IMO_TRIM30 0x0ffff36e -#define CYREG_SFLASH_IMO_TRIM31 0x0ffff36f -#define CYREG_SFLASH_IMO_TRIM32 0x0ffff370 -#define CYREG_SFLASH_IMO_TRIM33 0x0ffff371 -#define CYREG_SFLASH_IMO_TRIM34 0x0ffff372 -#define CYREG_SFLASH_IMO_TRIM35 0x0ffff373 -#define CYREG_SFLASH_IMO_TRIM36 0x0ffff374 -#define CYREG_SFLASH_IMO_TRIM37 0x0ffff375 -#define CYREG_SFLASH_IMO_TRIM38 0x0ffff376 -#define CYREG_SFLASH_IMO_TRIM39 0x0ffff377 -#define CYREG_SFLASH_IMO_TRIM40 0x0ffff378 -#define CYREG_SFLASH_IMO_TRIM41 0x0ffff379 -#define CYREG_SFLASH_IMO_TRIM42 0x0ffff37a -#define CYREG_SFLASH_IMO_TRIM43 0x0ffff37b -#define CYREG_SFLASH_IMO_TRIM44 0x0ffff37c -#define CYREG_SFLASH_IMO_TRIM45 0x0ffff37d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff400 +#define CYREG_SFLASH_IMO_TRIM1 0x0ffff1d1 +#define CYREG_SFLASH_IMO_TRIM2 0x0ffff1d2 +#define CYREG_SFLASH_IMO_TRIM3 0x0ffff1d3 +#define CYREG_SFLASH_IMO_TRIM4 0x0ffff1d4 +#define CYREG_SFLASH_IMO_TRIM5 0x0ffff1d5 +#define CYREG_SFLASH_IMO_TRIM6 0x0ffff1d6 +#define CYREG_SFLASH_IMO_TRIM7 0x0ffff1d7 +#define CYREG_SFLASH_IMO_TRIM8 0x0ffff1d8 +#define CYREG_SFLASH_IMO_TRIM9 0x0ffff1d9 +#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1da +#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1db +#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dc +#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1dd +#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1de +#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1df +#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0 +#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1 +#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2 +#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3 +#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4 +#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5 +#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6 +#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7 +#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8 +#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9 +#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1ea +#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1eb +#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ec +#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1ed +#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1ee +#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1ef +#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0 +#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1 +#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2 +#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3 +#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4 +#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5 +#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6 +#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7 +#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8 +#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9 +#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fa +#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fb +#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fc +#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff200 #define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000 #define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff401 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff402 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff403 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff404 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff405 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff406 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff407 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff408 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff409 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff40a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff40b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff40c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff40d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff40e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff40f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff410 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff411 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff412 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff413 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff414 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff415 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff416 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff417 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff418 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff419 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff41a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff41b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff41c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff41d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff41e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff41f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff420 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff421 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff422 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff423 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff424 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff425 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff426 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff427 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff428 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff429 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff42a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff42b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff42c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff42d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff42e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff42f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff430 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff431 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff432 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff433 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff434 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff435 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff436 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff437 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff438 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff439 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff43a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff43b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff43c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff43d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff43e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff43f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff440 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff441 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff442 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff443 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff444 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff445 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff446 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff447 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff448 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff449 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff44a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff44b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff44c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff44d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff44e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff44f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff450 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff451 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff452 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff453 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff454 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff455 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff456 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff457 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff458 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff459 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff45a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff45b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff45c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff45d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff45e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff45f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff460 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff461 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff462 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff463 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff464 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff465 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff466 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff467 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff468 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff469 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff46a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff46b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff46c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff46d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff46e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff46f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff470 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff471 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff472 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff473 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff474 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff475 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff476 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff477 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff478 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff479 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff47a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff47b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff47c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff47d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff47e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff47f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff480 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff481 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff482 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff483 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff484 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff485 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff486 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff487 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff488 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff489 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff48a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff48b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff48c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff48d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff48e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff48f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff490 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff491 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff492 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff493 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff494 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff495 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff496 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff497 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff498 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff499 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff49a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff49b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff49c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff49d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff49e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff49f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff4a0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff4a1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff4a2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff4a3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff4a4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff4a5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff4a6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff4a7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff4a8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff4a9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff4aa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff4ab -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff4ac -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff4ad -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff4ae -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff4af -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff4b0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff4b1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff4b2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff4b3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff4b4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff4b5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff4b6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff4b7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff4b8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff4b9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff4ba -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff4bb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff4bc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff4bd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff4be -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff4bf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff4c0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff4c1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff4c2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff4c3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff4c4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff4c5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff4c6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff4c7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff4c8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff4c9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff4ca -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff4cb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff4cc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff4cd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff4ce -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff4cf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff4d0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff4d1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff4d2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff4d3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff4d4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff4d5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff4d6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff4d7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff4d8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff4d9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff4da -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff4db -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff4dc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff4dd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff4de -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff4df -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff4e0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff4e1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff4e2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff4e3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff4e4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff4e5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff4e6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff4e7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff4e8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff4e9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff4ea -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff4eb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff4ec -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff4ed -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff4ee -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff4ef -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff4f0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff4f1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff4f2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff4f3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff4f4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff4f5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff4f6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff4f7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff4f8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff4f9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff4fa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff4fb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff4fc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff4fd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff4fe -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff4ff -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff500 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff501 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff502 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff503 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff504 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff505 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff506 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff507 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff508 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff509 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff50a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff50b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff50c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff50d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff50e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff50f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff510 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff511 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff512 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff513 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff514 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff515 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff516 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff517 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff518 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff519 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff51a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff51b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff51c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff51d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff51e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff51f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff520 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff521 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff522 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff523 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff524 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff525 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff526 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff527 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff528 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff529 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff52a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff52b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff52c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff52d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff52e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff52f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff530 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff531 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff532 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff533 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff534 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff535 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff536 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff537 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff538 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff539 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff53a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff53b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff53c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff53d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff53e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff53f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff540 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff541 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff542 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff543 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff544 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff545 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff546 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff547 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff548 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff549 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff54a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff54b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff54c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff54d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff54e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff54f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff550 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff551 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff552 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff553 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff554 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff555 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff556 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff557 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff558 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff559 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff55a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff55b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff55c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff55d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff55e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff55f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff560 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff561 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff562 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff563 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff564 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff565 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff566 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff567 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff568 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff569 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff56a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff56b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff56c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff56d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff56e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff56f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff570 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff571 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff572 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff573 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff574 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff575 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff576 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff577 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff578 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff579 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff57a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff57b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff57c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff57d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff57e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff57f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff580 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff581 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff582 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff583 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff584 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff585 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff586 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff587 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff588 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff589 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff58a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff58b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff58c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff58d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff58e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff58f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff590 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff591 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff592 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff593 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff594 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff595 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff596 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff597 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff598 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff599 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff59a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff59b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff59c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff59d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff59e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff59f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff5a0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff5a1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff5a2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff5a3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff5a4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff5a5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff5a6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff5a7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff5a8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff5a9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff5aa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff5ab -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff5ac -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff5ad -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff5ae -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff5af -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff5b0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff5b1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff5b2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff5b3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff5b4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff5b5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff5b6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff5b7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff5b8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff5b9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff5ba -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff5bb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff5bc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff5bd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff5be -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff5bf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff5c0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff5c1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff5c2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff5c3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff5c4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff5c5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff5c6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff5c7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff5c8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff5c9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff5ca -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff5cb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff5cc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff5cd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff5ce -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff5cf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff5d0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff5d1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff5d2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff5d3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff5d4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff5d5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff5d6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff5d7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff5d8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff5d9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff5da -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff5db -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff5dc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff5dd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff5de -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff5df -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff5e0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff5e1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff5e2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff5e3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff5e4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff5e5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff5e6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff5e7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff5e8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff5e9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff5ea -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff5eb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff5ec -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff5ed -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff5ee -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff5ef -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff5f0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff5f1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff5f2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff5f3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff5f4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff5f5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff5f6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff5f7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff5f8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff5f9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff5fa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff5fb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff5fc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff5fd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff5fe -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff5ff -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH512 0x0ffff600 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH513 0x0ffff601 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH514 0x0ffff602 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH515 0x0ffff603 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH516 0x0ffff604 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH517 0x0ffff605 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH518 0x0ffff606 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH519 0x0ffff607 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH520 0x0ffff608 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH521 0x0ffff609 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH522 0x0ffff60a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH523 0x0ffff60b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH524 0x0ffff60c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH525 0x0ffff60d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH526 0x0ffff60e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH527 0x0ffff60f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH528 0x0ffff610 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH529 0x0ffff611 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH530 0x0ffff612 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH531 0x0ffff613 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH532 0x0ffff614 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH533 0x0ffff615 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH534 0x0ffff616 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH535 0x0ffff617 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH536 0x0ffff618 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH537 0x0ffff619 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH538 0x0ffff61a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH539 0x0ffff61b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH540 0x0ffff61c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH541 0x0ffff61d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH542 0x0ffff61e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH543 0x0ffff61f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH544 0x0ffff620 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH545 0x0ffff621 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH546 0x0ffff622 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH547 0x0ffff623 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH548 0x0ffff624 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH549 0x0ffff625 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH550 0x0ffff626 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH551 0x0ffff627 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH552 0x0ffff628 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH553 0x0ffff629 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH554 0x0ffff62a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH555 0x0ffff62b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH556 0x0ffff62c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH557 0x0ffff62d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH558 0x0ffff62e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH559 0x0ffff62f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH560 0x0ffff630 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH561 0x0ffff631 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH562 0x0ffff632 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH563 0x0ffff633 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH564 0x0ffff634 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH565 0x0ffff635 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH566 0x0ffff636 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH567 0x0ffff637 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH568 0x0ffff638 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH569 0x0ffff639 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH570 0x0ffff63a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH571 0x0ffff63b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH572 0x0ffff63c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH573 0x0ffff63d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH574 0x0ffff63e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH575 0x0ffff63f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH576 0x0ffff640 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH577 0x0ffff641 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH578 0x0ffff642 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH579 0x0ffff643 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH580 0x0ffff644 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH581 0x0ffff645 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH582 0x0ffff646 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH583 0x0ffff647 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH584 0x0ffff648 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH585 0x0ffff649 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH586 0x0ffff64a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH587 0x0ffff64b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH588 0x0ffff64c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH589 0x0ffff64d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH590 0x0ffff64e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH591 0x0ffff64f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH592 0x0ffff650 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH593 0x0ffff651 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH594 0x0ffff652 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH595 0x0ffff653 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH596 0x0ffff654 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH597 0x0ffff655 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH598 0x0ffff656 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH599 0x0ffff657 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH600 0x0ffff658 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH601 0x0ffff659 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH602 0x0ffff65a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH603 0x0ffff65b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH604 0x0ffff65c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH605 0x0ffff65d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH606 0x0ffff65e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH607 0x0ffff65f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH608 0x0ffff660 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH609 0x0ffff661 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH610 0x0ffff662 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH611 0x0ffff663 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH612 0x0ffff664 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH613 0x0ffff665 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH614 0x0ffff666 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH615 0x0ffff667 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH616 0x0ffff668 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH617 0x0ffff669 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH618 0x0ffff66a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH619 0x0ffff66b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH620 0x0ffff66c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH621 0x0ffff66d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH622 0x0ffff66e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH623 0x0ffff66f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH624 0x0ffff670 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH625 0x0ffff671 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH626 0x0ffff672 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH627 0x0ffff673 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH628 0x0ffff674 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH629 0x0ffff675 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH630 0x0ffff676 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH631 0x0ffff677 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH632 0x0ffff678 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH633 0x0ffff679 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH634 0x0ffff67a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH635 0x0ffff67b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH636 0x0ffff67c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH637 0x0ffff67d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH638 0x0ffff67e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH639 0x0ffff67f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH640 0x0ffff680 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH641 0x0ffff681 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH642 0x0ffff682 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH643 0x0ffff683 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH644 0x0ffff684 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH645 0x0ffff685 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH646 0x0ffff686 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH647 0x0ffff687 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH648 0x0ffff688 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH649 0x0ffff689 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH650 0x0ffff68a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH651 0x0ffff68b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH652 0x0ffff68c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH653 0x0ffff68d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH654 0x0ffff68e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH655 0x0ffff68f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH656 0x0ffff690 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH657 0x0ffff691 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH658 0x0ffff692 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH659 0x0ffff693 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH660 0x0ffff694 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH661 0x0ffff695 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH662 0x0ffff696 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH663 0x0ffff697 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH664 0x0ffff698 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH665 0x0ffff699 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH666 0x0ffff69a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH667 0x0ffff69b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH668 0x0ffff69c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH669 0x0ffff69d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH670 0x0ffff69e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH671 0x0ffff69f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH672 0x0ffff6a0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH673 0x0ffff6a1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH674 0x0ffff6a2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH675 0x0ffff6a3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH676 0x0ffff6a4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH677 0x0ffff6a5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH678 0x0ffff6a6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH679 0x0ffff6a7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH680 0x0ffff6a8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH681 0x0ffff6a9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH682 0x0ffff6aa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH683 0x0ffff6ab -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH684 0x0ffff6ac -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH685 0x0ffff6ad -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH686 0x0ffff6ae -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH687 0x0ffff6af -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH688 0x0ffff6b0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH689 0x0ffff6b1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH690 0x0ffff6b2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH691 0x0ffff6b3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH692 0x0ffff6b4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH693 0x0ffff6b5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH694 0x0ffff6b6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH695 0x0ffff6b7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH696 0x0ffff6b8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH697 0x0ffff6b9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH698 0x0ffff6ba -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH699 0x0ffff6bb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH700 0x0ffff6bc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH701 0x0ffff6bd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH702 0x0ffff6be -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH703 0x0ffff6bf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH704 0x0ffff6c0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH705 0x0ffff6c1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH706 0x0ffff6c2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH707 0x0ffff6c3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH708 0x0ffff6c4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH709 0x0ffff6c5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH710 0x0ffff6c6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH711 0x0ffff6c7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH712 0x0ffff6c8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH713 0x0ffff6c9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH714 0x0ffff6ca -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH715 0x0ffff6cb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH716 0x0ffff6cc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH717 0x0ffff6cd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH718 0x0ffff6ce -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH719 0x0ffff6cf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH720 0x0ffff6d0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH721 0x0ffff6d1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH722 0x0ffff6d2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH723 0x0ffff6d3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH724 0x0ffff6d4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH725 0x0ffff6d5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH726 0x0ffff6d6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH727 0x0ffff6d7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH728 0x0ffff6d8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH729 0x0ffff6d9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH730 0x0ffff6da -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH731 0x0ffff6db -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH732 0x0ffff6dc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH733 0x0ffff6dd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH734 0x0ffff6de -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH735 0x0ffff6df -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH736 0x0ffff6e0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH737 0x0ffff6e1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH738 0x0ffff6e2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH739 0x0ffff6e3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH740 0x0ffff6e4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH741 0x0ffff6e5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH742 0x0ffff6e6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH743 0x0ffff6e7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH744 0x0ffff6e8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH745 0x0ffff6e9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH746 0x0ffff6ea -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH747 0x0ffff6eb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH748 0x0ffff6ec -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH749 0x0ffff6ed -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH750 0x0ffff6ee -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH751 0x0ffff6ef -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH752 0x0ffff6f0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH753 0x0ffff6f1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH754 0x0ffff6f2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH755 0x0ffff6f3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH756 0x0ffff6f4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH757 0x0ffff6f5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH758 0x0ffff6f6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH759 0x0ffff6f7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH760 0x0ffff6f8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH761 0x0ffff6f9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH762 0x0ffff6fa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH763 0x0ffff6fb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH764 0x0ffff6fc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH765 0x0ffff6fd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH766 0x0ffff6fe -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH767 0x0ffff6ff -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH768 0x0ffff700 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH769 0x0ffff701 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH770 0x0ffff702 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH771 0x0ffff703 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH772 0x0ffff704 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH773 0x0ffff705 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH774 0x0ffff706 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH775 0x0ffff707 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH776 0x0ffff708 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH777 0x0ffff709 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH778 0x0ffff70a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH779 0x0ffff70b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH780 0x0ffff70c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH781 0x0ffff70d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH782 0x0ffff70e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH783 0x0ffff70f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH784 0x0ffff710 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH785 0x0ffff711 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH786 0x0ffff712 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH787 0x0ffff713 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH788 0x0ffff714 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH789 0x0ffff715 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH790 0x0ffff716 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH791 0x0ffff717 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH792 0x0ffff718 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH793 0x0ffff719 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH794 0x0ffff71a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH795 0x0ffff71b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH796 0x0ffff71c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH797 0x0ffff71d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH798 0x0ffff71e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH799 0x0ffff71f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH800 0x0ffff720 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH801 0x0ffff721 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH802 0x0ffff722 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH803 0x0ffff723 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH804 0x0ffff724 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH805 0x0ffff725 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH806 0x0ffff726 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH807 0x0ffff727 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH808 0x0ffff728 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH809 0x0ffff729 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH810 0x0ffff72a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH811 0x0ffff72b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH812 0x0ffff72c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH813 0x0ffff72d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH814 0x0ffff72e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH815 0x0ffff72f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH816 0x0ffff730 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH817 0x0ffff731 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH818 0x0ffff732 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH819 0x0ffff733 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH820 0x0ffff734 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH821 0x0ffff735 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH822 0x0ffff736 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH823 0x0ffff737 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH824 0x0ffff738 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH825 0x0ffff739 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH826 0x0ffff73a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH827 0x0ffff73b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH828 0x0ffff73c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH829 0x0ffff73d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH830 0x0ffff73e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH831 0x0ffff73f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH832 0x0ffff740 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH833 0x0ffff741 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH834 0x0ffff742 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH835 0x0ffff743 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH836 0x0ffff744 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH837 0x0ffff745 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH838 0x0ffff746 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH839 0x0ffff747 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH840 0x0ffff748 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH841 0x0ffff749 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH842 0x0ffff74a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH843 0x0ffff74b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH844 0x0ffff74c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH845 0x0ffff74d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH846 0x0ffff74e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH847 0x0ffff74f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH848 0x0ffff750 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH849 0x0ffff751 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH850 0x0ffff752 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH851 0x0ffff753 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH852 0x0ffff754 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH853 0x0ffff755 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH854 0x0ffff756 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH855 0x0ffff757 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH856 0x0ffff758 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH857 0x0ffff759 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH858 0x0ffff75a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH859 0x0ffff75b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH860 0x0ffff75c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH861 0x0ffff75d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH862 0x0ffff75e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH863 0x0ffff75f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH864 0x0ffff760 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH865 0x0ffff761 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH866 0x0ffff762 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH867 0x0ffff763 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH868 0x0ffff764 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH869 0x0ffff765 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH870 0x0ffff766 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH871 0x0ffff767 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH872 0x0ffff768 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH873 0x0ffff769 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH874 0x0ffff76a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH875 0x0ffff76b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH876 0x0ffff76c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH877 0x0ffff76d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH878 0x0ffff76e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH879 0x0ffff76f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH880 0x0ffff770 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH881 0x0ffff771 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH882 0x0ffff772 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH883 0x0ffff773 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH884 0x0ffff774 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH885 0x0ffff775 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH886 0x0ffff776 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH887 0x0ffff777 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH888 0x0ffff778 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH889 0x0ffff779 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH890 0x0ffff77a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH891 0x0ffff77b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH892 0x0ffff77c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH893 0x0ffff77d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH894 0x0ffff77e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH895 0x0ffff77f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH896 0x0ffff780 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH897 0x0ffff781 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH898 0x0ffff782 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH899 0x0ffff783 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH900 0x0ffff784 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH901 0x0ffff785 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH902 0x0ffff786 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH903 0x0ffff787 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH904 0x0ffff788 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH905 0x0ffff789 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH906 0x0ffff78a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH907 0x0ffff78b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH908 0x0ffff78c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH909 0x0ffff78d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH910 0x0ffff78e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH911 0x0ffff78f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH912 0x0ffff790 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH913 0x0ffff791 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH914 0x0ffff792 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH915 0x0ffff793 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH916 0x0ffff794 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH917 0x0ffff795 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH918 0x0ffff796 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH919 0x0ffff797 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH920 0x0ffff798 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH921 0x0ffff799 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH922 0x0ffff79a -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH923 0x0ffff79b -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH924 0x0ffff79c -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH925 0x0ffff79d -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH926 0x0ffff79e -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH927 0x0ffff79f -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH928 0x0ffff7a0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH929 0x0ffff7a1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH930 0x0ffff7a2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH931 0x0ffff7a3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH932 0x0ffff7a4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH933 0x0ffff7a5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH934 0x0ffff7a6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH935 0x0ffff7a7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH936 0x0ffff7a8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH937 0x0ffff7a9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH938 0x0ffff7aa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH939 0x0ffff7ab -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH940 0x0ffff7ac -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH941 0x0ffff7ad -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH942 0x0ffff7ae -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH943 0x0ffff7af -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH944 0x0ffff7b0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH945 0x0ffff7b1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH946 0x0ffff7b2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH947 0x0ffff7b3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH948 0x0ffff7b4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH949 0x0ffff7b5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH950 0x0ffff7b6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH951 0x0ffff7b7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH952 0x0ffff7b8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH953 0x0ffff7b9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH954 0x0ffff7ba -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH955 0x0ffff7bb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH956 0x0ffff7bc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH957 0x0ffff7bd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH958 0x0ffff7be -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH959 0x0ffff7bf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH960 0x0ffff7c0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH961 0x0ffff7c1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH962 0x0ffff7c2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH963 0x0ffff7c3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH964 0x0ffff7c4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH965 0x0ffff7c5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH966 0x0ffff7c6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH967 0x0ffff7c7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH968 0x0ffff7c8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH969 0x0ffff7c9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH970 0x0ffff7ca -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH971 0x0ffff7cb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH972 0x0ffff7cc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH973 0x0ffff7cd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH974 0x0ffff7ce -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH975 0x0ffff7cf -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH976 0x0ffff7d0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH977 0x0ffff7d1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH978 0x0ffff7d2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH979 0x0ffff7d3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH980 0x0ffff7d4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH981 0x0ffff7d5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH982 0x0ffff7d6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH983 0x0ffff7d7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH984 0x0ffff7d8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH985 0x0ffff7d9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH986 0x0ffff7da -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH987 0x0ffff7db -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH988 0x0ffff7dc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH989 0x0ffff7dd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH990 0x0ffff7de -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH991 0x0ffff7df -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH992 0x0ffff7e0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH993 0x0ffff7e1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH994 0x0ffff7e2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH995 0x0ffff7e3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH996 0x0ffff7e4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH997 0x0ffff7e5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH998 0x0ffff7e6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH999 0x0ffff7e7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 0x0ffff7e8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 0x0ffff7e9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 0x0ffff7ea -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 0x0ffff7eb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 0x0ffff7ec -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 0x0ffff7ed -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 0x0ffff7ee -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 0x0ffff7ef -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 0x0ffff7f0 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 0x0ffff7f1 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 0x0ffff7f2 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 0x0ffff7f3 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 0x0ffff7f4 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 0x0ffff7f5 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 0x0ffff7f6 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 0x0ffff7f7 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 0x0ffff7f8 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 0x0ffff7f9 -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 0x0ffff7fa -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 0x0ffff7fb -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 0x0ffff7fc -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 0x0ffff7fd -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 0x0ffff7fe -#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 0x0ffff7ff -#define CYREG_SFLASH_ALT_PROT_ROW0 0x0ffff800 -#define CYREG_SFLASH_ALT_PROT_ROW1 0x0ffff801 -#define CYREG_SFLASH_ALT_PROT_ROW2 0x0ffff802 -#define CYREG_SFLASH_ALT_PROT_ROW3 0x0ffff803 -#define CYREG_SFLASH_ALT_PROT_ROW4 0x0ffff804 -#define CYREG_SFLASH_ALT_PROT_ROW5 0x0ffff805 -#define CYREG_SFLASH_ALT_PROT_ROW6 0x0ffff806 -#define CYREG_SFLASH_ALT_PROT_ROW7 0x0ffff807 -#define CYREG_SFLASH_ALT_PROT_ROW8 0x0ffff808 -#define CYREG_SFLASH_ALT_PROT_ROW9 0x0ffff809 -#define CYREG_SFLASH_ALT_PROT_ROW10 0x0ffff80a -#define CYREG_SFLASH_ALT_PROT_ROW11 0x0ffff80b -#define CYREG_SFLASH_ALT_PROT_ROW12 0x0ffff80c -#define CYREG_SFLASH_ALT_PROT_ROW13 0x0ffff80d -#define CYREG_SFLASH_ALT_PROT_ROW14 0x0ffff80e -#define CYREG_SFLASH_ALT_PROT_ROW15 0x0ffff80f -#define CYREG_SFLASH_ALT_PROT_ROW16 0x0ffff810 -#define CYREG_SFLASH_ALT_PROT_ROW17 0x0ffff811 -#define CYREG_SFLASH_ALT_PROT_ROW18 0x0ffff812 -#define CYREG_SFLASH_ALT_PROT_ROW19 0x0ffff813 -#define CYREG_SFLASH_ALT_PROT_ROW20 0x0ffff814 -#define CYREG_SFLASH_ALT_PROT_ROW21 0x0ffff815 -#define CYREG_SFLASH_ALT_PROT_ROW22 0x0ffff816 -#define CYREG_SFLASH_ALT_PROT_ROW23 0x0ffff817 -#define CYREG_SFLASH_ALT_PROT_ROW24 0x0ffff818 -#define CYREG_SFLASH_ALT_PROT_ROW25 0x0ffff819 -#define CYREG_SFLASH_ALT_PROT_ROW26 0x0ffff81a -#define CYREG_SFLASH_ALT_PROT_ROW27 0x0ffff81b -#define CYREG_SFLASH_ALT_PROT_ROW28 0x0ffff81c -#define CYREG_SFLASH_ALT_PROT_ROW29 0x0ffff81d -#define CYREG_SFLASH_ALT_PROT_ROW30 0x0ffff81e -#define CYREG_SFLASH_ALT_PROT_ROW31 0x0ffff81f -#define CYREG_SFLASH_ALT_PROT_ROW32 0x0ffff820 -#define CYREG_SFLASH_ALT_PROT_ROW33 0x0ffff821 -#define CYREG_SFLASH_ALT_PROT_ROW34 0x0ffff822 -#define CYREG_SFLASH_ALT_PROT_ROW35 0x0ffff823 -#define CYREG_SFLASH_ALT_PROT_ROW36 0x0ffff824 -#define CYREG_SFLASH_ALT_PROT_ROW37 0x0ffff825 -#define CYREG_SFLASH_ALT_PROT_ROW38 0x0ffff826 -#define CYREG_SFLASH_ALT_PROT_ROW39 0x0ffff827 -#define CYREG_SFLASH_ALT_PROT_ROW40 0x0ffff828 -#define CYREG_SFLASH_ALT_PROT_ROW41 0x0ffff829 -#define CYREG_SFLASH_ALT_PROT_ROW42 0x0ffff82a -#define CYREG_SFLASH_ALT_PROT_ROW43 0x0ffff82b -#define CYREG_SFLASH_ALT_PROT_ROW44 0x0ffff82c -#define CYREG_SFLASH_ALT_PROT_ROW45 0x0ffff82d -#define CYREG_SFLASH_ALT_PROT_ROW46 0x0ffff82e -#define CYREG_SFLASH_ALT_PROT_ROW47 0x0ffff82f -#define CYREG_SFLASH_ALT_PROT_ROW48 0x0ffff830 -#define CYREG_SFLASH_ALT_PROT_ROW49 0x0ffff831 -#define CYREG_SFLASH_ALT_PROT_ROW50 0x0ffff832 -#define CYREG_SFLASH_ALT_PROT_ROW51 0x0ffff833 -#define CYREG_SFLASH_ALT_PROT_ROW52 0x0ffff834 -#define CYREG_SFLASH_ALT_PROT_ROW53 0x0ffff835 -#define CYREG_SFLASH_ALT_PROT_ROW54 0x0ffff836 -#define CYREG_SFLASH_ALT_PROT_ROW55 0x0ffff837 -#define CYREG_SFLASH_ALT_PROT_ROW56 0x0ffff838 -#define CYREG_SFLASH_ALT_PROT_ROW57 0x0ffff839 -#define CYREG_SFLASH_ALT_PROT_ROW58 0x0ffff83a -#define CYREG_SFLASH_ALT_PROT_ROW59 0x0ffff83b -#define CYREG_SFLASH_ALT_PROT_ROW60 0x0ffff83c -#define CYREG_SFLASH_ALT_PROT_ROW61 0x0ffff83d -#define CYREG_SFLASH_ALT_PROT_ROW62 0x0ffff83e -#define CYREG_SFLASH_ALT_PROT_ROW63 0x0ffff83f -#define CYREG_SFLASH_ALT_PROT_ROW64 0x0ffff840 -#define CYREG_SFLASH_ALT_PROT_ROW65 0x0ffff841 -#define CYREG_SFLASH_ALT_PROT_ROW66 0x0ffff842 -#define CYREG_SFLASH_ALT_PROT_ROW67 0x0ffff843 -#define CYREG_SFLASH_ALT_PROT_ROW68 0x0ffff844 -#define CYREG_SFLASH_ALT_PROT_ROW69 0x0ffff845 -#define CYREG_SFLASH_ALT_PROT_ROW70 0x0ffff846 -#define CYREG_SFLASH_ALT_PROT_ROW71 0x0ffff847 -#define CYREG_SFLASH_ALT_PROT_ROW72 0x0ffff848 -#define CYREG_SFLASH_ALT_PROT_ROW73 0x0ffff849 -#define CYREG_SFLASH_ALT_PROT_ROW74 0x0ffff84a -#define CYREG_SFLASH_ALT_PROT_ROW75 0x0ffff84b -#define CYREG_SFLASH_ALT_PROT_ROW76 0x0ffff84c -#define CYREG_SFLASH_ALT_PROT_ROW77 0x0ffff84d -#define CYREG_SFLASH_ALT_PROT_ROW78 0x0ffff84e -#define CYREG_SFLASH_ALT_PROT_ROW79 0x0ffff84f -#define CYREG_SFLASH_ALT_PROT_ROW80 0x0ffff850 -#define CYREG_SFLASH_ALT_PROT_ROW81 0x0ffff851 -#define CYREG_SFLASH_ALT_PROT_ROW82 0x0ffff852 -#define CYREG_SFLASH_ALT_PROT_ROW83 0x0ffff853 -#define CYREG_SFLASH_ALT_PROT_ROW84 0x0ffff854 -#define CYREG_SFLASH_ALT_PROT_ROW85 0x0ffff855 -#define CYREG_SFLASH_ALT_PROT_ROW86 0x0ffff856 -#define CYREG_SFLASH_ALT_PROT_ROW87 0x0ffff857 -#define CYREG_SFLASH_ALT_PROT_ROW88 0x0ffff858 -#define CYREG_SFLASH_ALT_PROT_ROW89 0x0ffff859 -#define CYREG_SFLASH_ALT_PROT_ROW90 0x0ffff85a -#define CYREG_SFLASH_ALT_PROT_ROW91 0x0ffff85b -#define CYREG_SFLASH_ALT_PROT_ROW92 0x0ffff85c -#define CYREG_SFLASH_ALT_PROT_ROW93 0x0ffff85d -#define CYREG_SFLASH_ALT_PROT_ROW94 0x0ffff85e -#define CYREG_SFLASH_ALT_PROT_ROW95 0x0ffff85f -#define CYREG_SFLASH_ALT_PROT_ROW96 0x0ffff860 -#define CYREG_SFLASH_ALT_PROT_ROW97 0x0ffff861 -#define CYREG_SFLASH_ALT_PROT_ROW98 0x0ffff862 -#define CYREG_SFLASH_ALT_PROT_ROW99 0x0ffff863 -#define CYREG_SFLASH_ALT_PROT_ROW100 0x0ffff864 -#define CYREG_SFLASH_ALT_PROT_ROW101 0x0ffff865 -#define CYREG_SFLASH_ALT_PROT_ROW102 0x0ffff866 -#define CYREG_SFLASH_ALT_PROT_ROW103 0x0ffff867 -#define CYREG_SFLASH_ALT_PROT_ROW104 0x0ffff868 -#define CYREG_SFLASH_ALT_PROT_ROW105 0x0ffff869 -#define CYREG_SFLASH_ALT_PROT_ROW106 0x0ffff86a -#define CYREG_SFLASH_ALT_PROT_ROW107 0x0ffff86b -#define CYREG_SFLASH_ALT_PROT_ROW108 0x0ffff86c -#define CYREG_SFLASH_ALT_PROT_ROW109 0x0ffff86d -#define CYREG_SFLASH_ALT_PROT_ROW110 0x0ffff86e -#define CYREG_SFLASH_ALT_PROT_ROW111 0x0ffff86f -#define CYREG_SFLASH_ALT_PROT_ROW112 0x0ffff870 -#define CYREG_SFLASH_ALT_PROT_ROW113 0x0ffff871 -#define CYREG_SFLASH_ALT_PROT_ROW114 0x0ffff872 -#define CYREG_SFLASH_ALT_PROT_ROW115 0x0ffff873 -#define CYREG_SFLASH_ALT_PROT_ROW116 0x0ffff874 -#define CYREG_SFLASH_ALT_PROT_ROW117 0x0ffff875 -#define CYREG_SFLASH_ALT_PROT_ROW118 0x0ffff876 -#define CYREG_SFLASH_ALT_PROT_ROW119 0x0ffff877 -#define CYREG_SFLASH_ALT_PROT_ROW120 0x0ffff878 -#define CYREG_SFLASH_ALT_PROT_ROW121 0x0ffff879 -#define CYREG_SFLASH_ALT_PROT_ROW122 0x0ffff87a -#define CYREG_SFLASH_ALT_PROT_ROW123 0x0ffff87b -#define CYREG_SFLASH_ALT_PROT_ROW124 0x0ffff87c -#define CYREG_SFLASH_ALT_PROT_ROW125 0x0ffff87d -#define CYREG_SFLASH_ALT_PROT_ROW126 0x0ffff87e -#define CYREG_SFLASH_ALT_PROT_ROW127 0x0ffff87f -#define CYREG_SFLASH_ALT_PROT_ROW128 0x0ffff880 -#define CYREG_SFLASH_ALT_PROT_ROW129 0x0ffff881 -#define CYREG_SFLASH_ALT_PROT_ROW130 0x0ffff882 -#define CYREG_SFLASH_ALT_PROT_ROW131 0x0ffff883 -#define CYREG_SFLASH_ALT_PROT_ROW132 0x0ffff884 -#define CYREG_SFLASH_ALT_PROT_ROW133 0x0ffff885 -#define CYREG_SFLASH_ALT_PROT_ROW134 0x0ffff886 -#define CYREG_SFLASH_ALT_PROT_ROW135 0x0ffff887 -#define CYREG_SFLASH_ALT_PROT_ROW136 0x0ffff888 -#define CYREG_SFLASH_ALT_PROT_ROW137 0x0ffff889 -#define CYREG_SFLASH_ALT_PROT_ROW138 0x0ffff88a -#define CYREG_SFLASH_ALT_PROT_ROW139 0x0ffff88b -#define CYREG_SFLASH_ALT_PROT_ROW140 0x0ffff88c -#define CYREG_SFLASH_ALT_PROT_ROW141 0x0ffff88d -#define CYREG_SFLASH_ALT_PROT_ROW142 0x0ffff88e -#define CYREG_SFLASH_ALT_PROT_ROW143 0x0ffff88f -#define CYREG_SFLASH_ALT_PROT_ROW144 0x0ffff890 -#define CYREG_SFLASH_ALT_PROT_ROW145 0x0ffff891 -#define CYREG_SFLASH_ALT_PROT_ROW146 0x0ffff892 -#define CYREG_SFLASH_ALT_PROT_ROW147 0x0ffff893 -#define CYREG_SFLASH_ALT_PROT_ROW148 0x0ffff894 -#define CYREG_SFLASH_ALT_PROT_ROW149 0x0ffff895 -#define CYREG_SFLASH_ALT_PROT_ROW150 0x0ffff896 -#define CYREG_SFLASH_ALT_PROT_ROW151 0x0ffff897 -#define CYREG_SFLASH_ALT_PROT_ROW152 0x0ffff898 -#define CYREG_SFLASH_ALT_PROT_ROW153 0x0ffff899 -#define CYREG_SFLASH_ALT_PROT_ROW154 0x0ffff89a -#define CYREG_SFLASH_ALT_PROT_ROW155 0x0ffff89b -#define CYREG_SFLASH_ALT_PROT_ROW156 0x0ffff89c -#define CYREG_SFLASH_ALT_PROT_ROW157 0x0ffff89d -#define CYREG_SFLASH_ALT_PROT_ROW158 0x0ffff89e -#define CYREG_SFLASH_ALT_PROT_ROW159 0x0ffff89f -#define CYREG_SFLASH_ALT_PROT_ROW160 0x0ffff8a0 -#define CYREG_SFLASH_ALT_PROT_ROW161 0x0ffff8a1 -#define CYREG_SFLASH_ALT_PROT_ROW162 0x0ffff8a2 -#define CYREG_SFLASH_ALT_PROT_ROW163 0x0ffff8a3 -#define CYREG_SFLASH_ALT_PROT_ROW164 0x0ffff8a4 -#define CYREG_SFLASH_ALT_PROT_ROW165 0x0ffff8a5 -#define CYREG_SFLASH_ALT_PROT_ROW166 0x0ffff8a6 -#define CYREG_SFLASH_ALT_PROT_ROW167 0x0ffff8a7 -#define CYREG_SFLASH_ALT_PROT_ROW168 0x0ffff8a8 -#define CYREG_SFLASH_ALT_PROT_ROW169 0x0ffff8a9 -#define CYREG_SFLASH_ALT_PROT_ROW170 0x0ffff8aa -#define CYREG_SFLASH_ALT_PROT_ROW171 0x0ffff8ab -#define CYREG_SFLASH_ALT_PROT_ROW172 0x0ffff8ac -#define CYREG_SFLASH_ALT_PROT_ROW173 0x0ffff8ad -#define CYREG_SFLASH_ALT_PROT_ROW174 0x0ffff8ae -#define CYREG_SFLASH_ALT_PROT_ROW175 0x0ffff8af -#define CYREG_SFLASH_ALT_PROT_ROW176 0x0ffff8b0 -#define CYREG_SFLASH_ALT_PROT_ROW177 0x0ffff8b1 -#define CYREG_SFLASH_ALT_PROT_ROW178 0x0ffff8b2 -#define CYREG_SFLASH_ALT_PROT_ROW179 0x0ffff8b3 -#define CYREG_SFLASH_ALT_PROT_ROW180 0x0ffff8b4 -#define CYREG_SFLASH_ALT_PROT_ROW181 0x0ffff8b5 -#define CYREG_SFLASH_ALT_PROT_ROW182 0x0ffff8b6 -#define CYREG_SFLASH_ALT_PROT_ROW183 0x0ffff8b7 -#define CYREG_SFLASH_ALT_PROT_ROW184 0x0ffff8b8 -#define CYREG_SFLASH_ALT_PROT_ROW185 0x0ffff8b9 -#define CYREG_SFLASH_ALT_PROT_ROW186 0x0ffff8ba -#define CYREG_SFLASH_ALT_PROT_ROW187 0x0ffff8bb -#define CYREG_SFLASH_ALT_PROT_ROW188 0x0ffff8bc -#define CYREG_SFLASH_ALT_PROT_ROW189 0x0ffff8bd -#define CYREG_SFLASH_ALT_PROT_ROW190 0x0ffff8be -#define CYREG_SFLASH_ALT_PROT_ROW191 0x0ffff8bf -#define CYREG_SFLASH_ALT_PROT_ROW192 0x0ffff8c0 -#define CYREG_SFLASH_ALT_PROT_ROW193 0x0ffff8c1 -#define CYREG_SFLASH_ALT_PROT_ROW194 0x0ffff8c2 -#define CYREG_SFLASH_ALT_PROT_ROW195 0x0ffff8c3 -#define CYREG_SFLASH_ALT_PROT_ROW196 0x0ffff8c4 -#define CYREG_SFLASH_ALT_PROT_ROW197 0x0ffff8c5 -#define CYREG_SFLASH_ALT_PROT_ROW198 0x0ffff8c6 -#define CYREG_SFLASH_ALT_PROT_ROW199 0x0ffff8c7 -#define CYREG_SFLASH_ALT_PROT_ROW200 0x0ffff8c8 -#define CYREG_SFLASH_ALT_PROT_ROW201 0x0ffff8c9 -#define CYREG_SFLASH_ALT_PROT_ROW202 0x0ffff8ca -#define CYREG_SFLASH_ALT_PROT_ROW203 0x0ffff8cb -#define CYREG_SFLASH_ALT_PROT_ROW204 0x0ffff8cc -#define CYREG_SFLASH_ALT_PROT_ROW205 0x0ffff8cd -#define CYREG_SFLASH_ALT_PROT_ROW206 0x0ffff8ce -#define CYREG_SFLASH_ALT_PROT_ROW207 0x0ffff8cf -#define CYREG_SFLASH_ALT_PROT_ROW208 0x0ffff8d0 -#define CYREG_SFLASH_ALT_PROT_ROW209 0x0ffff8d1 -#define CYREG_SFLASH_ALT_PROT_ROW210 0x0ffff8d2 -#define CYREG_SFLASH_ALT_PROT_ROW211 0x0ffff8d3 -#define CYREG_SFLASH_ALT_PROT_ROW212 0x0ffff8d4 -#define CYREG_SFLASH_ALT_PROT_ROW213 0x0ffff8d5 -#define CYREG_SFLASH_ALT_PROT_ROW214 0x0ffff8d6 -#define CYREG_SFLASH_ALT_PROT_ROW215 0x0ffff8d7 -#define CYREG_SFLASH_ALT_PROT_ROW216 0x0ffff8d8 -#define CYREG_SFLASH_ALT_PROT_ROW217 0x0ffff8d9 -#define CYREG_SFLASH_ALT_PROT_ROW218 0x0ffff8da -#define CYREG_SFLASH_ALT_PROT_ROW219 0x0ffff8db -#define CYREG_SFLASH_ALT_PROT_ROW220 0x0ffff8dc -#define CYREG_SFLASH_ALT_PROT_ROW221 0x0ffff8dd -#define CYREG_SFLASH_ALT_PROT_ROW222 0x0ffff8de -#define CYREG_SFLASH_ALT_PROT_ROW223 0x0ffff8df -#define CYREG_SFLASH_ALT_PROT_ROW224 0x0ffff8e0 -#define CYREG_SFLASH_ALT_PROT_ROW225 0x0ffff8e1 -#define CYREG_SFLASH_ALT_PROT_ROW226 0x0ffff8e2 -#define CYREG_SFLASH_ALT_PROT_ROW227 0x0ffff8e3 -#define CYREG_SFLASH_ALT_PROT_ROW228 0x0ffff8e4 -#define CYREG_SFLASH_ALT_PROT_ROW229 0x0ffff8e5 -#define CYREG_SFLASH_ALT_PROT_ROW230 0x0ffff8e6 -#define CYREG_SFLASH_ALT_PROT_ROW231 0x0ffff8e7 -#define CYREG_SFLASH_ALT_PROT_ROW232 0x0ffff8e8 -#define CYREG_SFLASH_ALT_PROT_ROW233 0x0ffff8e9 -#define CYREG_SFLASH_ALT_PROT_ROW234 0x0ffff8ea -#define CYREG_SFLASH_ALT_PROT_ROW235 0x0ffff8eb -#define CYREG_SFLASH_ALT_PROT_ROW236 0x0ffff8ec -#define CYREG_SFLASH_ALT_PROT_ROW237 0x0ffff8ed -#define CYREG_SFLASH_ALT_PROT_ROW238 0x0ffff8ee -#define CYREG_SFLASH_ALT_PROT_ROW239 0x0ffff8ef -#define CYREG_SFLASH_ALT_PROT_ROW240 0x0ffff8f0 -#define CYREG_SFLASH_ALT_PROT_ROW241 0x0ffff8f1 -#define CYREG_SFLASH_ALT_PROT_ROW242 0x0ffff8f2 -#define CYREG_SFLASH_ALT_PROT_ROW243 0x0ffff8f3 -#define CYREG_SFLASH_ALT_PROT_ROW244 0x0ffff8f4 -#define CYREG_SFLASH_ALT_PROT_ROW245 0x0ffff8f5 -#define CYREG_SFLASH_ALT_PROT_ROW246 0x0ffff8f6 -#define CYREG_SFLASH_ALT_PROT_ROW247 0x0ffff8f7 -#define CYREG_SFLASH_ALT_PROT_ROW248 0x0ffff8f8 -#define CYREG_SFLASH_ALT_PROT_ROW249 0x0ffff8f9 -#define CYREG_SFLASH_ALT_PROT_ROW250 0x0ffff8fa -#define CYREG_SFLASH_ALT_PROT_ROW251 0x0ffff8fb -#define CYREG_SFLASH_ALT_PROT_ROW252 0x0ffff8fc -#define CYREG_SFLASH_ALT_PROT_ROW253 0x0ffff8fd -#define CYREG_SFLASH_ALT_PROT_ROW254 0x0ffff8fe -#define CYREG_SFLASH_ALT_PROT_ROW255 0x0ffff8ff -#define CYREG_SFLASH_ALT_PP 0x0ffffb20 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff201 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff202 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff203 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff204 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff205 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff206 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff207 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff208 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff209 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff20a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff20b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff20c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff20d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff20e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff20f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff210 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff211 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff212 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff213 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff214 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff215 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff216 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff217 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff218 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff219 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff21a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff21b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff21c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff21d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff21e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff21f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff220 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff221 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff222 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff223 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff224 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff225 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff226 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff227 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff228 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff229 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff22a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff22b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff22c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff22d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff22e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff22f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff230 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff231 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff232 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff233 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff234 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff235 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff236 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff237 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff238 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff239 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff23a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff23b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff23c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff23d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff23e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff23f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff240 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff241 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff242 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff243 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff244 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff245 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff246 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff247 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff248 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff249 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff24a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff24b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff24c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff24d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff24e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff24f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff250 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff251 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff252 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff253 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff254 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff255 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff256 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff257 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff258 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff259 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff25a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff25b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff25c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff25d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff25e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff25f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff260 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff261 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff262 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff263 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff264 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff265 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff266 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff267 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff268 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff269 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff26a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff26b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff26c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff26d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff26e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff26f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff270 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff271 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff272 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff273 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff274 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff275 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff276 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff277 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff278 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff279 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff27a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff27b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff27c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff27d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff27e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff27f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff280 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff281 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff282 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff283 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff284 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff285 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff286 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff287 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff288 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff289 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff28a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff28b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff28c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff28d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff28e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff28f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff290 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff291 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff292 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff293 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff294 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff295 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff296 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff297 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff298 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff299 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff29a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff29b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff29c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff29d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff29e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff29f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff2a0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff2a1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff2a2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff2a3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff2a4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff2a5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff2a6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff2a7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff2a8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff2a9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff2aa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff2ab +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff2ac +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff2ad +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff2ae +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff2af +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff2b0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff2b1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff2b2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff2b3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff2b4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff2b5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff2b6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff2b7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff2b8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff2b9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff2ba +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff2bb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff2bc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff2bd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff2be +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff2bf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff2c0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff2c1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff2c2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff2c3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff2c4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff2c5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff2c6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff2c7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff2c8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff2c9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff2ca +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff2cb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff2cc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff2cd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff2ce +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff2cf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff2d0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff2d1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff2d2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff2d3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff2d4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff2d5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff2d6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff2d7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff2d8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff2d9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff2da +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff2db +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff2dc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff2dd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff2de +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff2df +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff2e0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff2e1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff2e2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff2e3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff2e4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff2e5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff2e6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff2e7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff2e8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff2e9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff2ea +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff2eb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff2ec +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff2ed +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff2ee +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff2ef +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff2f0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff2f1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff2f2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff2f3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff2f4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff2f5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff2f6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff2f7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff2f8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff2f9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff2fa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff2fb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff2fc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff2fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff2fe +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff2ff +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff300 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff301 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff302 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff303 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff304 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff305 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff306 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff307 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff308 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff309 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff30a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff30b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff30c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff30d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff30e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff30f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff310 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff311 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff312 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff313 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff314 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff315 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff316 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff317 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff318 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff319 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff31a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff31b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff31c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff31d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff31e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff31f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff320 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff321 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff322 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff323 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff324 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff325 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff326 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff327 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff328 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff329 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff32a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff32b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff32c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff32d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff32e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff32f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff330 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff331 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff332 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff333 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff334 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff335 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff336 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff337 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff338 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff339 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff33a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff33b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff33c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff33d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff33e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff33f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff340 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff341 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff342 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff343 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff344 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff345 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff346 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff347 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff348 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff349 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff34a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff34b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff34c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff34d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff34e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff34f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff350 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff351 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff352 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff353 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff354 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff355 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff356 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff357 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff358 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff359 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff35a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff35b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff35c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff35d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff35e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff35f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff360 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff361 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff362 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff363 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff364 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff365 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff366 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff367 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff368 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff369 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff36a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff36b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff36c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff36d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff36e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff36f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff370 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff371 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff372 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff373 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff374 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff375 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff376 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff377 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff378 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff379 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff37a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff37b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff37c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff37d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff37e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff37f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff380 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff381 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff382 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff383 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff384 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff385 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff386 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff387 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff388 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff389 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff38a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff38b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff38c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff38d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff38e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff38f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff390 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff391 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff392 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff393 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff394 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff395 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff396 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff397 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff398 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff399 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff39a +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff39b +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff39c +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff39d +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff39e +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff39f +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff3a0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff3a1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff3a2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff3a3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff3a4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff3a5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff3a6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff3a7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff3a8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff3a9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff3aa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff3ab +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff3ac +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff3ad +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff3ae +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff3af +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff3b0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff3b1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff3b2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff3b3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff3b4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff3b5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff3b6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff3b7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff3b8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff3b9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff3ba +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff3bb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff3bc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff3bd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff3be +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff3bf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff3c0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff3c1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff3c2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff3c3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff3c4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff3c5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff3c6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff3c7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff3c8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff3c9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff3ca +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff3cb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff3cc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff3cd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff3ce +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff3cf +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff3d0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff3d1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff3d2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff3d3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff3d4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff3d5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff3d6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff3d7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff3d8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff3d9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff3da +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff3db +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff3dc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff3dd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff3de +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff3df +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff3e0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff3e1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff3e2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff3e3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff3e4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff3e5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff3e6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff3e7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff3e8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff3e9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff3ea +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff3eb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff3ec +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff3ed +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff3ee +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff3ef +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff3f0 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff3f1 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff3f2 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff3f3 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff3f4 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff3f5 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff3f6 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff3f7 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff3f8 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff3f9 +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff3fa +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff3fb +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff3fc +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff3fd +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff3fe +#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff3ff +#define CYREG_SFLASH_ALT_PROT_ROW0 0x0ffff400 +#define CYREG_SFLASH_ALT_PROT_ROW1 0x0ffff401 +#define CYREG_SFLASH_ALT_PROT_ROW2 0x0ffff402 +#define CYREG_SFLASH_ALT_PROT_ROW3 0x0ffff403 +#define CYREG_SFLASH_ALT_PROT_ROW4 0x0ffff404 +#define CYREG_SFLASH_ALT_PROT_ROW5 0x0ffff405 +#define CYREG_SFLASH_ALT_PROT_ROW6 0x0ffff406 +#define CYREG_SFLASH_ALT_PROT_ROW7 0x0ffff407 +#define CYREG_SFLASH_ALT_PROT_ROW8 0x0ffff408 +#define CYREG_SFLASH_ALT_PROT_ROW9 0x0ffff409 +#define CYREG_SFLASH_ALT_PROT_ROW10 0x0ffff40a +#define CYREG_SFLASH_ALT_PROT_ROW11 0x0ffff40b +#define CYREG_SFLASH_ALT_PROT_ROW12 0x0ffff40c +#define CYREG_SFLASH_ALT_PROT_ROW13 0x0ffff40d +#define CYREG_SFLASH_ALT_PROT_ROW14 0x0ffff40e +#define CYREG_SFLASH_ALT_PROT_ROW15 0x0ffff40f +#define CYREG_SFLASH_ALT_PROT_ROW16 0x0ffff410 +#define CYREG_SFLASH_ALT_PROT_ROW17 0x0ffff411 +#define CYREG_SFLASH_ALT_PROT_ROW18 0x0ffff412 +#define CYREG_SFLASH_ALT_PROT_ROW19 0x0ffff413 +#define CYREG_SFLASH_ALT_PROT_ROW20 0x0ffff414 +#define CYREG_SFLASH_ALT_PROT_ROW21 0x0ffff415 +#define CYREG_SFLASH_ALT_PROT_ROW22 0x0ffff416 +#define CYREG_SFLASH_ALT_PROT_ROW23 0x0ffff417 +#define CYREG_SFLASH_ALT_PROT_ROW24 0x0ffff418 +#define CYREG_SFLASH_ALT_PROT_ROW25 0x0ffff419 +#define CYREG_SFLASH_ALT_PROT_ROW26 0x0ffff41a +#define CYREG_SFLASH_ALT_PROT_ROW27 0x0ffff41b +#define CYREG_SFLASH_ALT_PROT_ROW28 0x0ffff41c +#define CYREG_SFLASH_ALT_PROT_ROW29 0x0ffff41d +#define CYREG_SFLASH_ALT_PROT_ROW30 0x0ffff41e +#define CYREG_SFLASH_ALT_PROT_ROW31 0x0ffff41f +#define CYREG_SFLASH_ALT_PROT_ROW32 0x0ffff420 +#define CYREG_SFLASH_ALT_PROT_ROW33 0x0ffff421 +#define CYREG_SFLASH_ALT_PROT_ROW34 0x0ffff422 +#define CYREG_SFLASH_ALT_PROT_ROW35 0x0ffff423 +#define CYREG_SFLASH_ALT_PROT_ROW36 0x0ffff424 +#define CYREG_SFLASH_ALT_PROT_ROW37 0x0ffff425 +#define CYREG_SFLASH_ALT_PROT_ROW38 0x0ffff426 +#define CYREG_SFLASH_ALT_PROT_ROW39 0x0ffff427 +#define CYREG_SFLASH_ALT_PROT_ROW40 0x0ffff428 +#define CYREG_SFLASH_ALT_PROT_ROW41 0x0ffff429 +#define CYREG_SFLASH_ALT_PROT_ROW42 0x0ffff42a +#define CYREG_SFLASH_ALT_PROT_ROW43 0x0ffff42b +#define CYREG_SFLASH_ALT_PROT_ROW44 0x0ffff42c +#define CYREG_SFLASH_ALT_PROT_ROW45 0x0ffff42d +#define CYREG_SFLASH_ALT_PROT_ROW46 0x0ffff42e +#define CYREG_SFLASH_ALT_PROT_ROW47 0x0ffff42f +#define CYREG_SFLASH_ALT_PROT_ROW48 0x0ffff430 +#define CYREG_SFLASH_ALT_PROT_ROW49 0x0ffff431 +#define CYREG_SFLASH_ALT_PROT_ROW50 0x0ffff432 +#define CYREG_SFLASH_ALT_PROT_ROW51 0x0ffff433 +#define CYREG_SFLASH_ALT_PROT_ROW52 0x0ffff434 +#define CYREG_SFLASH_ALT_PROT_ROW53 0x0ffff435 +#define CYREG_SFLASH_ALT_PROT_ROW54 0x0ffff436 +#define CYREG_SFLASH_ALT_PROT_ROW55 0x0ffff437 +#define CYREG_SFLASH_ALT_PROT_ROW56 0x0ffff438 +#define CYREG_SFLASH_ALT_PROT_ROW57 0x0ffff439 +#define CYREG_SFLASH_ALT_PROT_ROW58 0x0ffff43a +#define CYREG_SFLASH_ALT_PROT_ROW59 0x0ffff43b +#define CYREG_SFLASH_ALT_PROT_ROW60 0x0ffff43c +#define CYREG_SFLASH_ALT_PROT_ROW61 0x0ffff43d +#define CYREG_SFLASH_ALT_PROT_ROW62 0x0ffff43e +#define CYREG_SFLASH_ALT_PROT_ROW63 0x0ffff43f +#define CYREG_SFLASH_ALT_PROT_ROW64 0x0ffff440 +#define CYREG_SFLASH_ALT_PROT_ROW65 0x0ffff441 +#define CYREG_SFLASH_ALT_PROT_ROW66 0x0ffff442 +#define CYREG_SFLASH_ALT_PROT_ROW67 0x0ffff443 +#define CYREG_SFLASH_ALT_PROT_ROW68 0x0ffff444 +#define CYREG_SFLASH_ALT_PROT_ROW69 0x0ffff445 +#define CYREG_SFLASH_ALT_PROT_ROW70 0x0ffff446 +#define CYREG_SFLASH_ALT_PROT_ROW71 0x0ffff447 +#define CYREG_SFLASH_ALT_PROT_ROW72 0x0ffff448 +#define CYREG_SFLASH_ALT_PROT_ROW73 0x0ffff449 +#define CYREG_SFLASH_ALT_PROT_ROW74 0x0ffff44a +#define CYREG_SFLASH_ALT_PROT_ROW75 0x0ffff44b +#define CYREG_SFLASH_ALT_PROT_ROW76 0x0ffff44c +#define CYREG_SFLASH_ALT_PROT_ROW77 0x0ffff44d +#define CYREG_SFLASH_ALT_PROT_ROW78 0x0ffff44e +#define CYREG_SFLASH_ALT_PROT_ROW79 0x0ffff44f +#define CYREG_SFLASH_ALT_PROT_ROW80 0x0ffff450 +#define CYREG_SFLASH_ALT_PROT_ROW81 0x0ffff451 +#define CYREG_SFLASH_ALT_PROT_ROW82 0x0ffff452 +#define CYREG_SFLASH_ALT_PROT_ROW83 0x0ffff453 +#define CYREG_SFLASH_ALT_PROT_ROW84 0x0ffff454 +#define CYREG_SFLASH_ALT_PROT_ROW85 0x0ffff455 +#define CYREG_SFLASH_ALT_PROT_ROW86 0x0ffff456 +#define CYREG_SFLASH_ALT_PROT_ROW87 0x0ffff457 +#define CYREG_SFLASH_ALT_PROT_ROW88 0x0ffff458 +#define CYREG_SFLASH_ALT_PROT_ROW89 0x0ffff459 +#define CYREG_SFLASH_ALT_PROT_ROW90 0x0ffff45a +#define CYREG_SFLASH_ALT_PROT_ROW91 0x0ffff45b +#define CYREG_SFLASH_ALT_PROT_ROW92 0x0ffff45c +#define CYREG_SFLASH_ALT_PROT_ROW93 0x0ffff45d +#define CYREG_SFLASH_ALT_PROT_ROW94 0x0ffff45e +#define CYREG_SFLASH_ALT_PROT_ROW95 0x0ffff45f +#define CYREG_SFLASH_ALT_PROT_ROW96 0x0ffff460 +#define CYREG_SFLASH_ALT_PROT_ROW97 0x0ffff461 +#define CYREG_SFLASH_ALT_PROT_ROW98 0x0ffff462 +#define CYREG_SFLASH_ALT_PROT_ROW99 0x0ffff463 +#define CYREG_SFLASH_ALT_PROT_ROW100 0x0ffff464 +#define CYREG_SFLASH_ALT_PROT_ROW101 0x0ffff465 +#define CYREG_SFLASH_ALT_PROT_ROW102 0x0ffff466 +#define CYREG_SFLASH_ALT_PROT_ROW103 0x0ffff467 +#define CYREG_SFLASH_ALT_PROT_ROW104 0x0ffff468 +#define CYREG_SFLASH_ALT_PROT_ROW105 0x0ffff469 +#define CYREG_SFLASH_ALT_PROT_ROW106 0x0ffff46a +#define CYREG_SFLASH_ALT_PROT_ROW107 0x0ffff46b +#define CYREG_SFLASH_ALT_PROT_ROW108 0x0ffff46c +#define CYREG_SFLASH_ALT_PROT_ROW109 0x0ffff46d +#define CYREG_SFLASH_ALT_PROT_ROW110 0x0ffff46e +#define CYREG_SFLASH_ALT_PROT_ROW111 0x0ffff46f +#define CYREG_SFLASH_ALT_PROT_ROW112 0x0ffff470 +#define CYREG_SFLASH_ALT_PROT_ROW113 0x0ffff471 +#define CYREG_SFLASH_ALT_PROT_ROW114 0x0ffff472 +#define CYREG_SFLASH_ALT_PROT_ROW115 0x0ffff473 +#define CYREG_SFLASH_ALT_PROT_ROW116 0x0ffff474 +#define CYREG_SFLASH_ALT_PROT_ROW117 0x0ffff475 +#define CYREG_SFLASH_ALT_PROT_ROW118 0x0ffff476 +#define CYREG_SFLASH_ALT_PROT_ROW119 0x0ffff477 +#define CYREG_SFLASH_ALT_PROT_ROW120 0x0ffff478 +#define CYREG_SFLASH_ALT_PROT_ROW121 0x0ffff479 +#define CYREG_SFLASH_ALT_PROT_ROW122 0x0ffff47a +#define CYREG_SFLASH_ALT_PROT_ROW123 0x0ffff47b +#define CYREG_SFLASH_ALT_PROT_ROW124 0x0ffff47c +#define CYREG_SFLASH_ALT_PROT_ROW125 0x0ffff47d +#define CYREG_SFLASH_ALT_PROT_ROW126 0x0ffff47e +#define CYREG_SFLASH_ALT_PROT_ROW127 0x0ffff47f +#define CYREG_SFLASH_ALT_PROT_ROW128 0x0ffff480 +#define CYREG_SFLASH_ALT_PROT_ROW129 0x0ffff481 +#define CYREG_SFLASH_ALT_PROT_ROW130 0x0ffff482 +#define CYREG_SFLASH_ALT_PROT_ROW131 0x0ffff483 +#define CYREG_SFLASH_ALT_PROT_ROW132 0x0ffff484 +#define CYREG_SFLASH_ALT_PROT_ROW133 0x0ffff485 +#define CYREG_SFLASH_ALT_PROT_ROW134 0x0ffff486 +#define CYREG_SFLASH_ALT_PROT_ROW135 0x0ffff487 +#define CYREG_SFLASH_ALT_PROT_ROW136 0x0ffff488 +#define CYREG_SFLASH_ALT_PROT_ROW137 0x0ffff489 +#define CYREG_SFLASH_ALT_PROT_ROW138 0x0ffff48a +#define CYREG_SFLASH_ALT_PROT_ROW139 0x0ffff48b +#define CYREG_SFLASH_ALT_PROT_ROW140 0x0ffff48c +#define CYREG_SFLASH_ALT_PROT_ROW141 0x0ffff48d +#define CYREG_SFLASH_ALT_PROT_ROW142 0x0ffff48e +#define CYREG_SFLASH_ALT_PROT_ROW143 0x0ffff48f +#define CYREG_SFLASH_ALT_PROT_ROW144 0x0ffff490 +#define CYREG_SFLASH_ALT_PROT_ROW145 0x0ffff491 +#define CYREG_SFLASH_ALT_PROT_ROW146 0x0ffff492 +#define CYREG_SFLASH_ALT_PROT_ROW147 0x0ffff493 +#define CYREG_SFLASH_ALT_PROT_ROW148 0x0ffff494 +#define CYREG_SFLASH_ALT_PROT_ROW149 0x0ffff495 +#define CYREG_SFLASH_ALT_PROT_ROW150 0x0ffff496 +#define CYREG_SFLASH_ALT_PROT_ROW151 0x0ffff497 +#define CYREG_SFLASH_ALT_PROT_ROW152 0x0ffff498 +#define CYREG_SFLASH_ALT_PROT_ROW153 0x0ffff499 +#define CYREG_SFLASH_ALT_PROT_ROW154 0x0ffff49a +#define CYREG_SFLASH_ALT_PROT_ROW155 0x0ffff49b +#define CYREG_SFLASH_ALT_PROT_ROW156 0x0ffff49c +#define CYREG_SFLASH_ALT_PROT_ROW157 0x0ffff49d +#define CYREG_SFLASH_ALT_PROT_ROW158 0x0ffff49e +#define CYREG_SFLASH_ALT_PROT_ROW159 0x0ffff49f +#define CYREG_SFLASH_ALT_PROT_ROW160 0x0ffff4a0 +#define CYREG_SFLASH_ALT_PROT_ROW161 0x0ffff4a1 +#define CYREG_SFLASH_ALT_PROT_ROW162 0x0ffff4a2 +#define CYREG_SFLASH_ALT_PROT_ROW163 0x0ffff4a3 +#define CYREG_SFLASH_ALT_PROT_ROW164 0x0ffff4a4 +#define CYREG_SFLASH_ALT_PROT_ROW165 0x0ffff4a5 +#define CYREG_SFLASH_ALT_PROT_ROW166 0x0ffff4a6 +#define CYREG_SFLASH_ALT_PROT_ROW167 0x0ffff4a7 +#define CYREG_SFLASH_ALT_PROT_ROW168 0x0ffff4a8 +#define CYREG_SFLASH_ALT_PROT_ROW169 0x0ffff4a9 +#define CYREG_SFLASH_ALT_PROT_ROW170 0x0ffff4aa +#define CYREG_SFLASH_ALT_PROT_ROW171 0x0ffff4ab +#define CYREG_SFLASH_ALT_PROT_ROW172 0x0ffff4ac +#define CYREG_SFLASH_ALT_PROT_ROW173 0x0ffff4ad +#define CYREG_SFLASH_ALT_PROT_ROW174 0x0ffff4ae +#define CYREG_SFLASH_ALT_PROT_ROW175 0x0ffff4af +#define CYREG_SFLASH_ALT_PROT_ROW176 0x0ffff4b0 +#define CYREG_SFLASH_ALT_PROT_ROW177 0x0ffff4b1 +#define CYREG_SFLASH_ALT_PROT_ROW178 0x0ffff4b2 +#define CYREG_SFLASH_ALT_PROT_ROW179 0x0ffff4b3 +#define CYREG_SFLASH_ALT_PROT_ROW180 0x0ffff4b4 +#define CYREG_SFLASH_ALT_PROT_ROW181 0x0ffff4b5 +#define CYREG_SFLASH_ALT_PROT_ROW182 0x0ffff4b6 +#define CYREG_SFLASH_ALT_PROT_ROW183 0x0ffff4b7 +#define CYREG_SFLASH_ALT_PROT_ROW184 0x0ffff4b8 +#define CYREG_SFLASH_ALT_PROT_ROW185 0x0ffff4b9 +#define CYREG_SFLASH_ALT_PROT_ROW186 0x0ffff4ba +#define CYREG_SFLASH_ALT_PROT_ROW187 0x0ffff4bb +#define CYREG_SFLASH_ALT_PROT_ROW188 0x0ffff4bc +#define CYREG_SFLASH_ALT_PROT_ROW189 0x0ffff4bd +#define CYREG_SFLASH_ALT_PROT_ROW190 0x0ffff4be +#define CYREG_SFLASH_ALT_PROT_ROW191 0x0ffff4bf +#define CYREG_SFLASH_ALT_PROT_ROW192 0x0ffff4c0 +#define CYREG_SFLASH_ALT_PROT_ROW193 0x0ffff4c1 +#define CYREG_SFLASH_ALT_PROT_ROW194 0x0ffff4c2 +#define CYREG_SFLASH_ALT_PROT_ROW195 0x0ffff4c3 +#define CYREG_SFLASH_ALT_PROT_ROW196 0x0ffff4c4 +#define CYREG_SFLASH_ALT_PROT_ROW197 0x0ffff4c5 +#define CYREG_SFLASH_ALT_PROT_ROW198 0x0ffff4c6 +#define CYREG_SFLASH_ALT_PROT_ROW199 0x0ffff4c7 +#define CYREG_SFLASH_ALT_PROT_ROW200 0x0ffff4c8 +#define CYREG_SFLASH_ALT_PROT_ROW201 0x0ffff4c9 +#define CYREG_SFLASH_ALT_PROT_ROW202 0x0ffff4ca +#define CYREG_SFLASH_ALT_PROT_ROW203 0x0ffff4cb +#define CYREG_SFLASH_ALT_PROT_ROW204 0x0ffff4cc +#define CYREG_SFLASH_ALT_PROT_ROW205 0x0ffff4cd +#define CYREG_SFLASH_ALT_PROT_ROW206 0x0ffff4ce +#define CYREG_SFLASH_ALT_PROT_ROW207 0x0ffff4cf +#define CYREG_SFLASH_ALT_PROT_ROW208 0x0ffff4d0 +#define CYREG_SFLASH_ALT_PROT_ROW209 0x0ffff4d1 +#define CYREG_SFLASH_ALT_PROT_ROW210 0x0ffff4d2 +#define CYREG_SFLASH_ALT_PROT_ROW211 0x0ffff4d3 +#define CYREG_SFLASH_ALT_PROT_ROW212 0x0ffff4d4 +#define CYREG_SFLASH_ALT_PROT_ROW213 0x0ffff4d5 +#define CYREG_SFLASH_ALT_PROT_ROW214 0x0ffff4d6 +#define CYREG_SFLASH_ALT_PROT_ROW215 0x0ffff4d7 +#define CYREG_SFLASH_ALT_PROT_ROW216 0x0ffff4d8 +#define CYREG_SFLASH_ALT_PROT_ROW217 0x0ffff4d9 +#define CYREG_SFLASH_ALT_PROT_ROW218 0x0ffff4da +#define CYREG_SFLASH_ALT_PROT_ROW219 0x0ffff4db +#define CYREG_SFLASH_ALT_PROT_ROW220 0x0ffff4dc +#define CYREG_SFLASH_ALT_PROT_ROW221 0x0ffff4dd +#define CYREG_SFLASH_ALT_PROT_ROW222 0x0ffff4de +#define CYREG_SFLASH_ALT_PROT_ROW223 0x0ffff4df +#define CYREG_SFLASH_ALT_PROT_ROW224 0x0ffff4e0 +#define CYREG_SFLASH_ALT_PROT_ROW225 0x0ffff4e1 +#define CYREG_SFLASH_ALT_PROT_ROW226 0x0ffff4e2 +#define CYREG_SFLASH_ALT_PROT_ROW227 0x0ffff4e3 +#define CYREG_SFLASH_ALT_PROT_ROW228 0x0ffff4e4 +#define CYREG_SFLASH_ALT_PROT_ROW229 0x0ffff4e5 +#define CYREG_SFLASH_ALT_PROT_ROW230 0x0ffff4e6 +#define CYREG_SFLASH_ALT_PROT_ROW231 0x0ffff4e7 +#define CYREG_SFLASH_ALT_PROT_ROW232 0x0ffff4e8 +#define CYREG_SFLASH_ALT_PROT_ROW233 0x0ffff4e9 +#define CYREG_SFLASH_ALT_PROT_ROW234 0x0ffff4ea +#define CYREG_SFLASH_ALT_PROT_ROW235 0x0ffff4eb +#define CYREG_SFLASH_ALT_PROT_ROW236 0x0ffff4ec +#define CYREG_SFLASH_ALT_PROT_ROW237 0x0ffff4ed +#define CYREG_SFLASH_ALT_PROT_ROW238 0x0ffff4ee +#define CYREG_SFLASH_ALT_PROT_ROW239 0x0ffff4ef +#define CYREG_SFLASH_ALT_PROT_ROW240 0x0ffff4f0 +#define CYREG_SFLASH_ALT_PROT_ROW241 0x0ffff4f1 +#define CYREG_SFLASH_ALT_PROT_ROW242 0x0ffff4f2 +#define CYREG_SFLASH_ALT_PROT_ROW243 0x0ffff4f3 +#define CYREG_SFLASH_ALT_PROT_ROW244 0x0ffff4f4 +#define CYREG_SFLASH_ALT_PROT_ROW245 0x0ffff4f5 +#define CYREG_SFLASH_ALT_PROT_ROW246 0x0ffff4f6 +#define CYREG_SFLASH_ALT_PROT_ROW247 0x0ffff4f7 +#define CYREG_SFLASH_ALT_PROT_ROW248 0x0ffff4f8 +#define CYREG_SFLASH_ALT_PROT_ROW249 0x0ffff4f9 +#define CYREG_SFLASH_ALT_PROT_ROW250 0x0ffff4fa +#define CYREG_SFLASH_ALT_PROT_ROW251 0x0ffff4fb +#define CYREG_SFLASH_ALT_PROT_ROW252 0x0ffff4fc +#define CYREG_SFLASH_ALT_PROT_ROW253 0x0ffff4fd +#define CYREG_SFLASH_ALT_PROT_ROW254 0x0ffff4fe +#define CYREG_SFLASH_ALT_PROT_ROW255 0x0ffff4ff +#define CYREG_SFLASH_ALT_PP 0x0ffff5a0 #define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000 #define CYFLD_SFLASH_PERIOD__SIZE 0x00000018 #define CYFLD_SFLASH_PDAC__OFFSET 0x00000018 #define CYFLD_SFLASH_PDAC__SIZE 0x00000004 #define CYFLD_SFLASH_NDAC__OFFSET 0x0000001c #define CYFLD_SFLASH_NDAC__SIZE 0x00000004 -#define CYREG_SFLASH_ALT_E 0x0ffffb24 -#define CYREG_SFLASH_ALT_P 0x0ffffb28 -#define CYREG_SFLASH_ALT_EA_E 0x0ffffb2c -#define CYREG_SFLASH_ALT_EA_P 0x0ffffb30 -#define CYREG_SFLASH_ALT_ES_E 0x0ffffb34 -#define CYREG_SFLASH_ALT_ES_P_EO 0x0ffffb38 -#define CYREG_SFLASH_ALT_E_VCTAT 0x0ffffb3c +#define CYREG_SFLASH_ALT_E 0x0ffff5a4 +#define CYREG_SFLASH_ALT_P 0x0ffff5a8 +#define CYREG_SFLASH_ALT_EA_E 0x0ffff5ac +#define CYREG_SFLASH_ALT_EA_P 0x0ffff5b0 +#define CYREG_SFLASH_ALT_ES_E 0x0ffff5b4 +#define CYREG_SFLASH_ALT_ES_P_EO 0x0ffff5b8 +#define CYREG_SFLASH_ALT_E_VCTAT 0x0ffff5bc #define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000 #define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004 #define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004 #define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002 #define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006 #define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001 -#define CYREG_SFLASH_ALT_P_VCTAT 0x0ffffb3d +#define CYREG_SFLASH_ALT_P_VCTAT 0x0ffff5bd #define CYDEV_ROM_BASE 0x10000000 #define CYDEV_ROM_SIZE 0x00002000 #define CYREG_ROM_DATA_MBASE 0x10000000 #define CYREG_ROM_DATA_MSIZE 0x00002000 #define CYDEV_SRAM_BASE 0x20000000 -#define CYDEV_SRAM_SIZE 0x00008000 +#define CYDEV_SRAM_SIZE 0x00004000 #define CYREG_SRAM_DATA_MBASE 0x20000000 -#define CYREG_SRAM_DATA_MSIZE 0x00008000 +#define CYREG_SRAM_DATA_MSIZE 0x00004000 #define CYDEV_PERI_BASE 0x40010000 #define CYDEV_PERI_SIZE 0x00010000 #define CYREG_PERI_DIV_CMD 0x40010000 @@ -1845,29 +1287,6 @@ #define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003 #define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005 #define CYREG_PERI_DIV_16_5_CTL1 0x40010404 -#define CYREG_PERI_TR_CTL 0x40010600 -#define CYFLD_PERI_TR_SEL__OFFSET 0x00000000 -#define CYFLD_PERI_TR_SEL__SIZE 0x00000007 -#define CYFLD_PERI_TR_GROUP__OFFSET 0x00000008 -#define CYFLD_PERI_TR_GROUP__SIZE 0x00000004 -#define CYFLD_PERI_TR_COUNT__OFFSET 0x00000010 -#define CYFLD_PERI_TR_COUNT__SIZE 0x00000008 -#define CYFLD_PERI_TR_OUT__OFFSET 0x0000001e -#define CYFLD_PERI_TR_OUT__SIZE 0x00000001 -#define CYFLD_PERI_TR_ACT__OFFSET 0x0000001f -#define CYFLD_PERI_TR_ACT__SIZE 0x00000001 -#define CYDEV_PERI_TR_GROUP_BASE 0x40012000 -#define CYDEV_PERI_TR_GROUP_SIZE 0x00000200 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL0 0x40012000 -#define CYFLD_PERI_TR_GROUP_SEL__OFFSET 0x00000000 -#define CYFLD_PERI_TR_GROUP_SEL__SIZE 0x00000005 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL1 0x40012004 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL2 0x40012008 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL3 0x4001200c -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL4 0x40012010 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL5 0x40012014 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL6 0x40012018 -#define CYREG_PERI_TR_GROUP_TR_OUT_CTL7 0x4001201c #define CYDEV_HSIOM_BASE 0x40020000 #define CYDEV_HSIOM_SIZE 0x00004000 #define CYREG_HSIOM_PORT_SEL0 0x40020000 @@ -6250,165 +5669,9 @@ #define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001 #define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008 #define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001 -#define CYFLD_CPUSS_ARB__OFFSET 0x00000010 -#define CYFLD_CPUSS_ARB__SIZE 0x00000002 #define CYREG_CPUSS_ROM_CTL 0x40100034 #define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000 #define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001 -#define CYREG_CPUSS_RAM_CTL 0x40100038 -#define CYREG_CPUSS_DMAC_CTL 0x4010003c -#define CYREG_CPUSS_SL_CTL0 0x40100100 -#define CYREG_CPUSS_SL_CTL1 0x40100104 -#define CYREG_CPUSS_SL_CTL2 0x40100108 -#define CYDEV_DMAC_BASE 0x40101000 -#define CYDEV_DMAC_SIZE 0x00001000 -#define CYREG_DMAC_CTL 0x40101000 -#define CYFLD_DMAC_ENABLED__OFFSET 0x0000001f -#define CYFLD_DMAC_ENABLED__SIZE 0x00000001 -#define CYREG_DMAC_STATUS 0x40101010 -#define CYFLD_DMAC_DATA_NR__OFFSET 0x00000000 -#define CYFLD_DMAC_DATA_NR__SIZE 0x00000010 -#define CYFLD_DMAC_CH_ADDR__OFFSET 0x00000010 -#define CYFLD_DMAC_CH_ADDR__SIZE 0x00000003 -#define CYFLD_DMAC_STATE__OFFSET 0x00000018 -#define CYFLD_DMAC_STATE__SIZE 0x00000003 -#define CYFLD_DMAC_PRIO__OFFSET 0x0000001c -#define CYFLD_DMAC_PRIO__SIZE 0x00000002 -#define CYFLD_DMAC_PING_PONG__OFFSET 0x0000001e -#define CYFLD_DMAC_PING_PONG__SIZE 0x00000001 -#define CYFLD_DMAC_ACTIVE__OFFSET 0x0000001f -#define CYFLD_DMAC_ACTIVE__SIZE 0x00000001 -#define CYREG_DMAC_STATUS_SRC_ADDR 0x40101014 -#define CYFLD_DMAC_ADDR__OFFSET 0x00000000 -#define CYFLD_DMAC_ADDR__SIZE 0x00000020 -#define CYREG_DMAC_STATUS_DST_ADDR 0x40101018 -#define CYREG_DMAC_STATUS_CH_ACT 0x4010101c -#define CYFLD_DMAC_CH__OFFSET 0x00000000 -#define CYFLD_DMAC_CH__SIZE 0x00000008 -#define CYREG_DMAC_CH_CTL0 0x40101080 -#define CYREG_DMAC_CH_CTL1 0x40101084 -#define CYREG_DMAC_CH_CTL2 0x40101088 -#define CYREG_DMAC_CH_CTL3 0x4010108c -#define CYREG_DMAC_CH_CTL4 0x40101090 -#define CYREG_DMAC_CH_CTL5 0x40101094 -#define CYREG_DMAC_CH_CTL6 0x40101098 -#define CYREG_DMAC_CH_CTL7 0x4010109c -#define CYREG_DMAC_INTR 0x401017f0 -#define CYREG_DMAC_INTR_SET 0x401017f4 -#define CYREG_DMAC_INTR_MASK 0x401017f8 -#define CYREG_DMAC_INTR_MASKED 0x401017fc -#define CYDEV_DMAC_DESCR0_BASE 0x40101800 -#define CYDEV_DMAC_DESCR0_SIZE 0x00000020 -#define CYREG_DMAC_DESCR0_PING_SRC 0x40101800 -#define CYFLD_DMAC_DESCR_ADDR__OFFSET 0x00000000 -#define CYFLD_DMAC_DESCR_ADDR__SIZE 0x00000020 -#define CYREG_DMAC_DESCR0_PING_DST 0x40101804 -#define CYREG_DMAC_DESCR0_PING_CTL 0x40101808 -#define CYFLD_DMAC_DESCR_DATA_NR__OFFSET 0x00000000 -#define CYFLD_DMAC_DESCR_DATA_NR__SIZE 0x00000010 -#define CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET 0x00000010 -#define CYFLD_DMAC_DESCR_DATA_SIZE__SIZE 0x00000002 -#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET 0x00000014 -#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET 0x00000015 -#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET 0x00000016 -#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET 0x00000017 -#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET 0x00000018 -#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE 0x00000002 -#define CYFLD_DMAC_DESCR_INV_DESCR__OFFSET 0x0000001a -#define CYFLD_DMAC_DESCR_INV_DESCR__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET 0x0000001b -#define CYFLD_DMAC_DESCR_SET_CAUSE__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET 0x0000001c -#define CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_FLIPPING__OFFSET 0x0000001d -#define CYFLD_DMAC_DESCR_FLIPPING__SIZE 0x00000001 -#define CYFLD_DMAC_DESCR_OPCODE__OFFSET 0x0000001e -#define CYFLD_DMAC_DESCR_OPCODE__SIZE 0x00000002 -#define CYREG_DMAC_DESCR0_PING_STATUS 0x4010180c -#define CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET 0x00000000 -#define CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE 0x00000010 -#define CYFLD_DMAC_DESCR_RESPONSE__OFFSET 0x00000010 -#define CYFLD_DMAC_DESCR_RESPONSE__SIZE 0x00000003 -#define CYFLD_DMAC_DESCR_VALID__OFFSET 0x0000001f -#define CYFLD_DMAC_DESCR_VALID__SIZE 0x00000001 -#define CYREG_DMAC_DESCR0_PONG_SRC 0x40101810 -#define CYREG_DMAC_DESCR0_PONG_DST 0x40101814 -#define CYREG_DMAC_DESCR0_PONG_CTL 0x40101818 -#define CYREG_DMAC_DESCR0_PONG_STATUS 0x4010181c -#define CYDEV_DMAC_DESCR1_BASE 0x40101820 -#define CYDEV_DMAC_DESCR1_SIZE 0x00000020 -#define CYREG_DMAC_DESCR1_PING_SRC 0x40101820 -#define CYREG_DMAC_DESCR1_PING_DST 0x40101824 -#define CYREG_DMAC_DESCR1_PING_CTL 0x40101828 -#define CYREG_DMAC_DESCR1_PING_STATUS 0x4010182c -#define CYREG_DMAC_DESCR1_PONG_SRC 0x40101830 -#define CYREG_DMAC_DESCR1_PONG_DST 0x40101834 -#define CYREG_DMAC_DESCR1_PONG_CTL 0x40101838 -#define CYREG_DMAC_DESCR1_PONG_STATUS 0x4010183c -#define CYDEV_DMAC_DESCR2_BASE 0x40101840 -#define CYDEV_DMAC_DESCR2_SIZE 0x00000020 -#define CYREG_DMAC_DESCR2_PING_SRC 0x40101840 -#define CYREG_DMAC_DESCR2_PING_DST 0x40101844 -#define CYREG_DMAC_DESCR2_PING_CTL 0x40101848 -#define CYREG_DMAC_DESCR2_PING_STATUS 0x4010184c -#define CYREG_DMAC_DESCR2_PONG_SRC 0x40101850 -#define CYREG_DMAC_DESCR2_PONG_DST 0x40101854 -#define CYREG_DMAC_DESCR2_PONG_CTL 0x40101858 -#define CYREG_DMAC_DESCR2_PONG_STATUS 0x4010185c -#define CYDEV_DMAC_DESCR3_BASE 0x40101860 -#define CYDEV_DMAC_DESCR3_SIZE 0x00000020 -#define CYREG_DMAC_DESCR3_PING_SRC 0x40101860 -#define CYREG_DMAC_DESCR3_PING_DST 0x40101864 -#define CYREG_DMAC_DESCR3_PING_CTL 0x40101868 -#define CYREG_DMAC_DESCR3_PING_STATUS 0x4010186c -#define CYREG_DMAC_DESCR3_PONG_SRC 0x40101870 -#define CYREG_DMAC_DESCR3_PONG_DST 0x40101874 -#define CYREG_DMAC_DESCR3_PONG_CTL 0x40101878 -#define CYREG_DMAC_DESCR3_PONG_STATUS 0x4010187c -#define CYDEV_DMAC_DESCR4_BASE 0x40101880 -#define CYDEV_DMAC_DESCR4_SIZE 0x00000020 -#define CYREG_DMAC_DESCR4_PING_SRC 0x40101880 -#define CYREG_DMAC_DESCR4_PING_DST 0x40101884 -#define CYREG_DMAC_DESCR4_PING_CTL 0x40101888 -#define CYREG_DMAC_DESCR4_PING_STATUS 0x4010188c -#define CYREG_DMAC_DESCR4_PONG_SRC 0x40101890 -#define CYREG_DMAC_DESCR4_PONG_DST 0x40101894 -#define CYREG_DMAC_DESCR4_PONG_CTL 0x40101898 -#define CYREG_DMAC_DESCR4_PONG_STATUS 0x4010189c -#define CYDEV_DMAC_DESCR5_BASE 0x401018a0 -#define CYDEV_DMAC_DESCR5_SIZE 0x00000020 -#define CYREG_DMAC_DESCR5_PING_SRC 0x401018a0 -#define CYREG_DMAC_DESCR5_PING_DST 0x401018a4 -#define CYREG_DMAC_DESCR5_PING_CTL 0x401018a8 -#define CYREG_DMAC_DESCR5_PING_STATUS 0x401018ac -#define CYREG_DMAC_DESCR5_PONG_SRC 0x401018b0 -#define CYREG_DMAC_DESCR5_PONG_DST 0x401018b4 -#define CYREG_DMAC_DESCR5_PONG_CTL 0x401018b8 -#define CYREG_DMAC_DESCR5_PONG_STATUS 0x401018bc -#define CYDEV_DMAC_DESCR6_BASE 0x401018c0 -#define CYDEV_DMAC_DESCR6_SIZE 0x00000020 -#define CYREG_DMAC_DESCR6_PING_SRC 0x401018c0 -#define CYREG_DMAC_DESCR6_PING_DST 0x401018c4 -#define CYREG_DMAC_DESCR6_PING_CTL 0x401018c8 -#define CYREG_DMAC_DESCR6_PING_STATUS 0x401018cc -#define CYREG_DMAC_DESCR6_PONG_SRC 0x401018d0 -#define CYREG_DMAC_DESCR6_PONG_DST 0x401018d4 -#define CYREG_DMAC_DESCR6_PONG_CTL 0x401018d8 -#define CYREG_DMAC_DESCR6_PONG_STATUS 0x401018dc -#define CYDEV_DMAC_DESCR7_BASE 0x401018e0 -#define CYDEV_DMAC_DESCR7_SIZE 0x00000020 -#define CYREG_DMAC_DESCR7_PING_SRC 0x401018e0 -#define CYREG_DMAC_DESCR7_PING_DST 0x401018e4 -#define CYREG_DMAC_DESCR7_PING_CTL 0x401018e8 -#define CYREG_DMAC_DESCR7_PING_STATUS 0x401018ec -#define CYREG_DMAC_DESCR7_PONG_SRC 0x401018f0 -#define CYREG_DMAC_DESCR7_PONG_DST 0x401018f4 -#define CYREG_DMAC_DESCR7_PONG_CTL 0x401018f8 -#define CYREG_DMAC_DESCR7_PONG_STATUS 0x401018fc #define CYDEV_SPCIF_BASE 0x40110000 #define CYDEV_SPCIF_SIZE 0x00010000 #define CYREG_SPCIF_GEOMETRY 0x40110000 @@ -8077,33 +7340,8 @@ #define CYREG_BLE_BLERD_READ_IQ_4 0x402e010c #define CYFLD_BLE_BLERD_ADC_4__OFFSET 0x00000000 #define CYFLD_BLE_BLERD_ADC_4__SIZE 0x00000020 -#define CYREG_BLE_BLERD_AGC_GAIN_COMP_1 0x402e0180 -#define CYFLD_BLE_BLERD_GAIN_5__OFFSET 0x00000000 -#define CYFLD_BLE_BLERD_GAIN_5__SIZE 0x00000005 -#define CYFLD_BLE_BLERD_GAIN_4__OFFSET 0x00000005 -#define CYFLD_BLE_BLERD_GAIN_4__SIZE 0x00000005 -#define CYFLD_BLE_BLERD_GAIN_3__OFFSET 0x0000000a -#define CYFLD_BLE_BLERD_GAIN_3__SIZE 0x00000005 -#define CYREG_BLE_BLERD_AGC_GAIN_COMP_2 0x402e0184 -#define CYFLD_BLE_BLERD_GAIN_2__OFFSET 0x00000000 -#define CYFLD_BLE_BLERD_GAIN_2__SIZE 0x00000005 -#define CYFLD_BLE_BLERD_GAIN_1__OFFSET 0x00000005 -#define CYFLD_BLE_BLERD_GAIN_1__SIZE 0x00000005 -#define CYFLD_BLE_BLERD_GAIN_0__OFFSET 0x0000000a -#define CYFLD_BLE_BLERD_GAIN_0__SIZE 0x00000005 -#define CYREG_BLE_BLERD_PA_RSSI_NEW 0x402e0188 -#define CYFLD_BLE_BLERD_PA_RAMP_STEP__OFFSET 0x00000000 -#define CYFLD_BLE_BLERD_PA_RAMP_STEP__SIZE 0x00000002 -#define CYFLD_BLE_BLERD_PA_RAMP_NEW__OFFSET 0x00000003 -#define CYFLD_BLE_BLERD_PA_RAMP_NEW__SIZE 0x00000001 -#define CYFLD_BLE_BLERD_MIN_RSSI_NEW__OFFSET 0x00000004 -#define CYFLD_BLE_BLERD_MIN_RSSI_NEW__SIZE 0x00000001 -#define CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__OFFSET 0x00000005 -#define CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__OFFSET 0x00000006 -#define CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__SIZE 0x00000001 #define CYDEV_BLE_BLELL_BASE 0x402e1000 -#define CYDEV_BLE_BLELL_SIZE 0x00003000 +#define CYDEV_BLE_BLELL_SIZE 0x00001000 #define CYREG_BLE_BLELL_COMMAND_REGISTER 0x402e1000 #define CYFLD_BLE_BLELL_COMMAND__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_COMMAND__SIZE 0x00000008 @@ -8150,14 +7388,6 @@ #define CYFLD_BLE_BLELL_RX_ADDR__SIZE 0x00000001 #define CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__OFFSET 0x0000000a #define CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INITA_RPA_CHECK__OFFSET 0x0000000b -#define CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET 0x0000000c -#define CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__OFFSET 0x0000000d -#define CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET 0x0000000e -#define CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE 0x00000001 #define CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET 0x0000000f #define CYFLD_BLE_BLELL_RCV_TX_ADDR__SIZE 0x00000001 #define CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT 0x402e101c @@ -8182,14 +7412,6 @@ #define CYFLD_BLE_BLELL_ADV_TIMEOUT__SIZE 0x00000001 #define CYFLD_BLE_BLELL_ADV_ON__OFFSET 0x00000008 #define CYFLD_BLE_BLELL_ADV_ON__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET 0x0000000a -#define CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x0000000b -#define CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x0000000c -#define CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001 #define CYREG_BLE_BLELL_ADV_NEXT_INSTANT 0x402e1024 #define CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_ADV_NEXT_INSTANT__SIZE 0x00000010 @@ -8206,14 +7428,6 @@ #define CYFLD_BLE_BLELL_SCAN_FILT_POLICY__SIZE 0x00000002 #define CYFLD_BLE_BLELL_DUP_FILT_EN__OFFSET 0x00000005 #define CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET 0x00000008 -#define CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE 0x00000001 #define CYREG_BLE_BLELL_SCAN_INTR 0x402e1038 #define CYFLD_BLE_BLELL_SCAN_STRT_INTR__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_SCAN_STRT_INTR__SIZE 0x00000001 @@ -8225,18 +7439,8 @@ #define CYFLD_BLE_BLELL_ADV_RX_INTR__SIZE 0x00000001 #define CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET 0x00000004 #define CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__OFFSET 0x00000005 -#define CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE 0x00000001 #define CYFLD_BLE_BLELL_SCAN_ON__OFFSET 0x00000008 #define CYFLD_BLE_BLELL_SCAN_ON__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x0000000a -#define CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001 #define CYREG_BLE_BLELL_SCAN_NEXT_INSTANT 0x402e103c #define CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_NEXT_SCAN_INSTANT__SIZE 0x00000010 @@ -8251,8 +7455,6 @@ #define CYFLD_BLE_BLELL_RX_ADDR__RX_TX_ADDR__SIZE 0x00000001 #define CYFLD_BLE_BLELL_INIT_FILT_POLICY__OFFSET 0x00000003 #define CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__OFFSET 0x00000004 -#define CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE 0x00000001 #define CYREG_BLE_BLELL_INIT_INTR 0x402e1050 #define CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_INIT_INTERVAL_EXPIRE_INTR__SIZE 0x00000001 @@ -8262,16 +7464,6 @@ #define CYFLD_BLE_BLELL_INIT_TX_START_INTR__SIZE 0x00000001 #define CYFLD_BLE_BLELL_MASTER_CONN_CREATED__OFFSET 0x00000004 #define CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__OFFSET 0x00000005 -#define CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x00000008 -#define CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE 0x00000001 #define CYREG_BLE_BLELL_INIT_NEXT_INSTANT 0x402e1054 #define CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_INIT_NEXT_INSTANT__SIZE 0x00000010 @@ -8466,7 +7658,7 @@ #define CYFLD_BLE_BLELL_LLID__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_LLID__SIZE 0x00000002 #define CYFLD_BLE_BLELL_DATA_LENGTH__OFFSET 0x00000002 -#define CYFLD_BLE_BLELL_DATA_LENGTH__SIZE 0x00000008 +#define CYFLD_BLE_BLELL_DATA_LENGTH__SIZE 0x00000005 #define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1 0x402e1144 #define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2 0x402e1148 #define CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3 0x402e114c @@ -8489,9 +7681,6 @@ #define CYREG_BLE_BLELL_DTM_RX_PKT_COUNT 0x402e1174 #define CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE 0x00000010 -#define CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT 0x402e1178 -#define CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_TEST_LENGTH_EXT__SIZE 0x00000003 #define CYREG_BLE_BLELL_TXRX_HOP 0x402e1188 #define CYFLD_BLE_BLELL_HOP_CH_TX__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_HOP_CH_TX__SIZE 0x00000007 @@ -8536,10 +7725,6 @@ #define CYFLD_BLE_BLELL_ADV_TIMEOUT_EN__SIZE 0x00000001 #define CYFLD_BLE_BLELL_ADV_RAND_DISABLE__OFFSET 0x00000008 #define CYFLD_BLE_BLELL_ADV_RAND_DISABLE__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__OFFSET 0x0000000a -#define CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__SIZE 0x00000001 #define CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__OFFSET 0x0000000b #define CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__SIZE 0x00000005 #define CYREG_BLE_BLELL_SCAN_CONFIG 0x402e11d8 @@ -8553,14 +7738,6 @@ #define CYFLD_BLE_BLELL_ADV_RX_EN__SIZE 0x00000001 #define CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET 0x00000004 #define CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET 0x00000005 -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET 0x00000008 -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE 0x00000001 #define CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET 0x0000000b #define CYFLD_BLE_BLELL_BACKOFF_ENABLE__SIZE 0x00000001 #define CYFLD_BLE_BLELL_SCAN_CHANNEL_MAP__OFFSET 0x0000000d @@ -8574,12 +7751,6 @@ #define CYFLD_BLE_BLELL_CONN_REQ_TX_EN__SIZE 0x00000001 #define CYFLD_BLE_BLELL_CONN_CREATED__OFFSET 0x00000004 #define CYFLD_BLE_BLELL_CONN_CREATED__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__OFFSET 0x00000005 -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE 0x00000001 #define CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__OFFSET 0x0000000d #define CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__SIZE 0x00000003 #define CYREG_BLE_BLELL_CONN_CONFIG 0x402e11e0 @@ -8791,10 +7962,6 @@ #define CYFLD_BLE_BLELL_PAYLOAD_LENGTH__SIZE 0x00000005 #define CYFLD_BLE_BLELL_DIRECTION__OFFSET 0x00000007 #define CYFLD_BLE_BLELL_DIRECTION__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__OFFSET 0x00000008 -#define CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__SIZE 0x00000003 -#define CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__OFFSET 0x0000000b -#define CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE 0x00000001 #define CYREG_BLE_BLELL_ENC_CONFIG 0x402e1490 #define CYFLD_BLE_BLELL_START_PROC__OFFSET 0x00000000 #define CYFLD_BLE_BLELL_START_PROC__SIZE 0x00000001 @@ -8869,97 +8036,6 @@ #define CYFLD_BLE_BLELL_RX_EN_DELAY__SIZE 0x00000008 #define CYFLD_BLE_BLELL_TX_EN_DELAY__OFFSET 0x00000008 #define CYFLD_BLE_BLELL_TX_EN_DELAY__SIZE 0x00000008 -#define CYREG_BLE_BLELL_LL_CONTROL 0x402e1f00 -#define CYFLD_BLE_BLELL_PRIV_1_2__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_PRIV_1_2__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_DLE__OFFSET 0x00000001 -#define CYFLD_BLE_BLELL_DLE__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_WL_READ_AS_MEM__OFFSET 0x00000002 -#define CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__OFFSET 0x00000003 -#define CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__OFFSET 0x00000004 -#define CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET 0x00000005 -#define CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET 0x00000008 -#define CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET 0x0000000a -#define CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET 0x0000000b -#define CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET 0x0000000c -#define CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__OFFSET 0x0000000d -#define CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__OFFSET 0x0000000e -#define CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__OFFSET 0x0000000f -#define CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE 0x00000001 -#define CYREG_BLE_BLELL_DEV_PA_ADDR_L 0x402e1f04 -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_L__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_L__SIZE 0x00000010 -#define CYREG_BLE_BLELL_DEV_PA_ADDR_M 0x402e1f08 -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_M__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_M__SIZE 0x00000010 -#define CYREG_BLE_BLELL_DEV_PA_ADDR_H 0x402e1f0c -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_H__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_DEV_PA_ADDR_H__SIZE 0x00000010 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 0x402e1f10 -#define CYFLD_BLE_BLELL_VALID_ENTRY__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_VALID_ENTRY__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET 0x00000001 -#define CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET 0x00000002 -#define CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_WHITELISTED_PEER__OFFSET 0x00000003 -#define CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET 0x00000004 -#define CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET 0x00000005 -#define CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET 0x00000006 -#define CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET 0x00000007 -#define CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET 0x00000008 -#define CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE 0x00000001 -#define CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET 0x00000009 -#define CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE 0x00000001 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 0x402e1f14 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 0x402e1f18 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 0x402e1f1c -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 0x402e1f20 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 0x402e1f24 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 0x402e1f28 -#define CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 0x402e1f2c -#define CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR 0x402e2000 -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE 0x00000010 -#define CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR 0x402e2060 -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE 0x00000010 -#define CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR 0x402e20c0 -#define CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE 0x00000010 -#define CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR 0x402e2120 -#define CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE 0x00000010 -#define CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR 0x402e2200 -#define CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__SIZE 0x00000010 -#define CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE 0x402e2800 -#define CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__SIZE 0x00000010 -#define CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE 0x402e3000 -#define CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__OFFSET 0x00000000 -#define CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__SIZE 0x00000010 #define CYDEV_BLE_BLESS_BASE 0x402ef000 #define CYDEV_BLE_BLESS_SIZE 0x00001000 #define CYREG_BLE_BLESS_WCO_CONFIG 0x402ef000 @@ -9016,8 +8092,6 @@ #define CYREG_BLE_BLESS_LF_CLK_CTRL 0x402ef074 #define CYFLD_BLE_BLESS_DISABLE_LF_CLK__OFFSET 0x00000000 #define CYFLD_BLE_BLESS_DISABLE_LF_CLK__SIZE 0x00000001 -#define CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__OFFSET 0x0000001d -#define CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__SIZE 0x00000003 #define CYREG_BLE_BLESS_WCO_TRIM 0x402eff00 #define CYFLD_BLE_BLESS_XGM__OFFSET 0x00000000 #define CYFLD_BLE_BLESS_XGM__SIZE 0x00000003 @@ -9913,8 +8987,8 @@ #define CYREG_ROMTABLE_CID1 0xf0000ff4 #define CYREG_ROMTABLE_CID2 0xf0000ff8 #define CYREG_ROMTABLE_CID3 0xf0000ffc -#define CYDEV_FLS_SECTOR_SIZE 0x00020000 -#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000080 #define CYREG_SFLASH_PROT_ROW00 CYREG_SFLASH_PROT_ROW0 #define CYREG_SFLASH_PROT_ROW01 CYREG_SFLASH_PROT_ROW1 #define CYREG_SFLASH_PROT_ROW02 CYREG_SFLASH_PROT_ROW2 diff --git a/BLE.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc b/BLE.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc index 96929d7..7422689 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc +++ b/BLE.cydsn/Generated_Source/PSoC4/cydevicerv_trm.inc @@ -17,19 +17,19 @@ CYDEV_FLASH_BASE EQU 0x00000000 ENDIF IF :LNOT::DEF:CYDEV_FLASH_SIZE -CYDEV_FLASH_SIZE EQU 0x00040000 +CYDEV_FLASH_SIZE EQU 0x00020000 ENDIF IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE CYREG_FLASH_DATA_MBASE EQU 0x00000000 ENDIF IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE -CYREG_FLASH_DATA_MSIZE EQU 0x00040000 +CYREG_FLASH_DATA_MSIZE EQU 0x00020000 ENDIF IF :LNOT::DEF:CYDEV_SFLASH_BASE CYDEV_SFLASH_BASE EQU 0x0ffff000 ENDIF IF :LNOT::DEF:CYDEV_SFLASH_SIZE -CYDEV_SFLASH_SIZE EQU 0x00001000 +CYDEV_SFLASH_SIZE EQU 0x00000800 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW0 CYREG_SFLASH_PROT_ROW0 EQU 0x0ffff000 @@ -230,7 +230,7 @@ CYREG_SFLASH_PROT_ROW62 EQU 0x0ffff03e CYREG_SFLASH_PROT_ROW63 EQU 0x0ffff03f ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_PROTECTION -CYREG_SFLASH_PROT_PROTECTION EQU 0x0ffff0ff +CYREG_SFLASH_PROT_PROTECTION EQU 0x0ffff07f ENDIF IF :LNOT::DEF:CYFLD_SFLASH_PROT_LEVEL__OFFSET CYFLD_SFLASH_PROT_LEVEL__OFFSET EQU 0x00000000 @@ -251,271 +251,271 @@ CYVAL_SFLASH_PROT_LEVEL_PROTECTED EQU 0x00000002 CYVAL_SFLASH_PROT_LEVEL_KILL EQU 0x00000003 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B0 -CYREG_SFLASH_AV_PAIRS_8B0 EQU 0x0ffff100 +CYREG_SFLASH_AV_PAIRS_8B0 EQU 0x0ffff080 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B1 -CYREG_SFLASH_AV_PAIRS_8B1 EQU 0x0ffff101 +CYREG_SFLASH_AV_PAIRS_8B1 EQU 0x0ffff081 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B2 -CYREG_SFLASH_AV_PAIRS_8B2 EQU 0x0ffff102 +CYREG_SFLASH_AV_PAIRS_8B2 EQU 0x0ffff082 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B3 -CYREG_SFLASH_AV_PAIRS_8B3 EQU 0x0ffff103 +CYREG_SFLASH_AV_PAIRS_8B3 EQU 0x0ffff083 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B4 -CYREG_SFLASH_AV_PAIRS_8B4 EQU 0x0ffff104 +CYREG_SFLASH_AV_PAIRS_8B4 EQU 0x0ffff084 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B5 -CYREG_SFLASH_AV_PAIRS_8B5 EQU 0x0ffff105 +CYREG_SFLASH_AV_PAIRS_8B5 EQU 0x0ffff085 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B6 -CYREG_SFLASH_AV_PAIRS_8B6 EQU 0x0ffff106 +CYREG_SFLASH_AV_PAIRS_8B6 EQU 0x0ffff086 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B7 -CYREG_SFLASH_AV_PAIRS_8B7 EQU 0x0ffff107 +CYREG_SFLASH_AV_PAIRS_8B7 EQU 0x0ffff087 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B8 -CYREG_SFLASH_AV_PAIRS_8B8 EQU 0x0ffff108 +CYREG_SFLASH_AV_PAIRS_8B8 EQU 0x0ffff088 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B9 -CYREG_SFLASH_AV_PAIRS_8B9 EQU 0x0ffff109 +CYREG_SFLASH_AV_PAIRS_8B9 EQU 0x0ffff089 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B10 -CYREG_SFLASH_AV_PAIRS_8B10 EQU 0x0ffff10a +CYREG_SFLASH_AV_PAIRS_8B10 EQU 0x0ffff08a ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B11 -CYREG_SFLASH_AV_PAIRS_8B11 EQU 0x0ffff10b +CYREG_SFLASH_AV_PAIRS_8B11 EQU 0x0ffff08b ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B12 -CYREG_SFLASH_AV_PAIRS_8B12 EQU 0x0ffff10c +CYREG_SFLASH_AV_PAIRS_8B12 EQU 0x0ffff08c ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B13 -CYREG_SFLASH_AV_PAIRS_8B13 EQU 0x0ffff10d +CYREG_SFLASH_AV_PAIRS_8B13 EQU 0x0ffff08d ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B14 -CYREG_SFLASH_AV_PAIRS_8B14 EQU 0x0ffff10e +CYREG_SFLASH_AV_PAIRS_8B14 EQU 0x0ffff08e ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B15 -CYREG_SFLASH_AV_PAIRS_8B15 EQU 0x0ffff10f +CYREG_SFLASH_AV_PAIRS_8B15 EQU 0x0ffff08f ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B16 -CYREG_SFLASH_AV_PAIRS_8B16 EQU 0x0ffff110 +CYREG_SFLASH_AV_PAIRS_8B16 EQU 0x0ffff090 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B17 -CYREG_SFLASH_AV_PAIRS_8B17 EQU 0x0ffff111 +CYREG_SFLASH_AV_PAIRS_8B17 EQU 0x0ffff091 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B18 -CYREG_SFLASH_AV_PAIRS_8B18 EQU 0x0ffff112 +CYREG_SFLASH_AV_PAIRS_8B18 EQU 0x0ffff092 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B19 -CYREG_SFLASH_AV_PAIRS_8B19 EQU 0x0ffff113 +CYREG_SFLASH_AV_PAIRS_8B19 EQU 0x0ffff093 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B20 -CYREG_SFLASH_AV_PAIRS_8B20 EQU 0x0ffff114 +CYREG_SFLASH_AV_PAIRS_8B20 EQU 0x0ffff094 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B21 -CYREG_SFLASH_AV_PAIRS_8B21 EQU 0x0ffff115 +CYREG_SFLASH_AV_PAIRS_8B21 EQU 0x0ffff095 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B22 -CYREG_SFLASH_AV_PAIRS_8B22 EQU 0x0ffff116 +CYREG_SFLASH_AV_PAIRS_8B22 EQU 0x0ffff096 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B23 -CYREG_SFLASH_AV_PAIRS_8B23 EQU 0x0ffff117 +CYREG_SFLASH_AV_PAIRS_8B23 EQU 0x0ffff097 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B24 -CYREG_SFLASH_AV_PAIRS_8B24 EQU 0x0ffff118 +CYREG_SFLASH_AV_PAIRS_8B24 EQU 0x0ffff098 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B25 -CYREG_SFLASH_AV_PAIRS_8B25 EQU 0x0ffff119 +CYREG_SFLASH_AV_PAIRS_8B25 EQU 0x0ffff099 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B26 -CYREG_SFLASH_AV_PAIRS_8B26 EQU 0x0ffff11a +CYREG_SFLASH_AV_PAIRS_8B26 EQU 0x0ffff09a ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B27 -CYREG_SFLASH_AV_PAIRS_8B27 EQU 0x0ffff11b +CYREG_SFLASH_AV_PAIRS_8B27 EQU 0x0ffff09b ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B28 -CYREG_SFLASH_AV_PAIRS_8B28 EQU 0x0ffff11c +CYREG_SFLASH_AV_PAIRS_8B28 EQU 0x0ffff09c ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B29 -CYREG_SFLASH_AV_PAIRS_8B29 EQU 0x0ffff11d +CYREG_SFLASH_AV_PAIRS_8B29 EQU 0x0ffff09d ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B30 -CYREG_SFLASH_AV_PAIRS_8B30 EQU 0x0ffff11e +CYREG_SFLASH_AV_PAIRS_8B30 EQU 0x0ffff09e ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B31 -CYREG_SFLASH_AV_PAIRS_8B31 EQU 0x0ffff11f +CYREG_SFLASH_AV_PAIRS_8B31 EQU 0x0ffff09f ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B32 -CYREG_SFLASH_AV_PAIRS_8B32 EQU 0x0ffff120 +CYREG_SFLASH_AV_PAIRS_8B32 EQU 0x0ffff0a0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B33 -CYREG_SFLASH_AV_PAIRS_8B33 EQU 0x0ffff121 +CYREG_SFLASH_AV_PAIRS_8B33 EQU 0x0ffff0a1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B34 -CYREG_SFLASH_AV_PAIRS_8B34 EQU 0x0ffff122 +CYREG_SFLASH_AV_PAIRS_8B34 EQU 0x0ffff0a2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B35 -CYREG_SFLASH_AV_PAIRS_8B35 EQU 0x0ffff123 +CYREG_SFLASH_AV_PAIRS_8B35 EQU 0x0ffff0a3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B36 -CYREG_SFLASH_AV_PAIRS_8B36 EQU 0x0ffff124 +CYREG_SFLASH_AV_PAIRS_8B36 EQU 0x0ffff0a4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B37 -CYREG_SFLASH_AV_PAIRS_8B37 EQU 0x0ffff125 +CYREG_SFLASH_AV_PAIRS_8B37 EQU 0x0ffff0a5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B38 -CYREG_SFLASH_AV_PAIRS_8B38 EQU 0x0ffff126 +CYREG_SFLASH_AV_PAIRS_8B38 EQU 0x0ffff0a6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B39 -CYREG_SFLASH_AV_PAIRS_8B39 EQU 0x0ffff127 +CYREG_SFLASH_AV_PAIRS_8B39 EQU 0x0ffff0a7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B40 -CYREG_SFLASH_AV_PAIRS_8B40 EQU 0x0ffff128 +CYREG_SFLASH_AV_PAIRS_8B40 EQU 0x0ffff0a8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B41 -CYREG_SFLASH_AV_PAIRS_8B41 EQU 0x0ffff129 +CYREG_SFLASH_AV_PAIRS_8B41 EQU 0x0ffff0a9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B42 -CYREG_SFLASH_AV_PAIRS_8B42 EQU 0x0ffff12a +CYREG_SFLASH_AV_PAIRS_8B42 EQU 0x0ffff0aa ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B43 -CYREG_SFLASH_AV_PAIRS_8B43 EQU 0x0ffff12b +CYREG_SFLASH_AV_PAIRS_8B43 EQU 0x0ffff0ab ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B44 -CYREG_SFLASH_AV_PAIRS_8B44 EQU 0x0ffff12c +CYREG_SFLASH_AV_PAIRS_8B44 EQU 0x0ffff0ac ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B45 -CYREG_SFLASH_AV_PAIRS_8B45 EQU 0x0ffff12d +CYREG_SFLASH_AV_PAIRS_8B45 EQU 0x0ffff0ad ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B46 -CYREG_SFLASH_AV_PAIRS_8B46 EQU 0x0ffff12e +CYREG_SFLASH_AV_PAIRS_8B46 EQU 0x0ffff0ae ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B47 -CYREG_SFLASH_AV_PAIRS_8B47 EQU 0x0ffff12f +CYREG_SFLASH_AV_PAIRS_8B47 EQU 0x0ffff0af ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B48 -CYREG_SFLASH_AV_PAIRS_8B48 EQU 0x0ffff130 +CYREG_SFLASH_AV_PAIRS_8B48 EQU 0x0ffff0b0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B49 -CYREG_SFLASH_AV_PAIRS_8B49 EQU 0x0ffff131 +CYREG_SFLASH_AV_PAIRS_8B49 EQU 0x0ffff0b1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B50 -CYREG_SFLASH_AV_PAIRS_8B50 EQU 0x0ffff132 +CYREG_SFLASH_AV_PAIRS_8B50 EQU 0x0ffff0b2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B51 -CYREG_SFLASH_AV_PAIRS_8B51 EQU 0x0ffff133 +CYREG_SFLASH_AV_PAIRS_8B51 EQU 0x0ffff0b3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B52 -CYREG_SFLASH_AV_PAIRS_8B52 EQU 0x0ffff134 +CYREG_SFLASH_AV_PAIRS_8B52 EQU 0x0ffff0b4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B53 -CYREG_SFLASH_AV_PAIRS_8B53 EQU 0x0ffff135 +CYREG_SFLASH_AV_PAIRS_8B53 EQU 0x0ffff0b5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B54 -CYREG_SFLASH_AV_PAIRS_8B54 EQU 0x0ffff136 +CYREG_SFLASH_AV_PAIRS_8B54 EQU 0x0ffff0b6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B55 -CYREG_SFLASH_AV_PAIRS_8B55 EQU 0x0ffff137 +CYREG_SFLASH_AV_PAIRS_8B55 EQU 0x0ffff0b7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B56 -CYREG_SFLASH_AV_PAIRS_8B56 EQU 0x0ffff138 +CYREG_SFLASH_AV_PAIRS_8B56 EQU 0x0ffff0b8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B57 -CYREG_SFLASH_AV_PAIRS_8B57 EQU 0x0ffff139 +CYREG_SFLASH_AV_PAIRS_8B57 EQU 0x0ffff0b9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B58 -CYREG_SFLASH_AV_PAIRS_8B58 EQU 0x0ffff13a +CYREG_SFLASH_AV_PAIRS_8B58 EQU 0x0ffff0ba ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B59 -CYREG_SFLASH_AV_PAIRS_8B59 EQU 0x0ffff13b +CYREG_SFLASH_AV_PAIRS_8B59 EQU 0x0ffff0bb ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B60 -CYREG_SFLASH_AV_PAIRS_8B60 EQU 0x0ffff13c +CYREG_SFLASH_AV_PAIRS_8B60 EQU 0x0ffff0bc ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B61 -CYREG_SFLASH_AV_PAIRS_8B61 EQU 0x0ffff13d +CYREG_SFLASH_AV_PAIRS_8B61 EQU 0x0ffff0bd ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B62 -CYREG_SFLASH_AV_PAIRS_8B62 EQU 0x0ffff13e +CYREG_SFLASH_AV_PAIRS_8B62 EQU 0x0ffff0be ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B63 -CYREG_SFLASH_AV_PAIRS_8B63 EQU 0x0ffff13f +CYREG_SFLASH_AV_PAIRS_8B63 EQU 0x0ffff0bf ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B64 -CYREG_SFLASH_AV_PAIRS_8B64 EQU 0x0ffff140 +CYREG_SFLASH_AV_PAIRS_8B64 EQU 0x0ffff0c0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B65 -CYREG_SFLASH_AV_PAIRS_8B65 EQU 0x0ffff141 +CYREG_SFLASH_AV_PAIRS_8B65 EQU 0x0ffff0c1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B66 -CYREG_SFLASH_AV_PAIRS_8B66 EQU 0x0ffff142 +CYREG_SFLASH_AV_PAIRS_8B66 EQU 0x0ffff0c2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B67 -CYREG_SFLASH_AV_PAIRS_8B67 EQU 0x0ffff143 +CYREG_SFLASH_AV_PAIRS_8B67 EQU 0x0ffff0c3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B68 -CYREG_SFLASH_AV_PAIRS_8B68 EQU 0x0ffff144 +CYREG_SFLASH_AV_PAIRS_8B68 EQU 0x0ffff0c4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B69 -CYREG_SFLASH_AV_PAIRS_8B69 EQU 0x0ffff145 +CYREG_SFLASH_AV_PAIRS_8B69 EQU 0x0ffff0c5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B70 -CYREG_SFLASH_AV_PAIRS_8B70 EQU 0x0ffff146 +CYREG_SFLASH_AV_PAIRS_8B70 EQU 0x0ffff0c6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B71 -CYREG_SFLASH_AV_PAIRS_8B71 EQU 0x0ffff147 +CYREG_SFLASH_AV_PAIRS_8B71 EQU 0x0ffff0c7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B72 -CYREG_SFLASH_AV_PAIRS_8B72 EQU 0x0ffff148 +CYREG_SFLASH_AV_PAIRS_8B72 EQU 0x0ffff0c8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B73 -CYREG_SFLASH_AV_PAIRS_8B73 EQU 0x0ffff149 +CYREG_SFLASH_AV_PAIRS_8B73 EQU 0x0ffff0c9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B74 -CYREG_SFLASH_AV_PAIRS_8B74 EQU 0x0ffff14a +CYREG_SFLASH_AV_PAIRS_8B74 EQU 0x0ffff0ca ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B75 -CYREG_SFLASH_AV_PAIRS_8B75 EQU 0x0ffff14b +CYREG_SFLASH_AV_PAIRS_8B75 EQU 0x0ffff0cb ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B76 -CYREG_SFLASH_AV_PAIRS_8B76 EQU 0x0ffff14c +CYREG_SFLASH_AV_PAIRS_8B76 EQU 0x0ffff0cc ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B77 -CYREG_SFLASH_AV_PAIRS_8B77 EQU 0x0ffff14d +CYREG_SFLASH_AV_PAIRS_8B77 EQU 0x0ffff0cd ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B78 -CYREG_SFLASH_AV_PAIRS_8B78 EQU 0x0ffff14e +CYREG_SFLASH_AV_PAIRS_8B78 EQU 0x0ffff0ce ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B79 -CYREG_SFLASH_AV_PAIRS_8B79 EQU 0x0ffff14f +CYREG_SFLASH_AV_PAIRS_8B79 EQU 0x0ffff0cf ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B80 -CYREG_SFLASH_AV_PAIRS_8B80 EQU 0x0ffff150 +CYREG_SFLASH_AV_PAIRS_8B80 EQU 0x0ffff0d0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B81 -CYREG_SFLASH_AV_PAIRS_8B81 EQU 0x0ffff151 +CYREG_SFLASH_AV_PAIRS_8B81 EQU 0x0ffff0d1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B82 -CYREG_SFLASH_AV_PAIRS_8B82 EQU 0x0ffff152 +CYREG_SFLASH_AV_PAIRS_8B82 EQU 0x0ffff0d2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B83 -CYREG_SFLASH_AV_PAIRS_8B83 EQU 0x0ffff153 +CYREG_SFLASH_AV_PAIRS_8B83 EQU 0x0ffff0d3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B84 -CYREG_SFLASH_AV_PAIRS_8B84 EQU 0x0ffff154 +CYREG_SFLASH_AV_PAIRS_8B84 EQU 0x0ffff0d4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B85 -CYREG_SFLASH_AV_PAIRS_8B85 EQU 0x0ffff155 +CYREG_SFLASH_AV_PAIRS_8B85 EQU 0x0ffff0d5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B86 -CYREG_SFLASH_AV_PAIRS_8B86 EQU 0x0ffff156 +CYREG_SFLASH_AV_PAIRS_8B86 EQU 0x0ffff0d6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B87 -CYREG_SFLASH_AV_PAIRS_8B87 EQU 0x0ffff157 +CYREG_SFLASH_AV_PAIRS_8B87 EQU 0x0ffff0d7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_BLESS_BB_BUMP2 -CYREG_SFLASH_BLESS_BB_BUMP2 EQU 0x0ffff158 +CYREG_SFLASH_BLESS_BB_BUMP2 EQU 0x0ffff0d8 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_V2I_RCAL__OFFSET CYFLD_SFLASH_V2I_RCAL__OFFSET EQU 0x00000000 @@ -542,13 +542,13 @@ CYFLD_SFLASH_SY_IBIAS__OFFSET EQU 0x0000000d CYFLD_SFLASH_SY_IBIAS__SIZE EQU 0x00000003 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B88 -CYREG_SFLASH_AV_PAIRS_8B88 EQU 0x0ffff158 +CYREG_SFLASH_AV_PAIRS_8B88 EQU 0x0ffff0d8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B89 -CYREG_SFLASH_AV_PAIRS_8B89 EQU 0x0ffff159 +CYREG_SFLASH_AV_PAIRS_8B89 EQU 0x0ffff0d9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_BLESS_BB_XO -CYREG_SFLASH_BLESS_BB_XO EQU 0x0ffff15a +CYREG_SFLASH_BLESS_BB_XO EQU 0x0ffff0da ENDIF IF :LNOT::DEF:CYFLD_SFLASH_DIS_XOCORE_SUPFILT__OFFSET CYFLD_SFLASH_DIS_XOCORE_SUPFILT__OFFSET EQU 0x00000000 @@ -611,16 +611,16 @@ CYFLD_SFLASH_rev_bb_xo__OFFSET EQU 0x0000000f CYFLD_SFLASH_rev_bb_xo__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B90 -CYREG_SFLASH_AV_PAIRS_8B90 EQU 0x0ffff15a +CYREG_SFLASH_AV_PAIRS_8B90 EQU 0x0ffff0da ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B91 -CYREG_SFLASH_AV_PAIRS_8B91 EQU 0x0ffff15b +CYREG_SFLASH_AV_PAIRS_8B91 EQU 0x0ffff0db ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B92 -CYREG_SFLASH_AV_PAIRS_8B92 EQU 0x0ffff15c +CYREG_SFLASH_AV_PAIRS_8B92 EQU 0x0ffff0dc ENDIF IF :LNOT::DEF:CYREG_SFLASH_BLESS_SY_BUMP1 -CYREG_SFLASH_BLESS_SY_BUMP1 EQU 0x0ffff15c +CYREG_SFLASH_BLESS_SY_BUMP1 EQU 0x0ffff0dc ENDIF IF :LNOT::DEF:CYFLD_SFLASH_VCO__OFFSET CYFLD_SFLASH_VCO__OFFSET EQU 0x00000000 @@ -659,13 +659,13 @@ CYFLD_SFLASH_PDCPLPF__OFFSET EQU 0x0000000c CYFLD_SFLASH_PDCPLPF__SIZE EQU 0x00000004 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B93 -CYREG_SFLASH_AV_PAIRS_8B93 EQU 0x0ffff15d +CYREG_SFLASH_AV_PAIRS_8B93 EQU 0x0ffff0dd ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B94 -CYREG_SFLASH_AV_PAIRS_8B94 EQU 0x0ffff15e +CYREG_SFLASH_AV_PAIRS_8B94 EQU 0x0ffff0de ENDIF IF :LNOT::DEF:CYREG_SFLASH_BLESS_LDO -CYREG_SFLASH_BLESS_LDO EQU 0x0ffff15e +CYREG_SFLASH_BLESS_LDO EQU 0x0ffff0de ENDIF IF :LNOT::DEF:CYFLD_SFLASH_BUMP_BALUM_HF__OFFSET CYFLD_SFLASH_BUMP_BALUM_HF__OFFSET EQU 0x00000000 @@ -704,106 +704,106 @@ CYFLD_SFLASH_REV_LDO__OFFSET EQU 0x0000000c CYFLD_SFLASH_REV_LDO__SIZE EQU 0x00000004 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B95 -CYREG_SFLASH_AV_PAIRS_8B95 EQU 0x0ffff15f +CYREG_SFLASH_AV_PAIRS_8B95 EQU 0x0ffff0df ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B96 -CYREG_SFLASH_AV_PAIRS_8B96 EQU 0x0ffff160 +CYREG_SFLASH_AV_PAIRS_8B96 EQU 0x0ffff0e0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B97 -CYREG_SFLASH_AV_PAIRS_8B97 EQU 0x0ffff161 +CYREG_SFLASH_AV_PAIRS_8B97 EQU 0x0ffff0e1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B98 -CYREG_SFLASH_AV_PAIRS_8B98 EQU 0x0ffff162 +CYREG_SFLASH_AV_PAIRS_8B98 EQU 0x0ffff0e2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B99 -CYREG_SFLASH_AV_PAIRS_8B99 EQU 0x0ffff163 +CYREG_SFLASH_AV_PAIRS_8B99 EQU 0x0ffff0e3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B100 -CYREG_SFLASH_AV_PAIRS_8B100 EQU 0x0ffff164 +CYREG_SFLASH_AV_PAIRS_8B100 EQU 0x0ffff0e4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B101 -CYREG_SFLASH_AV_PAIRS_8B101 EQU 0x0ffff165 +CYREG_SFLASH_AV_PAIRS_8B101 EQU 0x0ffff0e5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B102 -CYREG_SFLASH_AV_PAIRS_8B102 EQU 0x0ffff166 +CYREG_SFLASH_AV_PAIRS_8B102 EQU 0x0ffff0e6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B103 -CYREG_SFLASH_AV_PAIRS_8B103 EQU 0x0ffff167 +CYREG_SFLASH_AV_PAIRS_8B103 EQU 0x0ffff0e7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B104 -CYREG_SFLASH_AV_PAIRS_8B104 EQU 0x0ffff168 +CYREG_SFLASH_AV_PAIRS_8B104 EQU 0x0ffff0e8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B105 -CYREG_SFLASH_AV_PAIRS_8B105 EQU 0x0ffff169 +CYREG_SFLASH_AV_PAIRS_8B105 EQU 0x0ffff0e9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B106 -CYREG_SFLASH_AV_PAIRS_8B106 EQU 0x0ffff16a +CYREG_SFLASH_AV_PAIRS_8B106 EQU 0x0ffff0ea ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B107 -CYREG_SFLASH_AV_PAIRS_8B107 EQU 0x0ffff16b +CYREG_SFLASH_AV_PAIRS_8B107 EQU 0x0ffff0eb ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B108 -CYREG_SFLASH_AV_PAIRS_8B108 EQU 0x0ffff16c +CYREG_SFLASH_AV_PAIRS_8B108 EQU 0x0ffff0ec ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B109 -CYREG_SFLASH_AV_PAIRS_8B109 EQU 0x0ffff16d +CYREG_SFLASH_AV_PAIRS_8B109 EQU 0x0ffff0ed ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B110 -CYREG_SFLASH_AV_PAIRS_8B110 EQU 0x0ffff16e +CYREG_SFLASH_AV_PAIRS_8B110 EQU 0x0ffff0ee ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B111 -CYREG_SFLASH_AV_PAIRS_8B111 EQU 0x0ffff16f +CYREG_SFLASH_AV_PAIRS_8B111 EQU 0x0ffff0ef ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B112 -CYREG_SFLASH_AV_PAIRS_8B112 EQU 0x0ffff170 +CYREG_SFLASH_AV_PAIRS_8B112 EQU 0x0ffff0f0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B113 -CYREG_SFLASH_AV_PAIRS_8B113 EQU 0x0ffff171 +CYREG_SFLASH_AV_PAIRS_8B113 EQU 0x0ffff0f1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B114 -CYREG_SFLASH_AV_PAIRS_8B114 EQU 0x0ffff172 +CYREG_SFLASH_AV_PAIRS_8B114 EQU 0x0ffff0f2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B115 -CYREG_SFLASH_AV_PAIRS_8B115 EQU 0x0ffff173 +CYREG_SFLASH_AV_PAIRS_8B115 EQU 0x0ffff0f3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B116 -CYREG_SFLASH_AV_PAIRS_8B116 EQU 0x0ffff174 +CYREG_SFLASH_AV_PAIRS_8B116 EQU 0x0ffff0f4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B117 -CYREG_SFLASH_AV_PAIRS_8B117 EQU 0x0ffff175 +CYREG_SFLASH_AV_PAIRS_8B117 EQU 0x0ffff0f5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B118 -CYREG_SFLASH_AV_PAIRS_8B118 EQU 0x0ffff176 +CYREG_SFLASH_AV_PAIRS_8B118 EQU 0x0ffff0f6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B119 -CYREG_SFLASH_AV_PAIRS_8B119 EQU 0x0ffff177 +CYREG_SFLASH_AV_PAIRS_8B119 EQU 0x0ffff0f7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B120 -CYREG_SFLASH_AV_PAIRS_8B120 EQU 0x0ffff178 +CYREG_SFLASH_AV_PAIRS_8B120 EQU 0x0ffff0f8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B121 -CYREG_SFLASH_AV_PAIRS_8B121 EQU 0x0ffff179 +CYREG_SFLASH_AV_PAIRS_8B121 EQU 0x0ffff0f9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B122 -CYREG_SFLASH_AV_PAIRS_8B122 EQU 0x0ffff17a +CYREG_SFLASH_AV_PAIRS_8B122 EQU 0x0ffff0fa ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B123 -CYREG_SFLASH_AV_PAIRS_8B123 EQU 0x0ffff17b +CYREG_SFLASH_AV_PAIRS_8B123 EQU 0x0ffff0fb ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B124 -CYREG_SFLASH_AV_PAIRS_8B124 EQU 0x0ffff17c +CYREG_SFLASH_AV_PAIRS_8B124 EQU 0x0ffff0fc ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B125 -CYREG_SFLASH_AV_PAIRS_8B125 EQU 0x0ffff17d +CYREG_SFLASH_AV_PAIRS_8B125 EQU 0x0ffff0fd ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B126 -CYREG_SFLASH_AV_PAIRS_8B126 EQU 0x0ffff17e +CYREG_SFLASH_AV_PAIRS_8B126 EQU 0x0ffff0fe ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_8B127 -CYREG_SFLASH_AV_PAIRS_8B127 EQU 0x0ffff17f +CYREG_SFLASH_AV_PAIRS_8B127 EQU 0x0ffff0ff ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B0 -CYREG_SFLASH_AV_PAIRS_32B0 EQU 0x0ffff200 +CYREG_SFLASH_AV_PAIRS_32B0 EQU 0x0ffff100 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_DATA32__OFFSET CYFLD_SFLASH_DATA32__OFFSET EQU 0x00000000 @@ -812,52 +812,52 @@ CYFLD_SFLASH_DATA32__OFFSET EQU 0x00000000 CYFLD_SFLASH_DATA32__SIZE EQU 0x00000020 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B1 -CYREG_SFLASH_AV_PAIRS_32B1 EQU 0x0ffff204 +CYREG_SFLASH_AV_PAIRS_32B1 EQU 0x0ffff104 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B2 -CYREG_SFLASH_AV_PAIRS_32B2 EQU 0x0ffff208 +CYREG_SFLASH_AV_PAIRS_32B2 EQU 0x0ffff108 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B3 -CYREG_SFLASH_AV_PAIRS_32B3 EQU 0x0ffff20c +CYREG_SFLASH_AV_PAIRS_32B3 EQU 0x0ffff10c ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B4 -CYREG_SFLASH_AV_PAIRS_32B4 EQU 0x0ffff210 +CYREG_SFLASH_AV_PAIRS_32B4 EQU 0x0ffff110 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B5 -CYREG_SFLASH_AV_PAIRS_32B5 EQU 0x0ffff214 +CYREG_SFLASH_AV_PAIRS_32B5 EQU 0x0ffff114 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B6 -CYREG_SFLASH_AV_PAIRS_32B6 EQU 0x0ffff218 +CYREG_SFLASH_AV_PAIRS_32B6 EQU 0x0ffff118 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B7 -CYREG_SFLASH_AV_PAIRS_32B7 EQU 0x0ffff21c +CYREG_SFLASH_AV_PAIRS_32B7 EQU 0x0ffff11c ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B8 -CYREG_SFLASH_AV_PAIRS_32B8 EQU 0x0ffff220 +CYREG_SFLASH_AV_PAIRS_32B8 EQU 0x0ffff120 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B9 -CYREG_SFLASH_AV_PAIRS_32B9 EQU 0x0ffff224 +CYREG_SFLASH_AV_PAIRS_32B9 EQU 0x0ffff124 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B10 -CYREG_SFLASH_AV_PAIRS_32B10 EQU 0x0ffff228 +CYREG_SFLASH_AV_PAIRS_32B10 EQU 0x0ffff128 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B11 -CYREG_SFLASH_AV_PAIRS_32B11 EQU 0x0ffff22c +CYREG_SFLASH_AV_PAIRS_32B11 EQU 0x0ffff12c ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B12 -CYREG_SFLASH_AV_PAIRS_32B12 EQU 0x0ffff230 +CYREG_SFLASH_AV_PAIRS_32B12 EQU 0x0ffff130 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B13 -CYREG_SFLASH_AV_PAIRS_32B13 EQU 0x0ffff234 +CYREG_SFLASH_AV_PAIRS_32B13 EQU 0x0ffff134 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B14 -CYREG_SFLASH_AV_PAIRS_32B14 EQU 0x0ffff238 +CYREG_SFLASH_AV_PAIRS_32B14 EQU 0x0ffff138 ENDIF IF :LNOT::DEF:CYREG_SFLASH_AV_PAIRS_32B15 -CYREG_SFLASH_AV_PAIRS_32B15 EQU 0x0ffff23c +CYREG_SFLASH_AV_PAIRS_32B15 EQU 0x0ffff13c ENDIF IF :LNOT::DEF:CYREG_SFLASH_SILICON_ID -CYREG_SFLASH_SILICON_ID EQU 0x0ffff244 +CYREG_SFLASH_SILICON_ID EQU 0x0ffff144 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_ID__OFFSET CYFLD_SFLASH_ID__OFFSET EQU 0x00000000 @@ -866,7 +866,7 @@ CYFLD_SFLASH_ID__OFFSET EQU 0x00000000 CYFLD_SFLASH_ID__SIZE EQU 0x00000010 ENDIF IF :LNOT::DEF:CYREG_SFLASH_HIB_KEY_DELAY -CYREG_SFLASH_HIB_KEY_DELAY EQU 0x0ffff250 +CYREG_SFLASH_HIB_KEY_DELAY EQU 0x0ffff150 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 @@ -875,10 +875,10 @@ CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET EQU 0x00000000 CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE EQU 0x0000000a ENDIF IF :LNOT::DEF:CYREG_SFLASH_DPSLP_KEY_DELAY -CYREG_SFLASH_DPSLP_KEY_DELAY EQU 0x0ffff252 +CYREG_SFLASH_DPSLP_KEY_DELAY EQU 0x0ffff152 ENDIF IF :LNOT::DEF:CYREG_SFLASH_SWD_CONFIG -CYREG_SFLASH_SWD_CONFIG EQU 0x0ffff254 +CYREG_SFLASH_SWD_CONFIG EQU 0x0ffff154 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_SWD_SELECT__OFFSET CYFLD_SFLASH_SWD_SELECT__OFFSET EQU 0x00000000 @@ -887,7 +887,7 @@ CYFLD_SFLASH_SWD_SELECT__OFFSET EQU 0x00000000 CYFLD_SFLASH_SWD_SELECT__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 -CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 EQU 0x0ffff255 +CYREG_SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0 EQU 0x0ffff155 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_IDAC__OFFSET CYFLD_SFLASH_IDAC__OFFSET EQU 0x00000000 @@ -902,7 +902,7 @@ CYFLD_SFLASH_SLOPE__OFFSET EQU 0x00000005 CYFLD_SFLASH_SLOPE__SIZE EQU 0x00000003 ENDIF IF :LNOT::DEF:CYREG_SFLASH_SWD_LISTEN -CYREG_SFLASH_SWD_LISTEN EQU 0x0ffff258 +CYREG_SFLASH_SWD_LISTEN EQU 0x0ffff158 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_CYCLES__OFFSET CYFLD_SFLASH_CYCLES__OFFSET EQU 0x00000000 @@ -911,7 +911,7 @@ CYFLD_SFLASH_CYCLES__OFFSET EQU 0x00000000 CYFLD_SFLASH_CYCLES__SIZE EQU 0x00000020 ENDIF IF :LNOT::DEF:CYREG_SFLASH_FLASH_START -CYREG_SFLASH_FLASH_START EQU 0x0ffff25c +CYREG_SFLASH_FLASH_START EQU 0x0ffff15c ENDIF IF :LNOT::DEF:CYFLD_SFLASH_ADDRESS__OFFSET CYFLD_SFLASH_ADDRESS__OFFSET EQU 0x00000000 @@ -920,7 +920,7 @@ CYFLD_SFLASH_ADDRESS__OFFSET EQU 0x00000000 CYFLD_SFLASH_ADDRESS__SIZE EQU 0x00000020 ENDIF IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM1_HVIDAC -CYREG_SFLASH_CSD_TRIM1_HVIDAC EQU 0x0ffff260 +CYREG_SFLASH_CSD_TRIM1_HVIDAC EQU 0x0ffff160 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_TRIM8__OFFSET CYFLD_SFLASH_TRIM8__OFFSET EQU 0x00000000 @@ -929,16 +929,16 @@ CYFLD_SFLASH_TRIM8__OFFSET EQU 0x00000000 CYFLD_SFLASH_TRIM8__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM2_HVIDAC -CYREG_SFLASH_CSD_TRIM2_HVIDAC EQU 0x0ffff261 +CYREG_SFLASH_CSD_TRIM2_HVIDAC EQU 0x0ffff161 ENDIF IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM1_CSD -CYREG_SFLASH_CSD_TRIM1_CSD EQU 0x0ffff262 +CYREG_SFLASH_CSD_TRIM1_CSD EQU 0x0ffff162 ENDIF IF :LNOT::DEF:CYREG_SFLASH_CSD_TRIM2_CSD -CYREG_SFLASH_CSD_TRIM2_CSD EQU 0x0ffff263 +CYREG_SFLASH_CSD_TRIM2_CSD EQU 0x0ffff163 ENDIF IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_MULTIPLIER -CYREG_SFLASH_SAR_TEMP_MULTIPLIER EQU 0x0ffff264 +CYREG_SFLASH_SAR_TEMP_MULTIPLIER EQU 0x0ffff164 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET EQU 0x00000000 @@ -947,154 +947,16 @@ CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET EQU 0x00000000 CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE EQU 0x00000010 ENDIF IF :LNOT::DEF:CYREG_SFLASH_SAR_TEMP_OFFSET -CYREG_SFLASH_SAR_TEMP_OFFSET EQU 0x0ffff266 +CYREG_SFLASH_SAR_TEMP_OFFSET EQU 0x0ffff166 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__OFFSET CYFLD_SFLASH_TEMP_OFFSET__OFFSET EQU 0x00000000 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_TEMP_OFFSET__SIZE CYFLD_SFLASH_TEMP_OFFSET__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0 -CYREG_SFLASH_BLE_BLERD_REG_34_TRIM0 EQU 0x0ffff26c - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_FCAL_BIAS_SEL__OFFSET -CYFLD_SFLASH_FCAL_BIAS_SEL__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_FCAL_BIAS_SEL__SIZE -CYFLD_SFLASH_FCAL_BIAS_SEL__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_ACAP_BIAS_SEL__OFFSET -CYFLD_SFLASH_ACAP_BIAS_SEL__OFFSET EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_ACAP_BIAS_SEL__SIZE -CYFLD_SFLASH_ACAP_BIAS_SEL__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_ICP_XFACTOR__OFFSET -CYFLD_SFLASH_ICP_XFACTOR__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_ICP_XFACTOR__SIZE -CYFLD_SFLASH_ICP_XFACTOR__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_ICP_OFFSET__OFFSET -CYFLD_SFLASH_ICP_OFFSET__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_ICP_OFFSET__SIZE -CYFLD_SFLASH_ICP_OFFSET__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_CLKNC_MODE__OFFSET -CYFLD_SFLASH_CLKNC_MODE__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_CLKNC_MODE__SIZE -CYFLD_SFLASH_CLKNC_MODE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_PUP_MON__OFFSET -CYFLD_SFLASH_PUP_MON__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_PUP_MON__SIZE -CYFLD_SFLASH_PUP_MON__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_VCTRL_PULLDN__OFFSET -CYFLD_SFLASH_VCTRL_PULLDN__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_VCTRL_PULLDN__SIZE -CYFLD_SFLASH_VCTRL_PULLDN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_VMOD_PULLDN__OFFSET -CYFLD_SFLASH_VMOD_PULLDN__OFFSET EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_VMOD_PULLDN__SIZE -CYFLD_SFLASH_VMOD_PULLDN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_RST_DLY__OFFSET -CYFLD_SFLASH_RST_DLY__OFFSET EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_RST_DLY__SIZE -CYFLD_SFLASH_RST_DLY__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_PDCP_OFFSET__OFFSET -CYFLD_SFLASH_PDCP_OFFSET__OFFSET EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_PDCP_OFFSET__SIZE -CYFLD_SFLASH_PDCP_OFFSET__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1 -CYREG_SFLASH_BLE_BLERD_REG_34_TRIM1 EQU 0x0ffff26d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0 -CYREG_SFLASH_BLE_BLERD_REG_38_TRIM0 EQU 0x0ffff26e - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_LNA_IBIAS__OFFSET -CYFLD_SFLASH_LNA_IBIAS__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_LNA_IBIAS__SIZE -CYFLD_SFLASH_LNA_IBIAS__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_TIA_IBIAS__OFFSET -CYFLD_SFLASH_TIA_IBIAS__OFFSET EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_TIA_IBIAS__SIZE -CYFLD_SFLASH_TIA_IBIAS__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_CBPF_IBIAS__OFFSET -CYFLD_SFLASH_CBPF_IBIAS__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_CBPF_IBIAS__SIZE -CYFLD_SFLASH_CBPF_IBIAS__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_IF_CM_IBIAS__OFFSET -CYFLD_SFLASH_IF_CM_IBIAS__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_IF_CM_IBIAS__SIZE -CYFLD_SFLASH_IF_CM_IBIAS__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_CBPF_HIZ_ENABLE__OFFSET -CYFLD_SFLASH_CBPF_HIZ_ENABLE__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_CBPF_HIZ_ENABLE__SIZE -CYFLD_SFLASH_CBPF_HIZ_ENABLE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_COMPLEX_DISABLE__OFFSET -CYFLD_SFLASH_COMPLEX_DISABLE__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_COMPLEX_DISABLE__SIZE -CYFLD_SFLASH_COMPLEX_DISABLE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_R2HIGHMODE__OFFSET -CYFLD_SFLASH_SY_R2HIGHMODE__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_R2HIGHMODE__SIZE -CYFLD_SFLASH_SY_R2HIGHMODE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_HILINEARITYR2_MODE__OFFSET -CYFLD_SFLASH_SY_HILINEARITYR2_MODE__OFFSET EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_HILINEARITYR2_MODE__SIZE -CYFLD_SFLASH_SY_HILINEARITYR2_MODE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_LOWKVAMODE__OFFSET -CYFLD_SFLASH_SY_LOWKVAMODE__OFFSET EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_LOWKVAMODE__SIZE -CYFLD_SFLASH_SY_LOWKVAMODE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_LOWKVMMODE__OFFSET -CYFLD_SFLASH_SY_LOWKVMMODE__OFFSET EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_SY_LOWKVMMODE__SIZE -CYFLD_SFLASH_SY_LOWKVMMODE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_REV_RX_BUMP2__OFFSET -CYFLD_SFLASH_REV_RX_BUMP2__OFFSET EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYFLD_SFLASH_REV_RX_BUMP2__SIZE -CYFLD_SFLASH_REV_RX_BUMP2__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1 -CYREG_SFLASH_BLE_BLERD_REG_38_TRIM1 EQU 0x0ffff26f ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY0 -CYREG_SFLASH_PROT_VIRGINKEY0 EQU 0x0ffff270 +CYREG_SFLASH_PROT_VIRGINKEY0 EQU 0x0ffff170 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_KEY8__OFFSET CYFLD_SFLASH_KEY8__OFFSET EQU 0x00000000 @@ -1103,28 +965,28 @@ CYFLD_SFLASH_KEY8__OFFSET EQU 0x00000000 CYFLD_SFLASH_KEY8__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY1 -CYREG_SFLASH_PROT_VIRGINKEY1 EQU 0x0ffff271 +CYREG_SFLASH_PROT_VIRGINKEY1 EQU 0x0ffff171 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY2 -CYREG_SFLASH_PROT_VIRGINKEY2 EQU 0x0ffff272 +CYREG_SFLASH_PROT_VIRGINKEY2 EQU 0x0ffff172 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY3 -CYREG_SFLASH_PROT_VIRGINKEY3 EQU 0x0ffff273 +CYREG_SFLASH_PROT_VIRGINKEY3 EQU 0x0ffff173 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY4 -CYREG_SFLASH_PROT_VIRGINKEY4 EQU 0x0ffff274 +CYREG_SFLASH_PROT_VIRGINKEY4 EQU 0x0ffff174 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY5 -CYREG_SFLASH_PROT_VIRGINKEY5 EQU 0x0ffff275 +CYREG_SFLASH_PROT_VIRGINKEY5 EQU 0x0ffff175 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY6 -CYREG_SFLASH_PROT_VIRGINKEY6 EQU 0x0ffff276 +CYREG_SFLASH_PROT_VIRGINKEY6 EQU 0x0ffff176 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_VIRGINKEY7 -CYREG_SFLASH_PROT_VIRGINKEY7 EQU 0x0ffff277 +CYREG_SFLASH_PROT_VIRGINKEY7 EQU 0x0ffff177 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT0 -CYREG_SFLASH_DIE_LOT0 EQU 0x0ffff278 +CYREG_SFLASH_DIE_LOT0 EQU 0x0ffff178 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_LOT__OFFSET CYFLD_SFLASH_LOT__OFFSET EQU 0x00000000 @@ -1133,13 +995,13 @@ CYFLD_SFLASH_LOT__OFFSET EQU 0x00000000 CYFLD_SFLASH_LOT__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT1 -CYREG_SFLASH_DIE_LOT1 EQU 0x0ffff279 +CYREG_SFLASH_DIE_LOT1 EQU 0x0ffff179 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_LOT2 -CYREG_SFLASH_DIE_LOT2 EQU 0x0ffff27a +CYREG_SFLASH_DIE_LOT2 EQU 0x0ffff17a ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_WAFER -CYREG_SFLASH_DIE_WAFER EQU 0x0ffff27b +CYREG_SFLASH_DIE_WAFER EQU 0x0ffff17b ENDIF IF :LNOT::DEF:CYFLD_SFLASH_WAFER__OFFSET CYFLD_SFLASH_WAFER__OFFSET EQU 0x00000000 @@ -1148,7 +1010,7 @@ CYFLD_SFLASH_WAFER__OFFSET EQU 0x00000000 CYFLD_SFLASH_WAFER__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_X -CYREG_SFLASH_DIE_X EQU 0x0ffff27c +CYREG_SFLASH_DIE_X EQU 0x0ffff17c ENDIF IF :LNOT::DEF:CYFLD_SFLASH_X__OFFSET CYFLD_SFLASH_X__OFFSET EQU 0x00000000 @@ -1157,7 +1019,7 @@ CYFLD_SFLASH_X__OFFSET EQU 0x00000000 CYFLD_SFLASH_X__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_Y -CYREG_SFLASH_DIE_Y EQU 0x0ffff27d +CYREG_SFLASH_DIE_Y EQU 0x0ffff17d ENDIF IF :LNOT::DEF:CYFLD_SFLASH_Y__OFFSET CYFLD_SFLASH_Y__OFFSET EQU 0x00000000 @@ -1166,7 +1028,7 @@ CYFLD_SFLASH_Y__OFFSET EQU 0x00000000 CYFLD_SFLASH_Y__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_SORT -CYREG_SFLASH_DIE_SORT EQU 0x0ffff27e +CYREG_SFLASH_DIE_SORT EQU 0x0ffff17e ENDIF IF :LNOT::DEF:CYFLD_SFLASH_S1_PASS__OFFSET CYFLD_SFLASH_S1_PASS__OFFSET EQU 0x00000000 @@ -1205,7 +1067,7 @@ CYFLD_SFLASH_ENG_PASS__OFFSET EQU 0x00000005 CYFLD_SFLASH_ENG_PASS__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_SFLASH_DIE_MINOR -CYREG_SFLASH_DIE_MINOR EQU 0x0ffff27f +CYREG_SFLASH_DIE_MINOR EQU 0x0ffff17f ENDIF IF :LNOT::DEF:CYFLD_SFLASH_MINOR__OFFSET CYFLD_SFLASH_MINOR__OFFSET EQU 0x00000000 @@ -1214,7 +1076,7 @@ CYFLD_SFLASH_MINOR__OFFSET EQU 0x00000000 CYFLD_SFLASH_MINOR__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_USBMODE_24 -CYREG_SFLASH_IMO_TRIM_USBMODE_24 EQU 0x0ffff33e +CYREG_SFLASH_IMO_TRIM_USBMODE_24 EQU 0x0ffff1be ENDIF IF :LNOT::DEF:CYFLD_SFLASH_TRIM_24__OFFSET CYFLD_SFLASH_TRIM_24__OFFSET EQU 0x00000000 @@ -1223,10 +1085,10 @@ CYFLD_SFLASH_TRIM_24__OFFSET EQU 0x00000000 CYFLD_SFLASH_TRIM_24__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM_USBMODE_48 -CYREG_SFLASH_IMO_TRIM_USBMODE_48 EQU 0x0ffff33f +CYREG_SFLASH_IMO_TRIM_USBMODE_48 EQU 0x0ffff1bf ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF0 -CYREG_SFLASH_IMO_MAXF0 EQU 0x0ffff340 +CYREG_SFLASH_IMO_MAXF0 EQU 0x0ffff1c0 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_MAXFREQ__OFFSET CYFLD_SFLASH_MAXFREQ__OFFSET EQU 0x00000000 @@ -1235,7 +1097,7 @@ CYFLD_SFLASH_MAXFREQ__OFFSET EQU 0x00000000 CYFLD_SFLASH_MAXFREQ__SIZE EQU 0x00000006 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS0 -CYREG_SFLASH_IMO_ABS0 EQU 0x0ffff341 +CYREG_SFLASH_IMO_ABS0 EQU 0x0ffff1c1 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET EQU 0x00000000 @@ -1244,7 +1106,7 @@ CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET EQU 0x00000000 CYFLD_SFLASH_ABS_TRIM_IMO__SIZE EQU 0x00000006 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO0 -CYREG_SFLASH_IMO_TMPCO0 EQU 0x0ffff342 +CYREG_SFLASH_IMO_TMPCO0 EQU 0x0ffff1c2 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET EQU 0x00000000 @@ -1253,40 +1115,40 @@ CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET EQU 0x00000000 CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE EQU 0x00000006 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF1 -CYREG_SFLASH_IMO_MAXF1 EQU 0x0ffff343 +CYREG_SFLASH_IMO_MAXF1 EQU 0x0ffff1c3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS1 -CYREG_SFLASH_IMO_ABS1 EQU 0x0ffff344 +CYREG_SFLASH_IMO_ABS1 EQU 0x0ffff1c4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO1 -CYREG_SFLASH_IMO_TMPCO1 EQU 0x0ffff345 +CYREG_SFLASH_IMO_TMPCO1 EQU 0x0ffff1c5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF2 -CYREG_SFLASH_IMO_MAXF2 EQU 0x0ffff346 +CYREG_SFLASH_IMO_MAXF2 EQU 0x0ffff1c6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS2 -CYREG_SFLASH_IMO_ABS2 EQU 0x0ffff347 +CYREG_SFLASH_IMO_ABS2 EQU 0x0ffff1c7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO2 -CYREG_SFLASH_IMO_TMPCO2 EQU 0x0ffff348 +CYREG_SFLASH_IMO_TMPCO2 EQU 0x0ffff1c8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_MAXF3 -CYREG_SFLASH_IMO_MAXF3 EQU 0x0ffff349 +CYREG_SFLASH_IMO_MAXF3 EQU 0x0ffff1c9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS3 -CYREG_SFLASH_IMO_ABS3 EQU 0x0ffff34a +CYREG_SFLASH_IMO_ABS3 EQU 0x0ffff1ca ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO3 -CYREG_SFLASH_IMO_TMPCO3 EQU 0x0ffff34b +CYREG_SFLASH_IMO_TMPCO3 EQU 0x0ffff1cb ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_ABS4 -CYREG_SFLASH_IMO_ABS4 EQU 0x0ffff34c +CYREG_SFLASH_IMO_ABS4 EQU 0x0ffff1cc ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TMPCO4 -CYREG_SFLASH_IMO_TMPCO4 EQU 0x0ffff34d +CYREG_SFLASH_IMO_TMPCO4 EQU 0x0ffff1cd ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM0 -CYREG_SFLASH_IMO_TRIM0 EQU 0x0ffff350 +CYREG_SFLASH_IMO_TRIM0 EQU 0x0ffff1d0 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_OFFSET__OFFSET CYFLD_SFLASH_OFFSET__OFFSET EQU 0x00000000 @@ -1295,142 +1157,142 @@ CYFLD_SFLASH_OFFSET__OFFSET EQU 0x00000000 CYFLD_SFLASH_OFFSET__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM1 -CYREG_SFLASH_IMO_TRIM1 EQU 0x0ffff351 +CYREG_SFLASH_IMO_TRIM1 EQU 0x0ffff1d1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM2 -CYREG_SFLASH_IMO_TRIM2 EQU 0x0ffff352 +CYREG_SFLASH_IMO_TRIM2 EQU 0x0ffff1d2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM3 -CYREG_SFLASH_IMO_TRIM3 EQU 0x0ffff353 +CYREG_SFLASH_IMO_TRIM3 EQU 0x0ffff1d3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM4 -CYREG_SFLASH_IMO_TRIM4 EQU 0x0ffff354 +CYREG_SFLASH_IMO_TRIM4 EQU 0x0ffff1d4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM5 -CYREG_SFLASH_IMO_TRIM5 EQU 0x0ffff355 +CYREG_SFLASH_IMO_TRIM5 EQU 0x0ffff1d5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM6 -CYREG_SFLASH_IMO_TRIM6 EQU 0x0ffff356 +CYREG_SFLASH_IMO_TRIM6 EQU 0x0ffff1d6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM7 -CYREG_SFLASH_IMO_TRIM7 EQU 0x0ffff357 +CYREG_SFLASH_IMO_TRIM7 EQU 0x0ffff1d7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM8 -CYREG_SFLASH_IMO_TRIM8 EQU 0x0ffff358 +CYREG_SFLASH_IMO_TRIM8 EQU 0x0ffff1d8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM9 -CYREG_SFLASH_IMO_TRIM9 EQU 0x0ffff359 +CYREG_SFLASH_IMO_TRIM9 EQU 0x0ffff1d9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM10 -CYREG_SFLASH_IMO_TRIM10 EQU 0x0ffff35a +CYREG_SFLASH_IMO_TRIM10 EQU 0x0ffff1da ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM11 -CYREG_SFLASH_IMO_TRIM11 EQU 0x0ffff35b +CYREG_SFLASH_IMO_TRIM11 EQU 0x0ffff1db ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM12 -CYREG_SFLASH_IMO_TRIM12 EQU 0x0ffff35c +CYREG_SFLASH_IMO_TRIM12 EQU 0x0ffff1dc ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM13 -CYREG_SFLASH_IMO_TRIM13 EQU 0x0ffff35d +CYREG_SFLASH_IMO_TRIM13 EQU 0x0ffff1dd ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM14 -CYREG_SFLASH_IMO_TRIM14 EQU 0x0ffff35e +CYREG_SFLASH_IMO_TRIM14 EQU 0x0ffff1de ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM15 -CYREG_SFLASH_IMO_TRIM15 EQU 0x0ffff35f +CYREG_SFLASH_IMO_TRIM15 EQU 0x0ffff1df ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM16 -CYREG_SFLASH_IMO_TRIM16 EQU 0x0ffff360 +CYREG_SFLASH_IMO_TRIM16 EQU 0x0ffff1e0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM17 -CYREG_SFLASH_IMO_TRIM17 EQU 0x0ffff361 +CYREG_SFLASH_IMO_TRIM17 EQU 0x0ffff1e1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM18 -CYREG_SFLASH_IMO_TRIM18 EQU 0x0ffff362 +CYREG_SFLASH_IMO_TRIM18 EQU 0x0ffff1e2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM19 -CYREG_SFLASH_IMO_TRIM19 EQU 0x0ffff363 +CYREG_SFLASH_IMO_TRIM19 EQU 0x0ffff1e3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM20 -CYREG_SFLASH_IMO_TRIM20 EQU 0x0ffff364 +CYREG_SFLASH_IMO_TRIM20 EQU 0x0ffff1e4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM21 -CYREG_SFLASH_IMO_TRIM21 EQU 0x0ffff365 +CYREG_SFLASH_IMO_TRIM21 EQU 0x0ffff1e5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM22 -CYREG_SFLASH_IMO_TRIM22 EQU 0x0ffff366 +CYREG_SFLASH_IMO_TRIM22 EQU 0x0ffff1e6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM23 -CYREG_SFLASH_IMO_TRIM23 EQU 0x0ffff367 +CYREG_SFLASH_IMO_TRIM23 EQU 0x0ffff1e7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM24 -CYREG_SFLASH_IMO_TRIM24 EQU 0x0ffff368 +CYREG_SFLASH_IMO_TRIM24 EQU 0x0ffff1e8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM25 -CYREG_SFLASH_IMO_TRIM25 EQU 0x0ffff369 +CYREG_SFLASH_IMO_TRIM25 EQU 0x0ffff1e9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM26 -CYREG_SFLASH_IMO_TRIM26 EQU 0x0ffff36a +CYREG_SFLASH_IMO_TRIM26 EQU 0x0ffff1ea ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM27 -CYREG_SFLASH_IMO_TRIM27 EQU 0x0ffff36b +CYREG_SFLASH_IMO_TRIM27 EQU 0x0ffff1eb ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM28 -CYREG_SFLASH_IMO_TRIM28 EQU 0x0ffff36c +CYREG_SFLASH_IMO_TRIM28 EQU 0x0ffff1ec ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM29 -CYREG_SFLASH_IMO_TRIM29 EQU 0x0ffff36d +CYREG_SFLASH_IMO_TRIM29 EQU 0x0ffff1ed ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM30 -CYREG_SFLASH_IMO_TRIM30 EQU 0x0ffff36e +CYREG_SFLASH_IMO_TRIM30 EQU 0x0ffff1ee ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM31 -CYREG_SFLASH_IMO_TRIM31 EQU 0x0ffff36f +CYREG_SFLASH_IMO_TRIM31 EQU 0x0ffff1ef ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM32 -CYREG_SFLASH_IMO_TRIM32 EQU 0x0ffff370 +CYREG_SFLASH_IMO_TRIM32 EQU 0x0ffff1f0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM33 -CYREG_SFLASH_IMO_TRIM33 EQU 0x0ffff371 +CYREG_SFLASH_IMO_TRIM33 EQU 0x0ffff1f1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM34 -CYREG_SFLASH_IMO_TRIM34 EQU 0x0ffff372 +CYREG_SFLASH_IMO_TRIM34 EQU 0x0ffff1f2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM35 -CYREG_SFLASH_IMO_TRIM35 EQU 0x0ffff373 +CYREG_SFLASH_IMO_TRIM35 EQU 0x0ffff1f3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM36 -CYREG_SFLASH_IMO_TRIM36 EQU 0x0ffff374 +CYREG_SFLASH_IMO_TRIM36 EQU 0x0ffff1f4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM37 -CYREG_SFLASH_IMO_TRIM37 EQU 0x0ffff375 +CYREG_SFLASH_IMO_TRIM37 EQU 0x0ffff1f5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM38 -CYREG_SFLASH_IMO_TRIM38 EQU 0x0ffff376 +CYREG_SFLASH_IMO_TRIM38 EQU 0x0ffff1f6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM39 -CYREG_SFLASH_IMO_TRIM39 EQU 0x0ffff377 +CYREG_SFLASH_IMO_TRIM39 EQU 0x0ffff1f7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM40 -CYREG_SFLASH_IMO_TRIM40 EQU 0x0ffff378 +CYREG_SFLASH_IMO_TRIM40 EQU 0x0ffff1f8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM41 -CYREG_SFLASH_IMO_TRIM41 EQU 0x0ffff379 +CYREG_SFLASH_IMO_TRIM41 EQU 0x0ffff1f9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM42 -CYREG_SFLASH_IMO_TRIM42 EQU 0x0ffff37a +CYREG_SFLASH_IMO_TRIM42 EQU 0x0ffff1fa ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM43 -CYREG_SFLASH_IMO_TRIM43 EQU 0x0ffff37b +CYREG_SFLASH_IMO_TRIM43 EQU 0x0ffff1fb ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM44 -CYREG_SFLASH_IMO_TRIM44 EQU 0x0ffff37c +CYREG_SFLASH_IMO_TRIM44 EQU 0x0ffff1fc ENDIF IF :LNOT::DEF:CYREG_SFLASH_IMO_TRIM45 -CYREG_SFLASH_IMO_TRIM45 EQU 0x0ffff37d +CYREG_SFLASH_IMO_TRIM45 EQU 0x0ffff1fd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH0 -CYREG_SFLASH_MACRO_0_FREE_SFLASH0 EQU 0x0ffff400 +CYREG_SFLASH_MACRO_0_FREE_SFLASH0 EQU 0x0ffff200 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_BYTE_MEM__OFFSET CYFLD_SFLASH_BYTE_MEM__OFFSET EQU 0x00000000 @@ -1439,3844 +1301,2308 @@ CYFLD_SFLASH_BYTE_MEM__OFFSET EQU 0x00000000 CYFLD_SFLASH_BYTE_MEM__SIZE EQU 0x00000008 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1 EQU 0x0ffff401 +CYREG_SFLASH_MACRO_0_FREE_SFLASH1 EQU 0x0ffff201 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH2 -CYREG_SFLASH_MACRO_0_FREE_SFLASH2 EQU 0x0ffff402 +CYREG_SFLASH_MACRO_0_FREE_SFLASH2 EQU 0x0ffff202 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH3 -CYREG_SFLASH_MACRO_0_FREE_SFLASH3 EQU 0x0ffff403 +CYREG_SFLASH_MACRO_0_FREE_SFLASH3 EQU 0x0ffff203 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH4 -CYREG_SFLASH_MACRO_0_FREE_SFLASH4 EQU 0x0ffff404 +CYREG_SFLASH_MACRO_0_FREE_SFLASH4 EQU 0x0ffff204 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH5 -CYREG_SFLASH_MACRO_0_FREE_SFLASH5 EQU 0x0ffff405 +CYREG_SFLASH_MACRO_0_FREE_SFLASH5 EQU 0x0ffff205 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH6 -CYREG_SFLASH_MACRO_0_FREE_SFLASH6 EQU 0x0ffff406 +CYREG_SFLASH_MACRO_0_FREE_SFLASH6 EQU 0x0ffff206 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH7 -CYREG_SFLASH_MACRO_0_FREE_SFLASH7 EQU 0x0ffff407 +CYREG_SFLASH_MACRO_0_FREE_SFLASH7 EQU 0x0ffff207 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH8 -CYREG_SFLASH_MACRO_0_FREE_SFLASH8 EQU 0x0ffff408 +CYREG_SFLASH_MACRO_0_FREE_SFLASH8 EQU 0x0ffff208 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH9 -CYREG_SFLASH_MACRO_0_FREE_SFLASH9 EQU 0x0ffff409 +CYREG_SFLASH_MACRO_0_FREE_SFLASH9 EQU 0x0ffff209 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH10 -CYREG_SFLASH_MACRO_0_FREE_SFLASH10 EQU 0x0ffff40a +CYREG_SFLASH_MACRO_0_FREE_SFLASH10 EQU 0x0ffff20a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH11 -CYREG_SFLASH_MACRO_0_FREE_SFLASH11 EQU 0x0ffff40b +CYREG_SFLASH_MACRO_0_FREE_SFLASH11 EQU 0x0ffff20b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH12 -CYREG_SFLASH_MACRO_0_FREE_SFLASH12 EQU 0x0ffff40c +CYREG_SFLASH_MACRO_0_FREE_SFLASH12 EQU 0x0ffff20c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH13 -CYREG_SFLASH_MACRO_0_FREE_SFLASH13 EQU 0x0ffff40d +CYREG_SFLASH_MACRO_0_FREE_SFLASH13 EQU 0x0ffff20d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH14 -CYREG_SFLASH_MACRO_0_FREE_SFLASH14 EQU 0x0ffff40e +CYREG_SFLASH_MACRO_0_FREE_SFLASH14 EQU 0x0ffff20e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH15 -CYREG_SFLASH_MACRO_0_FREE_SFLASH15 EQU 0x0ffff40f +CYREG_SFLASH_MACRO_0_FREE_SFLASH15 EQU 0x0ffff20f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH16 -CYREG_SFLASH_MACRO_0_FREE_SFLASH16 EQU 0x0ffff410 +CYREG_SFLASH_MACRO_0_FREE_SFLASH16 EQU 0x0ffff210 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH17 -CYREG_SFLASH_MACRO_0_FREE_SFLASH17 EQU 0x0ffff411 +CYREG_SFLASH_MACRO_0_FREE_SFLASH17 EQU 0x0ffff211 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH18 -CYREG_SFLASH_MACRO_0_FREE_SFLASH18 EQU 0x0ffff412 +CYREG_SFLASH_MACRO_0_FREE_SFLASH18 EQU 0x0ffff212 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH19 -CYREG_SFLASH_MACRO_0_FREE_SFLASH19 EQU 0x0ffff413 +CYREG_SFLASH_MACRO_0_FREE_SFLASH19 EQU 0x0ffff213 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH20 -CYREG_SFLASH_MACRO_0_FREE_SFLASH20 EQU 0x0ffff414 +CYREG_SFLASH_MACRO_0_FREE_SFLASH20 EQU 0x0ffff214 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH21 -CYREG_SFLASH_MACRO_0_FREE_SFLASH21 EQU 0x0ffff415 +CYREG_SFLASH_MACRO_0_FREE_SFLASH21 EQU 0x0ffff215 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH22 -CYREG_SFLASH_MACRO_0_FREE_SFLASH22 EQU 0x0ffff416 +CYREG_SFLASH_MACRO_0_FREE_SFLASH22 EQU 0x0ffff216 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH23 -CYREG_SFLASH_MACRO_0_FREE_SFLASH23 EQU 0x0ffff417 +CYREG_SFLASH_MACRO_0_FREE_SFLASH23 EQU 0x0ffff217 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH24 -CYREG_SFLASH_MACRO_0_FREE_SFLASH24 EQU 0x0ffff418 +CYREG_SFLASH_MACRO_0_FREE_SFLASH24 EQU 0x0ffff218 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH25 -CYREG_SFLASH_MACRO_0_FREE_SFLASH25 EQU 0x0ffff419 +CYREG_SFLASH_MACRO_0_FREE_SFLASH25 EQU 0x0ffff219 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH26 -CYREG_SFLASH_MACRO_0_FREE_SFLASH26 EQU 0x0ffff41a +CYREG_SFLASH_MACRO_0_FREE_SFLASH26 EQU 0x0ffff21a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH27 -CYREG_SFLASH_MACRO_0_FREE_SFLASH27 EQU 0x0ffff41b +CYREG_SFLASH_MACRO_0_FREE_SFLASH27 EQU 0x0ffff21b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH28 -CYREG_SFLASH_MACRO_0_FREE_SFLASH28 EQU 0x0ffff41c +CYREG_SFLASH_MACRO_0_FREE_SFLASH28 EQU 0x0ffff21c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH29 -CYREG_SFLASH_MACRO_0_FREE_SFLASH29 EQU 0x0ffff41d +CYREG_SFLASH_MACRO_0_FREE_SFLASH29 EQU 0x0ffff21d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH30 -CYREG_SFLASH_MACRO_0_FREE_SFLASH30 EQU 0x0ffff41e +CYREG_SFLASH_MACRO_0_FREE_SFLASH30 EQU 0x0ffff21e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH31 -CYREG_SFLASH_MACRO_0_FREE_SFLASH31 EQU 0x0ffff41f +CYREG_SFLASH_MACRO_0_FREE_SFLASH31 EQU 0x0ffff21f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH32 -CYREG_SFLASH_MACRO_0_FREE_SFLASH32 EQU 0x0ffff420 +CYREG_SFLASH_MACRO_0_FREE_SFLASH32 EQU 0x0ffff220 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH33 -CYREG_SFLASH_MACRO_0_FREE_SFLASH33 EQU 0x0ffff421 +CYREG_SFLASH_MACRO_0_FREE_SFLASH33 EQU 0x0ffff221 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH34 -CYREG_SFLASH_MACRO_0_FREE_SFLASH34 EQU 0x0ffff422 +CYREG_SFLASH_MACRO_0_FREE_SFLASH34 EQU 0x0ffff222 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH35 -CYREG_SFLASH_MACRO_0_FREE_SFLASH35 EQU 0x0ffff423 +CYREG_SFLASH_MACRO_0_FREE_SFLASH35 EQU 0x0ffff223 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH36 -CYREG_SFLASH_MACRO_0_FREE_SFLASH36 EQU 0x0ffff424 +CYREG_SFLASH_MACRO_0_FREE_SFLASH36 EQU 0x0ffff224 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH37 -CYREG_SFLASH_MACRO_0_FREE_SFLASH37 EQU 0x0ffff425 +CYREG_SFLASH_MACRO_0_FREE_SFLASH37 EQU 0x0ffff225 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH38 -CYREG_SFLASH_MACRO_0_FREE_SFLASH38 EQU 0x0ffff426 +CYREG_SFLASH_MACRO_0_FREE_SFLASH38 EQU 0x0ffff226 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH39 -CYREG_SFLASH_MACRO_0_FREE_SFLASH39 EQU 0x0ffff427 +CYREG_SFLASH_MACRO_0_FREE_SFLASH39 EQU 0x0ffff227 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH40 -CYREG_SFLASH_MACRO_0_FREE_SFLASH40 EQU 0x0ffff428 +CYREG_SFLASH_MACRO_0_FREE_SFLASH40 EQU 0x0ffff228 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH41 -CYREG_SFLASH_MACRO_0_FREE_SFLASH41 EQU 0x0ffff429 +CYREG_SFLASH_MACRO_0_FREE_SFLASH41 EQU 0x0ffff229 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH42 -CYREG_SFLASH_MACRO_0_FREE_SFLASH42 EQU 0x0ffff42a +CYREG_SFLASH_MACRO_0_FREE_SFLASH42 EQU 0x0ffff22a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH43 -CYREG_SFLASH_MACRO_0_FREE_SFLASH43 EQU 0x0ffff42b +CYREG_SFLASH_MACRO_0_FREE_SFLASH43 EQU 0x0ffff22b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH44 -CYREG_SFLASH_MACRO_0_FREE_SFLASH44 EQU 0x0ffff42c +CYREG_SFLASH_MACRO_0_FREE_SFLASH44 EQU 0x0ffff22c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH45 -CYREG_SFLASH_MACRO_0_FREE_SFLASH45 EQU 0x0ffff42d +CYREG_SFLASH_MACRO_0_FREE_SFLASH45 EQU 0x0ffff22d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH46 -CYREG_SFLASH_MACRO_0_FREE_SFLASH46 EQU 0x0ffff42e +CYREG_SFLASH_MACRO_0_FREE_SFLASH46 EQU 0x0ffff22e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH47 -CYREG_SFLASH_MACRO_0_FREE_SFLASH47 EQU 0x0ffff42f +CYREG_SFLASH_MACRO_0_FREE_SFLASH47 EQU 0x0ffff22f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH48 -CYREG_SFLASH_MACRO_0_FREE_SFLASH48 EQU 0x0ffff430 +CYREG_SFLASH_MACRO_0_FREE_SFLASH48 EQU 0x0ffff230 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH49 -CYREG_SFLASH_MACRO_0_FREE_SFLASH49 EQU 0x0ffff431 +CYREG_SFLASH_MACRO_0_FREE_SFLASH49 EQU 0x0ffff231 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH50 -CYREG_SFLASH_MACRO_0_FREE_SFLASH50 EQU 0x0ffff432 +CYREG_SFLASH_MACRO_0_FREE_SFLASH50 EQU 0x0ffff232 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH51 -CYREG_SFLASH_MACRO_0_FREE_SFLASH51 EQU 0x0ffff433 +CYREG_SFLASH_MACRO_0_FREE_SFLASH51 EQU 0x0ffff233 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH52 -CYREG_SFLASH_MACRO_0_FREE_SFLASH52 EQU 0x0ffff434 +CYREG_SFLASH_MACRO_0_FREE_SFLASH52 EQU 0x0ffff234 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH53 -CYREG_SFLASH_MACRO_0_FREE_SFLASH53 EQU 0x0ffff435 +CYREG_SFLASH_MACRO_0_FREE_SFLASH53 EQU 0x0ffff235 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH54 -CYREG_SFLASH_MACRO_0_FREE_SFLASH54 EQU 0x0ffff436 +CYREG_SFLASH_MACRO_0_FREE_SFLASH54 EQU 0x0ffff236 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH55 -CYREG_SFLASH_MACRO_0_FREE_SFLASH55 EQU 0x0ffff437 +CYREG_SFLASH_MACRO_0_FREE_SFLASH55 EQU 0x0ffff237 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH56 -CYREG_SFLASH_MACRO_0_FREE_SFLASH56 EQU 0x0ffff438 +CYREG_SFLASH_MACRO_0_FREE_SFLASH56 EQU 0x0ffff238 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH57 -CYREG_SFLASH_MACRO_0_FREE_SFLASH57 EQU 0x0ffff439 +CYREG_SFLASH_MACRO_0_FREE_SFLASH57 EQU 0x0ffff239 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH58 -CYREG_SFLASH_MACRO_0_FREE_SFLASH58 EQU 0x0ffff43a +CYREG_SFLASH_MACRO_0_FREE_SFLASH58 EQU 0x0ffff23a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH59 -CYREG_SFLASH_MACRO_0_FREE_SFLASH59 EQU 0x0ffff43b +CYREG_SFLASH_MACRO_0_FREE_SFLASH59 EQU 0x0ffff23b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH60 -CYREG_SFLASH_MACRO_0_FREE_SFLASH60 EQU 0x0ffff43c +CYREG_SFLASH_MACRO_0_FREE_SFLASH60 EQU 0x0ffff23c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH61 -CYREG_SFLASH_MACRO_0_FREE_SFLASH61 EQU 0x0ffff43d +CYREG_SFLASH_MACRO_0_FREE_SFLASH61 EQU 0x0ffff23d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH62 -CYREG_SFLASH_MACRO_0_FREE_SFLASH62 EQU 0x0ffff43e +CYREG_SFLASH_MACRO_0_FREE_SFLASH62 EQU 0x0ffff23e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH63 -CYREG_SFLASH_MACRO_0_FREE_SFLASH63 EQU 0x0ffff43f +CYREG_SFLASH_MACRO_0_FREE_SFLASH63 EQU 0x0ffff23f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH64 -CYREG_SFLASH_MACRO_0_FREE_SFLASH64 EQU 0x0ffff440 +CYREG_SFLASH_MACRO_0_FREE_SFLASH64 EQU 0x0ffff240 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH65 -CYREG_SFLASH_MACRO_0_FREE_SFLASH65 EQU 0x0ffff441 +CYREG_SFLASH_MACRO_0_FREE_SFLASH65 EQU 0x0ffff241 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH66 -CYREG_SFLASH_MACRO_0_FREE_SFLASH66 EQU 0x0ffff442 +CYREG_SFLASH_MACRO_0_FREE_SFLASH66 EQU 0x0ffff242 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH67 -CYREG_SFLASH_MACRO_0_FREE_SFLASH67 EQU 0x0ffff443 +CYREG_SFLASH_MACRO_0_FREE_SFLASH67 EQU 0x0ffff243 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH68 -CYREG_SFLASH_MACRO_0_FREE_SFLASH68 EQU 0x0ffff444 +CYREG_SFLASH_MACRO_0_FREE_SFLASH68 EQU 0x0ffff244 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH69 -CYREG_SFLASH_MACRO_0_FREE_SFLASH69 EQU 0x0ffff445 +CYREG_SFLASH_MACRO_0_FREE_SFLASH69 EQU 0x0ffff245 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH70 -CYREG_SFLASH_MACRO_0_FREE_SFLASH70 EQU 0x0ffff446 +CYREG_SFLASH_MACRO_0_FREE_SFLASH70 EQU 0x0ffff246 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH71 -CYREG_SFLASH_MACRO_0_FREE_SFLASH71 EQU 0x0ffff447 +CYREG_SFLASH_MACRO_0_FREE_SFLASH71 EQU 0x0ffff247 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH72 -CYREG_SFLASH_MACRO_0_FREE_SFLASH72 EQU 0x0ffff448 +CYREG_SFLASH_MACRO_0_FREE_SFLASH72 EQU 0x0ffff248 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH73 -CYREG_SFLASH_MACRO_0_FREE_SFLASH73 EQU 0x0ffff449 +CYREG_SFLASH_MACRO_0_FREE_SFLASH73 EQU 0x0ffff249 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH74 -CYREG_SFLASH_MACRO_0_FREE_SFLASH74 EQU 0x0ffff44a +CYREG_SFLASH_MACRO_0_FREE_SFLASH74 EQU 0x0ffff24a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH75 -CYREG_SFLASH_MACRO_0_FREE_SFLASH75 EQU 0x0ffff44b +CYREG_SFLASH_MACRO_0_FREE_SFLASH75 EQU 0x0ffff24b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH76 -CYREG_SFLASH_MACRO_0_FREE_SFLASH76 EQU 0x0ffff44c +CYREG_SFLASH_MACRO_0_FREE_SFLASH76 EQU 0x0ffff24c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH77 -CYREG_SFLASH_MACRO_0_FREE_SFLASH77 EQU 0x0ffff44d +CYREG_SFLASH_MACRO_0_FREE_SFLASH77 EQU 0x0ffff24d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH78 -CYREG_SFLASH_MACRO_0_FREE_SFLASH78 EQU 0x0ffff44e +CYREG_SFLASH_MACRO_0_FREE_SFLASH78 EQU 0x0ffff24e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH79 -CYREG_SFLASH_MACRO_0_FREE_SFLASH79 EQU 0x0ffff44f +CYREG_SFLASH_MACRO_0_FREE_SFLASH79 EQU 0x0ffff24f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH80 -CYREG_SFLASH_MACRO_0_FREE_SFLASH80 EQU 0x0ffff450 +CYREG_SFLASH_MACRO_0_FREE_SFLASH80 EQU 0x0ffff250 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH81 -CYREG_SFLASH_MACRO_0_FREE_SFLASH81 EQU 0x0ffff451 +CYREG_SFLASH_MACRO_0_FREE_SFLASH81 EQU 0x0ffff251 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH82 -CYREG_SFLASH_MACRO_0_FREE_SFLASH82 EQU 0x0ffff452 +CYREG_SFLASH_MACRO_0_FREE_SFLASH82 EQU 0x0ffff252 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH83 -CYREG_SFLASH_MACRO_0_FREE_SFLASH83 EQU 0x0ffff453 +CYREG_SFLASH_MACRO_0_FREE_SFLASH83 EQU 0x0ffff253 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH84 -CYREG_SFLASH_MACRO_0_FREE_SFLASH84 EQU 0x0ffff454 +CYREG_SFLASH_MACRO_0_FREE_SFLASH84 EQU 0x0ffff254 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH85 -CYREG_SFLASH_MACRO_0_FREE_SFLASH85 EQU 0x0ffff455 +CYREG_SFLASH_MACRO_0_FREE_SFLASH85 EQU 0x0ffff255 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH86 -CYREG_SFLASH_MACRO_0_FREE_SFLASH86 EQU 0x0ffff456 +CYREG_SFLASH_MACRO_0_FREE_SFLASH86 EQU 0x0ffff256 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH87 -CYREG_SFLASH_MACRO_0_FREE_SFLASH87 EQU 0x0ffff457 +CYREG_SFLASH_MACRO_0_FREE_SFLASH87 EQU 0x0ffff257 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH88 -CYREG_SFLASH_MACRO_0_FREE_SFLASH88 EQU 0x0ffff458 +CYREG_SFLASH_MACRO_0_FREE_SFLASH88 EQU 0x0ffff258 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH89 -CYREG_SFLASH_MACRO_0_FREE_SFLASH89 EQU 0x0ffff459 +CYREG_SFLASH_MACRO_0_FREE_SFLASH89 EQU 0x0ffff259 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH90 -CYREG_SFLASH_MACRO_0_FREE_SFLASH90 EQU 0x0ffff45a +CYREG_SFLASH_MACRO_0_FREE_SFLASH90 EQU 0x0ffff25a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH91 -CYREG_SFLASH_MACRO_0_FREE_SFLASH91 EQU 0x0ffff45b +CYREG_SFLASH_MACRO_0_FREE_SFLASH91 EQU 0x0ffff25b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH92 -CYREG_SFLASH_MACRO_0_FREE_SFLASH92 EQU 0x0ffff45c +CYREG_SFLASH_MACRO_0_FREE_SFLASH92 EQU 0x0ffff25c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH93 -CYREG_SFLASH_MACRO_0_FREE_SFLASH93 EQU 0x0ffff45d +CYREG_SFLASH_MACRO_0_FREE_SFLASH93 EQU 0x0ffff25d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH94 -CYREG_SFLASH_MACRO_0_FREE_SFLASH94 EQU 0x0ffff45e +CYREG_SFLASH_MACRO_0_FREE_SFLASH94 EQU 0x0ffff25e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH95 -CYREG_SFLASH_MACRO_0_FREE_SFLASH95 EQU 0x0ffff45f +CYREG_SFLASH_MACRO_0_FREE_SFLASH95 EQU 0x0ffff25f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH96 -CYREG_SFLASH_MACRO_0_FREE_SFLASH96 EQU 0x0ffff460 +CYREG_SFLASH_MACRO_0_FREE_SFLASH96 EQU 0x0ffff260 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH97 -CYREG_SFLASH_MACRO_0_FREE_SFLASH97 EQU 0x0ffff461 +CYREG_SFLASH_MACRO_0_FREE_SFLASH97 EQU 0x0ffff261 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH98 -CYREG_SFLASH_MACRO_0_FREE_SFLASH98 EQU 0x0ffff462 +CYREG_SFLASH_MACRO_0_FREE_SFLASH98 EQU 0x0ffff262 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH99 -CYREG_SFLASH_MACRO_0_FREE_SFLASH99 EQU 0x0ffff463 +CYREG_SFLASH_MACRO_0_FREE_SFLASH99 EQU 0x0ffff263 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH100 -CYREG_SFLASH_MACRO_0_FREE_SFLASH100 EQU 0x0ffff464 +CYREG_SFLASH_MACRO_0_FREE_SFLASH100 EQU 0x0ffff264 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH101 -CYREG_SFLASH_MACRO_0_FREE_SFLASH101 EQU 0x0ffff465 +CYREG_SFLASH_MACRO_0_FREE_SFLASH101 EQU 0x0ffff265 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH102 -CYREG_SFLASH_MACRO_0_FREE_SFLASH102 EQU 0x0ffff466 +CYREG_SFLASH_MACRO_0_FREE_SFLASH102 EQU 0x0ffff266 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH103 -CYREG_SFLASH_MACRO_0_FREE_SFLASH103 EQU 0x0ffff467 +CYREG_SFLASH_MACRO_0_FREE_SFLASH103 EQU 0x0ffff267 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH104 -CYREG_SFLASH_MACRO_0_FREE_SFLASH104 EQU 0x0ffff468 +CYREG_SFLASH_MACRO_0_FREE_SFLASH104 EQU 0x0ffff268 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH105 -CYREG_SFLASH_MACRO_0_FREE_SFLASH105 EQU 0x0ffff469 +CYREG_SFLASH_MACRO_0_FREE_SFLASH105 EQU 0x0ffff269 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH106 -CYREG_SFLASH_MACRO_0_FREE_SFLASH106 EQU 0x0ffff46a +CYREG_SFLASH_MACRO_0_FREE_SFLASH106 EQU 0x0ffff26a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH107 -CYREG_SFLASH_MACRO_0_FREE_SFLASH107 EQU 0x0ffff46b +CYREG_SFLASH_MACRO_0_FREE_SFLASH107 EQU 0x0ffff26b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH108 -CYREG_SFLASH_MACRO_0_FREE_SFLASH108 EQU 0x0ffff46c +CYREG_SFLASH_MACRO_0_FREE_SFLASH108 EQU 0x0ffff26c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH109 -CYREG_SFLASH_MACRO_0_FREE_SFLASH109 EQU 0x0ffff46d +CYREG_SFLASH_MACRO_0_FREE_SFLASH109 EQU 0x0ffff26d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH110 -CYREG_SFLASH_MACRO_0_FREE_SFLASH110 EQU 0x0ffff46e +CYREG_SFLASH_MACRO_0_FREE_SFLASH110 EQU 0x0ffff26e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH111 -CYREG_SFLASH_MACRO_0_FREE_SFLASH111 EQU 0x0ffff46f +CYREG_SFLASH_MACRO_0_FREE_SFLASH111 EQU 0x0ffff26f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH112 -CYREG_SFLASH_MACRO_0_FREE_SFLASH112 EQU 0x0ffff470 +CYREG_SFLASH_MACRO_0_FREE_SFLASH112 EQU 0x0ffff270 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH113 -CYREG_SFLASH_MACRO_0_FREE_SFLASH113 EQU 0x0ffff471 +CYREG_SFLASH_MACRO_0_FREE_SFLASH113 EQU 0x0ffff271 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH114 -CYREG_SFLASH_MACRO_0_FREE_SFLASH114 EQU 0x0ffff472 +CYREG_SFLASH_MACRO_0_FREE_SFLASH114 EQU 0x0ffff272 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH115 -CYREG_SFLASH_MACRO_0_FREE_SFLASH115 EQU 0x0ffff473 +CYREG_SFLASH_MACRO_0_FREE_SFLASH115 EQU 0x0ffff273 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH116 -CYREG_SFLASH_MACRO_0_FREE_SFLASH116 EQU 0x0ffff474 +CYREG_SFLASH_MACRO_0_FREE_SFLASH116 EQU 0x0ffff274 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH117 -CYREG_SFLASH_MACRO_0_FREE_SFLASH117 EQU 0x0ffff475 +CYREG_SFLASH_MACRO_0_FREE_SFLASH117 EQU 0x0ffff275 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH118 -CYREG_SFLASH_MACRO_0_FREE_SFLASH118 EQU 0x0ffff476 +CYREG_SFLASH_MACRO_0_FREE_SFLASH118 EQU 0x0ffff276 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH119 -CYREG_SFLASH_MACRO_0_FREE_SFLASH119 EQU 0x0ffff477 +CYREG_SFLASH_MACRO_0_FREE_SFLASH119 EQU 0x0ffff277 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH120 -CYREG_SFLASH_MACRO_0_FREE_SFLASH120 EQU 0x0ffff478 +CYREG_SFLASH_MACRO_0_FREE_SFLASH120 EQU 0x0ffff278 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH121 -CYREG_SFLASH_MACRO_0_FREE_SFLASH121 EQU 0x0ffff479 +CYREG_SFLASH_MACRO_0_FREE_SFLASH121 EQU 0x0ffff279 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH122 -CYREG_SFLASH_MACRO_0_FREE_SFLASH122 EQU 0x0ffff47a +CYREG_SFLASH_MACRO_0_FREE_SFLASH122 EQU 0x0ffff27a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH123 -CYREG_SFLASH_MACRO_0_FREE_SFLASH123 EQU 0x0ffff47b +CYREG_SFLASH_MACRO_0_FREE_SFLASH123 EQU 0x0ffff27b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH124 -CYREG_SFLASH_MACRO_0_FREE_SFLASH124 EQU 0x0ffff47c +CYREG_SFLASH_MACRO_0_FREE_SFLASH124 EQU 0x0ffff27c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH125 -CYREG_SFLASH_MACRO_0_FREE_SFLASH125 EQU 0x0ffff47d +CYREG_SFLASH_MACRO_0_FREE_SFLASH125 EQU 0x0ffff27d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH126 -CYREG_SFLASH_MACRO_0_FREE_SFLASH126 EQU 0x0ffff47e +CYREG_SFLASH_MACRO_0_FREE_SFLASH126 EQU 0x0ffff27e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH127 -CYREG_SFLASH_MACRO_0_FREE_SFLASH127 EQU 0x0ffff47f +CYREG_SFLASH_MACRO_0_FREE_SFLASH127 EQU 0x0ffff27f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH128 -CYREG_SFLASH_MACRO_0_FREE_SFLASH128 EQU 0x0ffff480 +CYREG_SFLASH_MACRO_0_FREE_SFLASH128 EQU 0x0ffff280 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH129 -CYREG_SFLASH_MACRO_0_FREE_SFLASH129 EQU 0x0ffff481 +CYREG_SFLASH_MACRO_0_FREE_SFLASH129 EQU 0x0ffff281 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH130 -CYREG_SFLASH_MACRO_0_FREE_SFLASH130 EQU 0x0ffff482 +CYREG_SFLASH_MACRO_0_FREE_SFLASH130 EQU 0x0ffff282 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH131 -CYREG_SFLASH_MACRO_0_FREE_SFLASH131 EQU 0x0ffff483 +CYREG_SFLASH_MACRO_0_FREE_SFLASH131 EQU 0x0ffff283 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH132 -CYREG_SFLASH_MACRO_0_FREE_SFLASH132 EQU 0x0ffff484 +CYREG_SFLASH_MACRO_0_FREE_SFLASH132 EQU 0x0ffff284 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH133 -CYREG_SFLASH_MACRO_0_FREE_SFLASH133 EQU 0x0ffff485 +CYREG_SFLASH_MACRO_0_FREE_SFLASH133 EQU 0x0ffff285 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH134 -CYREG_SFLASH_MACRO_0_FREE_SFLASH134 EQU 0x0ffff486 +CYREG_SFLASH_MACRO_0_FREE_SFLASH134 EQU 0x0ffff286 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH135 -CYREG_SFLASH_MACRO_0_FREE_SFLASH135 EQU 0x0ffff487 +CYREG_SFLASH_MACRO_0_FREE_SFLASH135 EQU 0x0ffff287 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH136 -CYREG_SFLASH_MACRO_0_FREE_SFLASH136 EQU 0x0ffff488 +CYREG_SFLASH_MACRO_0_FREE_SFLASH136 EQU 0x0ffff288 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH137 -CYREG_SFLASH_MACRO_0_FREE_SFLASH137 EQU 0x0ffff489 +CYREG_SFLASH_MACRO_0_FREE_SFLASH137 EQU 0x0ffff289 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH138 -CYREG_SFLASH_MACRO_0_FREE_SFLASH138 EQU 0x0ffff48a +CYREG_SFLASH_MACRO_0_FREE_SFLASH138 EQU 0x0ffff28a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH139 -CYREG_SFLASH_MACRO_0_FREE_SFLASH139 EQU 0x0ffff48b +CYREG_SFLASH_MACRO_0_FREE_SFLASH139 EQU 0x0ffff28b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH140 -CYREG_SFLASH_MACRO_0_FREE_SFLASH140 EQU 0x0ffff48c +CYREG_SFLASH_MACRO_0_FREE_SFLASH140 EQU 0x0ffff28c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH141 -CYREG_SFLASH_MACRO_0_FREE_SFLASH141 EQU 0x0ffff48d +CYREG_SFLASH_MACRO_0_FREE_SFLASH141 EQU 0x0ffff28d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH142 -CYREG_SFLASH_MACRO_0_FREE_SFLASH142 EQU 0x0ffff48e +CYREG_SFLASH_MACRO_0_FREE_SFLASH142 EQU 0x0ffff28e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH143 -CYREG_SFLASH_MACRO_0_FREE_SFLASH143 EQU 0x0ffff48f +CYREG_SFLASH_MACRO_0_FREE_SFLASH143 EQU 0x0ffff28f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH144 -CYREG_SFLASH_MACRO_0_FREE_SFLASH144 EQU 0x0ffff490 +CYREG_SFLASH_MACRO_0_FREE_SFLASH144 EQU 0x0ffff290 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH145 -CYREG_SFLASH_MACRO_0_FREE_SFLASH145 EQU 0x0ffff491 +CYREG_SFLASH_MACRO_0_FREE_SFLASH145 EQU 0x0ffff291 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH146 -CYREG_SFLASH_MACRO_0_FREE_SFLASH146 EQU 0x0ffff492 +CYREG_SFLASH_MACRO_0_FREE_SFLASH146 EQU 0x0ffff292 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH147 -CYREG_SFLASH_MACRO_0_FREE_SFLASH147 EQU 0x0ffff493 +CYREG_SFLASH_MACRO_0_FREE_SFLASH147 EQU 0x0ffff293 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH148 -CYREG_SFLASH_MACRO_0_FREE_SFLASH148 EQU 0x0ffff494 +CYREG_SFLASH_MACRO_0_FREE_SFLASH148 EQU 0x0ffff294 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH149 -CYREG_SFLASH_MACRO_0_FREE_SFLASH149 EQU 0x0ffff495 +CYREG_SFLASH_MACRO_0_FREE_SFLASH149 EQU 0x0ffff295 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH150 -CYREG_SFLASH_MACRO_0_FREE_SFLASH150 EQU 0x0ffff496 +CYREG_SFLASH_MACRO_0_FREE_SFLASH150 EQU 0x0ffff296 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH151 -CYREG_SFLASH_MACRO_0_FREE_SFLASH151 EQU 0x0ffff497 +CYREG_SFLASH_MACRO_0_FREE_SFLASH151 EQU 0x0ffff297 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH152 -CYREG_SFLASH_MACRO_0_FREE_SFLASH152 EQU 0x0ffff498 +CYREG_SFLASH_MACRO_0_FREE_SFLASH152 EQU 0x0ffff298 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH153 -CYREG_SFLASH_MACRO_0_FREE_SFLASH153 EQU 0x0ffff499 +CYREG_SFLASH_MACRO_0_FREE_SFLASH153 EQU 0x0ffff299 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH154 -CYREG_SFLASH_MACRO_0_FREE_SFLASH154 EQU 0x0ffff49a +CYREG_SFLASH_MACRO_0_FREE_SFLASH154 EQU 0x0ffff29a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH155 -CYREG_SFLASH_MACRO_0_FREE_SFLASH155 EQU 0x0ffff49b +CYREG_SFLASH_MACRO_0_FREE_SFLASH155 EQU 0x0ffff29b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH156 -CYREG_SFLASH_MACRO_0_FREE_SFLASH156 EQU 0x0ffff49c +CYREG_SFLASH_MACRO_0_FREE_SFLASH156 EQU 0x0ffff29c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH157 -CYREG_SFLASH_MACRO_0_FREE_SFLASH157 EQU 0x0ffff49d +CYREG_SFLASH_MACRO_0_FREE_SFLASH157 EQU 0x0ffff29d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH158 -CYREG_SFLASH_MACRO_0_FREE_SFLASH158 EQU 0x0ffff49e +CYREG_SFLASH_MACRO_0_FREE_SFLASH158 EQU 0x0ffff29e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH159 -CYREG_SFLASH_MACRO_0_FREE_SFLASH159 EQU 0x0ffff49f +CYREG_SFLASH_MACRO_0_FREE_SFLASH159 EQU 0x0ffff29f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH160 -CYREG_SFLASH_MACRO_0_FREE_SFLASH160 EQU 0x0ffff4a0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH160 EQU 0x0ffff2a0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH161 -CYREG_SFLASH_MACRO_0_FREE_SFLASH161 EQU 0x0ffff4a1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH161 EQU 0x0ffff2a1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH162 -CYREG_SFLASH_MACRO_0_FREE_SFLASH162 EQU 0x0ffff4a2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH162 EQU 0x0ffff2a2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH163 -CYREG_SFLASH_MACRO_0_FREE_SFLASH163 EQU 0x0ffff4a3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH163 EQU 0x0ffff2a3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH164 -CYREG_SFLASH_MACRO_0_FREE_SFLASH164 EQU 0x0ffff4a4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH164 EQU 0x0ffff2a4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH165 -CYREG_SFLASH_MACRO_0_FREE_SFLASH165 EQU 0x0ffff4a5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH165 EQU 0x0ffff2a5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH166 -CYREG_SFLASH_MACRO_0_FREE_SFLASH166 EQU 0x0ffff4a6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH166 EQU 0x0ffff2a6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH167 -CYREG_SFLASH_MACRO_0_FREE_SFLASH167 EQU 0x0ffff4a7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH167 EQU 0x0ffff2a7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH168 -CYREG_SFLASH_MACRO_0_FREE_SFLASH168 EQU 0x0ffff4a8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH168 EQU 0x0ffff2a8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH169 -CYREG_SFLASH_MACRO_0_FREE_SFLASH169 EQU 0x0ffff4a9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH169 EQU 0x0ffff2a9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH170 -CYREG_SFLASH_MACRO_0_FREE_SFLASH170 EQU 0x0ffff4aa +CYREG_SFLASH_MACRO_0_FREE_SFLASH170 EQU 0x0ffff2aa ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH171 -CYREG_SFLASH_MACRO_0_FREE_SFLASH171 EQU 0x0ffff4ab +CYREG_SFLASH_MACRO_0_FREE_SFLASH171 EQU 0x0ffff2ab ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH172 -CYREG_SFLASH_MACRO_0_FREE_SFLASH172 EQU 0x0ffff4ac +CYREG_SFLASH_MACRO_0_FREE_SFLASH172 EQU 0x0ffff2ac ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH173 -CYREG_SFLASH_MACRO_0_FREE_SFLASH173 EQU 0x0ffff4ad +CYREG_SFLASH_MACRO_0_FREE_SFLASH173 EQU 0x0ffff2ad ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH174 -CYREG_SFLASH_MACRO_0_FREE_SFLASH174 EQU 0x0ffff4ae +CYREG_SFLASH_MACRO_0_FREE_SFLASH174 EQU 0x0ffff2ae ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH175 -CYREG_SFLASH_MACRO_0_FREE_SFLASH175 EQU 0x0ffff4af +CYREG_SFLASH_MACRO_0_FREE_SFLASH175 EQU 0x0ffff2af ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH176 -CYREG_SFLASH_MACRO_0_FREE_SFLASH176 EQU 0x0ffff4b0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH176 EQU 0x0ffff2b0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH177 -CYREG_SFLASH_MACRO_0_FREE_SFLASH177 EQU 0x0ffff4b1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH177 EQU 0x0ffff2b1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH178 -CYREG_SFLASH_MACRO_0_FREE_SFLASH178 EQU 0x0ffff4b2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH178 EQU 0x0ffff2b2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH179 -CYREG_SFLASH_MACRO_0_FREE_SFLASH179 EQU 0x0ffff4b3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH179 EQU 0x0ffff2b3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH180 -CYREG_SFLASH_MACRO_0_FREE_SFLASH180 EQU 0x0ffff4b4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH180 EQU 0x0ffff2b4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH181 -CYREG_SFLASH_MACRO_0_FREE_SFLASH181 EQU 0x0ffff4b5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH181 EQU 0x0ffff2b5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH182 -CYREG_SFLASH_MACRO_0_FREE_SFLASH182 EQU 0x0ffff4b6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH182 EQU 0x0ffff2b6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH183 -CYREG_SFLASH_MACRO_0_FREE_SFLASH183 EQU 0x0ffff4b7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH183 EQU 0x0ffff2b7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH184 -CYREG_SFLASH_MACRO_0_FREE_SFLASH184 EQU 0x0ffff4b8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH184 EQU 0x0ffff2b8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH185 -CYREG_SFLASH_MACRO_0_FREE_SFLASH185 EQU 0x0ffff4b9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH185 EQU 0x0ffff2b9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH186 -CYREG_SFLASH_MACRO_0_FREE_SFLASH186 EQU 0x0ffff4ba +CYREG_SFLASH_MACRO_0_FREE_SFLASH186 EQU 0x0ffff2ba ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH187 -CYREG_SFLASH_MACRO_0_FREE_SFLASH187 EQU 0x0ffff4bb +CYREG_SFLASH_MACRO_0_FREE_SFLASH187 EQU 0x0ffff2bb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH188 -CYREG_SFLASH_MACRO_0_FREE_SFLASH188 EQU 0x0ffff4bc +CYREG_SFLASH_MACRO_0_FREE_SFLASH188 EQU 0x0ffff2bc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH189 -CYREG_SFLASH_MACRO_0_FREE_SFLASH189 EQU 0x0ffff4bd +CYREG_SFLASH_MACRO_0_FREE_SFLASH189 EQU 0x0ffff2bd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH190 -CYREG_SFLASH_MACRO_0_FREE_SFLASH190 EQU 0x0ffff4be +CYREG_SFLASH_MACRO_0_FREE_SFLASH190 EQU 0x0ffff2be ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH191 -CYREG_SFLASH_MACRO_0_FREE_SFLASH191 EQU 0x0ffff4bf +CYREG_SFLASH_MACRO_0_FREE_SFLASH191 EQU 0x0ffff2bf ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH192 -CYREG_SFLASH_MACRO_0_FREE_SFLASH192 EQU 0x0ffff4c0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH192 EQU 0x0ffff2c0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH193 -CYREG_SFLASH_MACRO_0_FREE_SFLASH193 EQU 0x0ffff4c1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH193 EQU 0x0ffff2c1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH194 -CYREG_SFLASH_MACRO_0_FREE_SFLASH194 EQU 0x0ffff4c2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH194 EQU 0x0ffff2c2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH195 -CYREG_SFLASH_MACRO_0_FREE_SFLASH195 EQU 0x0ffff4c3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH195 EQU 0x0ffff2c3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH196 -CYREG_SFLASH_MACRO_0_FREE_SFLASH196 EQU 0x0ffff4c4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH196 EQU 0x0ffff2c4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH197 -CYREG_SFLASH_MACRO_0_FREE_SFLASH197 EQU 0x0ffff4c5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH197 EQU 0x0ffff2c5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH198 -CYREG_SFLASH_MACRO_0_FREE_SFLASH198 EQU 0x0ffff4c6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH198 EQU 0x0ffff2c6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH199 -CYREG_SFLASH_MACRO_0_FREE_SFLASH199 EQU 0x0ffff4c7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH199 EQU 0x0ffff2c7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH200 -CYREG_SFLASH_MACRO_0_FREE_SFLASH200 EQU 0x0ffff4c8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH200 EQU 0x0ffff2c8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH201 -CYREG_SFLASH_MACRO_0_FREE_SFLASH201 EQU 0x0ffff4c9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH201 EQU 0x0ffff2c9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH202 -CYREG_SFLASH_MACRO_0_FREE_SFLASH202 EQU 0x0ffff4ca +CYREG_SFLASH_MACRO_0_FREE_SFLASH202 EQU 0x0ffff2ca ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH203 -CYREG_SFLASH_MACRO_0_FREE_SFLASH203 EQU 0x0ffff4cb +CYREG_SFLASH_MACRO_0_FREE_SFLASH203 EQU 0x0ffff2cb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH204 -CYREG_SFLASH_MACRO_0_FREE_SFLASH204 EQU 0x0ffff4cc +CYREG_SFLASH_MACRO_0_FREE_SFLASH204 EQU 0x0ffff2cc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH205 -CYREG_SFLASH_MACRO_0_FREE_SFLASH205 EQU 0x0ffff4cd +CYREG_SFLASH_MACRO_0_FREE_SFLASH205 EQU 0x0ffff2cd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH206 -CYREG_SFLASH_MACRO_0_FREE_SFLASH206 EQU 0x0ffff4ce +CYREG_SFLASH_MACRO_0_FREE_SFLASH206 EQU 0x0ffff2ce ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH207 -CYREG_SFLASH_MACRO_0_FREE_SFLASH207 EQU 0x0ffff4cf +CYREG_SFLASH_MACRO_0_FREE_SFLASH207 EQU 0x0ffff2cf ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH208 -CYREG_SFLASH_MACRO_0_FREE_SFLASH208 EQU 0x0ffff4d0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH208 EQU 0x0ffff2d0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH209 -CYREG_SFLASH_MACRO_0_FREE_SFLASH209 EQU 0x0ffff4d1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH209 EQU 0x0ffff2d1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH210 -CYREG_SFLASH_MACRO_0_FREE_SFLASH210 EQU 0x0ffff4d2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH210 EQU 0x0ffff2d2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH211 -CYREG_SFLASH_MACRO_0_FREE_SFLASH211 EQU 0x0ffff4d3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH211 EQU 0x0ffff2d3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH212 -CYREG_SFLASH_MACRO_0_FREE_SFLASH212 EQU 0x0ffff4d4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH212 EQU 0x0ffff2d4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH213 -CYREG_SFLASH_MACRO_0_FREE_SFLASH213 EQU 0x0ffff4d5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH213 EQU 0x0ffff2d5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH214 -CYREG_SFLASH_MACRO_0_FREE_SFLASH214 EQU 0x0ffff4d6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH214 EQU 0x0ffff2d6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH215 -CYREG_SFLASH_MACRO_0_FREE_SFLASH215 EQU 0x0ffff4d7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH215 EQU 0x0ffff2d7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH216 -CYREG_SFLASH_MACRO_0_FREE_SFLASH216 EQU 0x0ffff4d8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH216 EQU 0x0ffff2d8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH217 -CYREG_SFLASH_MACRO_0_FREE_SFLASH217 EQU 0x0ffff4d9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH217 EQU 0x0ffff2d9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH218 -CYREG_SFLASH_MACRO_0_FREE_SFLASH218 EQU 0x0ffff4da +CYREG_SFLASH_MACRO_0_FREE_SFLASH218 EQU 0x0ffff2da ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH219 -CYREG_SFLASH_MACRO_0_FREE_SFLASH219 EQU 0x0ffff4db +CYREG_SFLASH_MACRO_0_FREE_SFLASH219 EQU 0x0ffff2db ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH220 -CYREG_SFLASH_MACRO_0_FREE_SFLASH220 EQU 0x0ffff4dc +CYREG_SFLASH_MACRO_0_FREE_SFLASH220 EQU 0x0ffff2dc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH221 -CYREG_SFLASH_MACRO_0_FREE_SFLASH221 EQU 0x0ffff4dd +CYREG_SFLASH_MACRO_0_FREE_SFLASH221 EQU 0x0ffff2dd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH222 -CYREG_SFLASH_MACRO_0_FREE_SFLASH222 EQU 0x0ffff4de +CYREG_SFLASH_MACRO_0_FREE_SFLASH222 EQU 0x0ffff2de ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH223 -CYREG_SFLASH_MACRO_0_FREE_SFLASH223 EQU 0x0ffff4df +CYREG_SFLASH_MACRO_0_FREE_SFLASH223 EQU 0x0ffff2df ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH224 -CYREG_SFLASH_MACRO_0_FREE_SFLASH224 EQU 0x0ffff4e0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH224 EQU 0x0ffff2e0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH225 -CYREG_SFLASH_MACRO_0_FREE_SFLASH225 EQU 0x0ffff4e1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH225 EQU 0x0ffff2e1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH226 -CYREG_SFLASH_MACRO_0_FREE_SFLASH226 EQU 0x0ffff4e2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH226 EQU 0x0ffff2e2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH227 -CYREG_SFLASH_MACRO_0_FREE_SFLASH227 EQU 0x0ffff4e3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH227 EQU 0x0ffff2e3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH228 -CYREG_SFLASH_MACRO_0_FREE_SFLASH228 EQU 0x0ffff4e4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH228 EQU 0x0ffff2e4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH229 -CYREG_SFLASH_MACRO_0_FREE_SFLASH229 EQU 0x0ffff4e5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH229 EQU 0x0ffff2e5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH230 -CYREG_SFLASH_MACRO_0_FREE_SFLASH230 EQU 0x0ffff4e6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH230 EQU 0x0ffff2e6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH231 -CYREG_SFLASH_MACRO_0_FREE_SFLASH231 EQU 0x0ffff4e7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH231 EQU 0x0ffff2e7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH232 -CYREG_SFLASH_MACRO_0_FREE_SFLASH232 EQU 0x0ffff4e8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH232 EQU 0x0ffff2e8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH233 -CYREG_SFLASH_MACRO_0_FREE_SFLASH233 EQU 0x0ffff4e9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH233 EQU 0x0ffff2e9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH234 -CYREG_SFLASH_MACRO_0_FREE_SFLASH234 EQU 0x0ffff4ea +CYREG_SFLASH_MACRO_0_FREE_SFLASH234 EQU 0x0ffff2ea ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH235 -CYREG_SFLASH_MACRO_0_FREE_SFLASH235 EQU 0x0ffff4eb +CYREG_SFLASH_MACRO_0_FREE_SFLASH235 EQU 0x0ffff2eb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH236 -CYREG_SFLASH_MACRO_0_FREE_SFLASH236 EQU 0x0ffff4ec +CYREG_SFLASH_MACRO_0_FREE_SFLASH236 EQU 0x0ffff2ec ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH237 -CYREG_SFLASH_MACRO_0_FREE_SFLASH237 EQU 0x0ffff4ed +CYREG_SFLASH_MACRO_0_FREE_SFLASH237 EQU 0x0ffff2ed ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH238 -CYREG_SFLASH_MACRO_0_FREE_SFLASH238 EQU 0x0ffff4ee +CYREG_SFLASH_MACRO_0_FREE_SFLASH238 EQU 0x0ffff2ee ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH239 -CYREG_SFLASH_MACRO_0_FREE_SFLASH239 EQU 0x0ffff4ef +CYREG_SFLASH_MACRO_0_FREE_SFLASH239 EQU 0x0ffff2ef ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH240 -CYREG_SFLASH_MACRO_0_FREE_SFLASH240 EQU 0x0ffff4f0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH240 EQU 0x0ffff2f0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH241 -CYREG_SFLASH_MACRO_0_FREE_SFLASH241 EQU 0x0ffff4f1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH241 EQU 0x0ffff2f1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH242 -CYREG_SFLASH_MACRO_0_FREE_SFLASH242 EQU 0x0ffff4f2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH242 EQU 0x0ffff2f2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH243 -CYREG_SFLASH_MACRO_0_FREE_SFLASH243 EQU 0x0ffff4f3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH243 EQU 0x0ffff2f3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH244 -CYREG_SFLASH_MACRO_0_FREE_SFLASH244 EQU 0x0ffff4f4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH244 EQU 0x0ffff2f4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH245 -CYREG_SFLASH_MACRO_0_FREE_SFLASH245 EQU 0x0ffff4f5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH245 EQU 0x0ffff2f5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH246 -CYREG_SFLASH_MACRO_0_FREE_SFLASH246 EQU 0x0ffff4f6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH246 EQU 0x0ffff2f6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH247 -CYREG_SFLASH_MACRO_0_FREE_SFLASH247 EQU 0x0ffff4f7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH247 EQU 0x0ffff2f7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH248 -CYREG_SFLASH_MACRO_0_FREE_SFLASH248 EQU 0x0ffff4f8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH248 EQU 0x0ffff2f8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH249 -CYREG_SFLASH_MACRO_0_FREE_SFLASH249 EQU 0x0ffff4f9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH249 EQU 0x0ffff2f9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH250 -CYREG_SFLASH_MACRO_0_FREE_SFLASH250 EQU 0x0ffff4fa +CYREG_SFLASH_MACRO_0_FREE_SFLASH250 EQU 0x0ffff2fa ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH251 -CYREG_SFLASH_MACRO_0_FREE_SFLASH251 EQU 0x0ffff4fb +CYREG_SFLASH_MACRO_0_FREE_SFLASH251 EQU 0x0ffff2fb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH252 -CYREG_SFLASH_MACRO_0_FREE_SFLASH252 EQU 0x0ffff4fc +CYREG_SFLASH_MACRO_0_FREE_SFLASH252 EQU 0x0ffff2fc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH253 -CYREG_SFLASH_MACRO_0_FREE_SFLASH253 EQU 0x0ffff4fd +CYREG_SFLASH_MACRO_0_FREE_SFLASH253 EQU 0x0ffff2fd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH254 -CYREG_SFLASH_MACRO_0_FREE_SFLASH254 EQU 0x0ffff4fe +CYREG_SFLASH_MACRO_0_FREE_SFLASH254 EQU 0x0ffff2fe ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH255 -CYREG_SFLASH_MACRO_0_FREE_SFLASH255 EQU 0x0ffff4ff +CYREG_SFLASH_MACRO_0_FREE_SFLASH255 EQU 0x0ffff2ff ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH256 -CYREG_SFLASH_MACRO_0_FREE_SFLASH256 EQU 0x0ffff500 +CYREG_SFLASH_MACRO_0_FREE_SFLASH256 EQU 0x0ffff300 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH257 -CYREG_SFLASH_MACRO_0_FREE_SFLASH257 EQU 0x0ffff501 +CYREG_SFLASH_MACRO_0_FREE_SFLASH257 EQU 0x0ffff301 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH258 -CYREG_SFLASH_MACRO_0_FREE_SFLASH258 EQU 0x0ffff502 +CYREG_SFLASH_MACRO_0_FREE_SFLASH258 EQU 0x0ffff302 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH259 -CYREG_SFLASH_MACRO_0_FREE_SFLASH259 EQU 0x0ffff503 +CYREG_SFLASH_MACRO_0_FREE_SFLASH259 EQU 0x0ffff303 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH260 -CYREG_SFLASH_MACRO_0_FREE_SFLASH260 EQU 0x0ffff504 +CYREG_SFLASH_MACRO_0_FREE_SFLASH260 EQU 0x0ffff304 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH261 -CYREG_SFLASH_MACRO_0_FREE_SFLASH261 EQU 0x0ffff505 +CYREG_SFLASH_MACRO_0_FREE_SFLASH261 EQU 0x0ffff305 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH262 -CYREG_SFLASH_MACRO_0_FREE_SFLASH262 EQU 0x0ffff506 +CYREG_SFLASH_MACRO_0_FREE_SFLASH262 EQU 0x0ffff306 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH263 -CYREG_SFLASH_MACRO_0_FREE_SFLASH263 EQU 0x0ffff507 +CYREG_SFLASH_MACRO_0_FREE_SFLASH263 EQU 0x0ffff307 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH264 -CYREG_SFLASH_MACRO_0_FREE_SFLASH264 EQU 0x0ffff508 +CYREG_SFLASH_MACRO_0_FREE_SFLASH264 EQU 0x0ffff308 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH265 -CYREG_SFLASH_MACRO_0_FREE_SFLASH265 EQU 0x0ffff509 +CYREG_SFLASH_MACRO_0_FREE_SFLASH265 EQU 0x0ffff309 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH266 -CYREG_SFLASH_MACRO_0_FREE_SFLASH266 EQU 0x0ffff50a +CYREG_SFLASH_MACRO_0_FREE_SFLASH266 EQU 0x0ffff30a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH267 -CYREG_SFLASH_MACRO_0_FREE_SFLASH267 EQU 0x0ffff50b +CYREG_SFLASH_MACRO_0_FREE_SFLASH267 EQU 0x0ffff30b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH268 -CYREG_SFLASH_MACRO_0_FREE_SFLASH268 EQU 0x0ffff50c +CYREG_SFLASH_MACRO_0_FREE_SFLASH268 EQU 0x0ffff30c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH269 -CYREG_SFLASH_MACRO_0_FREE_SFLASH269 EQU 0x0ffff50d +CYREG_SFLASH_MACRO_0_FREE_SFLASH269 EQU 0x0ffff30d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH270 -CYREG_SFLASH_MACRO_0_FREE_SFLASH270 EQU 0x0ffff50e +CYREG_SFLASH_MACRO_0_FREE_SFLASH270 EQU 0x0ffff30e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH271 -CYREG_SFLASH_MACRO_0_FREE_SFLASH271 EQU 0x0ffff50f +CYREG_SFLASH_MACRO_0_FREE_SFLASH271 EQU 0x0ffff30f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH272 -CYREG_SFLASH_MACRO_0_FREE_SFLASH272 EQU 0x0ffff510 +CYREG_SFLASH_MACRO_0_FREE_SFLASH272 EQU 0x0ffff310 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH273 -CYREG_SFLASH_MACRO_0_FREE_SFLASH273 EQU 0x0ffff511 +CYREG_SFLASH_MACRO_0_FREE_SFLASH273 EQU 0x0ffff311 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH274 -CYREG_SFLASH_MACRO_0_FREE_SFLASH274 EQU 0x0ffff512 +CYREG_SFLASH_MACRO_0_FREE_SFLASH274 EQU 0x0ffff312 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH275 -CYREG_SFLASH_MACRO_0_FREE_SFLASH275 EQU 0x0ffff513 +CYREG_SFLASH_MACRO_0_FREE_SFLASH275 EQU 0x0ffff313 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH276 -CYREG_SFLASH_MACRO_0_FREE_SFLASH276 EQU 0x0ffff514 +CYREG_SFLASH_MACRO_0_FREE_SFLASH276 EQU 0x0ffff314 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH277 -CYREG_SFLASH_MACRO_0_FREE_SFLASH277 EQU 0x0ffff515 +CYREG_SFLASH_MACRO_0_FREE_SFLASH277 EQU 0x0ffff315 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH278 -CYREG_SFLASH_MACRO_0_FREE_SFLASH278 EQU 0x0ffff516 +CYREG_SFLASH_MACRO_0_FREE_SFLASH278 EQU 0x0ffff316 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH279 -CYREG_SFLASH_MACRO_0_FREE_SFLASH279 EQU 0x0ffff517 +CYREG_SFLASH_MACRO_0_FREE_SFLASH279 EQU 0x0ffff317 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH280 -CYREG_SFLASH_MACRO_0_FREE_SFLASH280 EQU 0x0ffff518 +CYREG_SFLASH_MACRO_0_FREE_SFLASH280 EQU 0x0ffff318 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH281 -CYREG_SFLASH_MACRO_0_FREE_SFLASH281 EQU 0x0ffff519 +CYREG_SFLASH_MACRO_0_FREE_SFLASH281 EQU 0x0ffff319 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH282 -CYREG_SFLASH_MACRO_0_FREE_SFLASH282 EQU 0x0ffff51a +CYREG_SFLASH_MACRO_0_FREE_SFLASH282 EQU 0x0ffff31a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH283 -CYREG_SFLASH_MACRO_0_FREE_SFLASH283 EQU 0x0ffff51b +CYREG_SFLASH_MACRO_0_FREE_SFLASH283 EQU 0x0ffff31b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH284 -CYREG_SFLASH_MACRO_0_FREE_SFLASH284 EQU 0x0ffff51c +CYREG_SFLASH_MACRO_0_FREE_SFLASH284 EQU 0x0ffff31c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH285 -CYREG_SFLASH_MACRO_0_FREE_SFLASH285 EQU 0x0ffff51d +CYREG_SFLASH_MACRO_0_FREE_SFLASH285 EQU 0x0ffff31d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH286 -CYREG_SFLASH_MACRO_0_FREE_SFLASH286 EQU 0x0ffff51e +CYREG_SFLASH_MACRO_0_FREE_SFLASH286 EQU 0x0ffff31e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH287 -CYREG_SFLASH_MACRO_0_FREE_SFLASH287 EQU 0x0ffff51f +CYREG_SFLASH_MACRO_0_FREE_SFLASH287 EQU 0x0ffff31f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH288 -CYREG_SFLASH_MACRO_0_FREE_SFLASH288 EQU 0x0ffff520 +CYREG_SFLASH_MACRO_0_FREE_SFLASH288 EQU 0x0ffff320 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH289 -CYREG_SFLASH_MACRO_0_FREE_SFLASH289 EQU 0x0ffff521 +CYREG_SFLASH_MACRO_0_FREE_SFLASH289 EQU 0x0ffff321 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH290 -CYREG_SFLASH_MACRO_0_FREE_SFLASH290 EQU 0x0ffff522 +CYREG_SFLASH_MACRO_0_FREE_SFLASH290 EQU 0x0ffff322 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH291 -CYREG_SFLASH_MACRO_0_FREE_SFLASH291 EQU 0x0ffff523 +CYREG_SFLASH_MACRO_0_FREE_SFLASH291 EQU 0x0ffff323 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH292 -CYREG_SFLASH_MACRO_0_FREE_SFLASH292 EQU 0x0ffff524 +CYREG_SFLASH_MACRO_0_FREE_SFLASH292 EQU 0x0ffff324 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH293 -CYREG_SFLASH_MACRO_0_FREE_SFLASH293 EQU 0x0ffff525 +CYREG_SFLASH_MACRO_0_FREE_SFLASH293 EQU 0x0ffff325 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH294 -CYREG_SFLASH_MACRO_0_FREE_SFLASH294 EQU 0x0ffff526 +CYREG_SFLASH_MACRO_0_FREE_SFLASH294 EQU 0x0ffff326 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH295 -CYREG_SFLASH_MACRO_0_FREE_SFLASH295 EQU 0x0ffff527 +CYREG_SFLASH_MACRO_0_FREE_SFLASH295 EQU 0x0ffff327 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH296 -CYREG_SFLASH_MACRO_0_FREE_SFLASH296 EQU 0x0ffff528 +CYREG_SFLASH_MACRO_0_FREE_SFLASH296 EQU 0x0ffff328 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH297 -CYREG_SFLASH_MACRO_0_FREE_SFLASH297 EQU 0x0ffff529 +CYREG_SFLASH_MACRO_0_FREE_SFLASH297 EQU 0x0ffff329 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH298 -CYREG_SFLASH_MACRO_0_FREE_SFLASH298 EQU 0x0ffff52a +CYREG_SFLASH_MACRO_0_FREE_SFLASH298 EQU 0x0ffff32a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH299 -CYREG_SFLASH_MACRO_0_FREE_SFLASH299 EQU 0x0ffff52b +CYREG_SFLASH_MACRO_0_FREE_SFLASH299 EQU 0x0ffff32b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH300 -CYREG_SFLASH_MACRO_0_FREE_SFLASH300 EQU 0x0ffff52c +CYREG_SFLASH_MACRO_0_FREE_SFLASH300 EQU 0x0ffff32c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH301 -CYREG_SFLASH_MACRO_0_FREE_SFLASH301 EQU 0x0ffff52d +CYREG_SFLASH_MACRO_0_FREE_SFLASH301 EQU 0x0ffff32d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH302 -CYREG_SFLASH_MACRO_0_FREE_SFLASH302 EQU 0x0ffff52e +CYREG_SFLASH_MACRO_0_FREE_SFLASH302 EQU 0x0ffff32e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH303 -CYREG_SFLASH_MACRO_0_FREE_SFLASH303 EQU 0x0ffff52f +CYREG_SFLASH_MACRO_0_FREE_SFLASH303 EQU 0x0ffff32f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH304 -CYREG_SFLASH_MACRO_0_FREE_SFLASH304 EQU 0x0ffff530 +CYREG_SFLASH_MACRO_0_FREE_SFLASH304 EQU 0x0ffff330 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH305 -CYREG_SFLASH_MACRO_0_FREE_SFLASH305 EQU 0x0ffff531 +CYREG_SFLASH_MACRO_0_FREE_SFLASH305 EQU 0x0ffff331 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH306 -CYREG_SFLASH_MACRO_0_FREE_SFLASH306 EQU 0x0ffff532 +CYREG_SFLASH_MACRO_0_FREE_SFLASH306 EQU 0x0ffff332 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH307 -CYREG_SFLASH_MACRO_0_FREE_SFLASH307 EQU 0x0ffff533 +CYREG_SFLASH_MACRO_0_FREE_SFLASH307 EQU 0x0ffff333 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH308 -CYREG_SFLASH_MACRO_0_FREE_SFLASH308 EQU 0x0ffff534 +CYREG_SFLASH_MACRO_0_FREE_SFLASH308 EQU 0x0ffff334 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH309 -CYREG_SFLASH_MACRO_0_FREE_SFLASH309 EQU 0x0ffff535 +CYREG_SFLASH_MACRO_0_FREE_SFLASH309 EQU 0x0ffff335 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH310 -CYREG_SFLASH_MACRO_0_FREE_SFLASH310 EQU 0x0ffff536 +CYREG_SFLASH_MACRO_0_FREE_SFLASH310 EQU 0x0ffff336 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH311 -CYREG_SFLASH_MACRO_0_FREE_SFLASH311 EQU 0x0ffff537 +CYREG_SFLASH_MACRO_0_FREE_SFLASH311 EQU 0x0ffff337 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH312 -CYREG_SFLASH_MACRO_0_FREE_SFLASH312 EQU 0x0ffff538 +CYREG_SFLASH_MACRO_0_FREE_SFLASH312 EQU 0x0ffff338 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH313 -CYREG_SFLASH_MACRO_0_FREE_SFLASH313 EQU 0x0ffff539 +CYREG_SFLASH_MACRO_0_FREE_SFLASH313 EQU 0x0ffff339 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH314 -CYREG_SFLASH_MACRO_0_FREE_SFLASH314 EQU 0x0ffff53a +CYREG_SFLASH_MACRO_0_FREE_SFLASH314 EQU 0x0ffff33a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH315 -CYREG_SFLASH_MACRO_0_FREE_SFLASH315 EQU 0x0ffff53b +CYREG_SFLASH_MACRO_0_FREE_SFLASH315 EQU 0x0ffff33b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH316 -CYREG_SFLASH_MACRO_0_FREE_SFLASH316 EQU 0x0ffff53c +CYREG_SFLASH_MACRO_0_FREE_SFLASH316 EQU 0x0ffff33c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH317 -CYREG_SFLASH_MACRO_0_FREE_SFLASH317 EQU 0x0ffff53d +CYREG_SFLASH_MACRO_0_FREE_SFLASH317 EQU 0x0ffff33d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH318 -CYREG_SFLASH_MACRO_0_FREE_SFLASH318 EQU 0x0ffff53e +CYREG_SFLASH_MACRO_0_FREE_SFLASH318 EQU 0x0ffff33e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH319 -CYREG_SFLASH_MACRO_0_FREE_SFLASH319 EQU 0x0ffff53f +CYREG_SFLASH_MACRO_0_FREE_SFLASH319 EQU 0x0ffff33f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH320 -CYREG_SFLASH_MACRO_0_FREE_SFLASH320 EQU 0x0ffff540 +CYREG_SFLASH_MACRO_0_FREE_SFLASH320 EQU 0x0ffff340 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH321 -CYREG_SFLASH_MACRO_0_FREE_SFLASH321 EQU 0x0ffff541 +CYREG_SFLASH_MACRO_0_FREE_SFLASH321 EQU 0x0ffff341 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH322 -CYREG_SFLASH_MACRO_0_FREE_SFLASH322 EQU 0x0ffff542 +CYREG_SFLASH_MACRO_0_FREE_SFLASH322 EQU 0x0ffff342 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH323 -CYREG_SFLASH_MACRO_0_FREE_SFLASH323 EQU 0x0ffff543 +CYREG_SFLASH_MACRO_0_FREE_SFLASH323 EQU 0x0ffff343 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH324 -CYREG_SFLASH_MACRO_0_FREE_SFLASH324 EQU 0x0ffff544 +CYREG_SFLASH_MACRO_0_FREE_SFLASH324 EQU 0x0ffff344 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH325 -CYREG_SFLASH_MACRO_0_FREE_SFLASH325 EQU 0x0ffff545 +CYREG_SFLASH_MACRO_0_FREE_SFLASH325 EQU 0x0ffff345 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH326 -CYREG_SFLASH_MACRO_0_FREE_SFLASH326 EQU 0x0ffff546 +CYREG_SFLASH_MACRO_0_FREE_SFLASH326 EQU 0x0ffff346 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH327 -CYREG_SFLASH_MACRO_0_FREE_SFLASH327 EQU 0x0ffff547 +CYREG_SFLASH_MACRO_0_FREE_SFLASH327 EQU 0x0ffff347 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH328 -CYREG_SFLASH_MACRO_0_FREE_SFLASH328 EQU 0x0ffff548 +CYREG_SFLASH_MACRO_0_FREE_SFLASH328 EQU 0x0ffff348 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH329 -CYREG_SFLASH_MACRO_0_FREE_SFLASH329 EQU 0x0ffff549 +CYREG_SFLASH_MACRO_0_FREE_SFLASH329 EQU 0x0ffff349 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH330 -CYREG_SFLASH_MACRO_0_FREE_SFLASH330 EQU 0x0ffff54a +CYREG_SFLASH_MACRO_0_FREE_SFLASH330 EQU 0x0ffff34a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH331 -CYREG_SFLASH_MACRO_0_FREE_SFLASH331 EQU 0x0ffff54b +CYREG_SFLASH_MACRO_0_FREE_SFLASH331 EQU 0x0ffff34b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH332 -CYREG_SFLASH_MACRO_0_FREE_SFLASH332 EQU 0x0ffff54c +CYREG_SFLASH_MACRO_0_FREE_SFLASH332 EQU 0x0ffff34c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH333 -CYREG_SFLASH_MACRO_0_FREE_SFLASH333 EQU 0x0ffff54d +CYREG_SFLASH_MACRO_0_FREE_SFLASH333 EQU 0x0ffff34d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH334 -CYREG_SFLASH_MACRO_0_FREE_SFLASH334 EQU 0x0ffff54e +CYREG_SFLASH_MACRO_0_FREE_SFLASH334 EQU 0x0ffff34e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH335 -CYREG_SFLASH_MACRO_0_FREE_SFLASH335 EQU 0x0ffff54f +CYREG_SFLASH_MACRO_0_FREE_SFLASH335 EQU 0x0ffff34f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH336 -CYREG_SFLASH_MACRO_0_FREE_SFLASH336 EQU 0x0ffff550 +CYREG_SFLASH_MACRO_0_FREE_SFLASH336 EQU 0x0ffff350 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH337 -CYREG_SFLASH_MACRO_0_FREE_SFLASH337 EQU 0x0ffff551 +CYREG_SFLASH_MACRO_0_FREE_SFLASH337 EQU 0x0ffff351 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH338 -CYREG_SFLASH_MACRO_0_FREE_SFLASH338 EQU 0x0ffff552 +CYREG_SFLASH_MACRO_0_FREE_SFLASH338 EQU 0x0ffff352 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH339 -CYREG_SFLASH_MACRO_0_FREE_SFLASH339 EQU 0x0ffff553 +CYREG_SFLASH_MACRO_0_FREE_SFLASH339 EQU 0x0ffff353 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH340 -CYREG_SFLASH_MACRO_0_FREE_SFLASH340 EQU 0x0ffff554 +CYREG_SFLASH_MACRO_0_FREE_SFLASH340 EQU 0x0ffff354 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH341 -CYREG_SFLASH_MACRO_0_FREE_SFLASH341 EQU 0x0ffff555 +CYREG_SFLASH_MACRO_0_FREE_SFLASH341 EQU 0x0ffff355 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH342 -CYREG_SFLASH_MACRO_0_FREE_SFLASH342 EQU 0x0ffff556 +CYREG_SFLASH_MACRO_0_FREE_SFLASH342 EQU 0x0ffff356 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH343 -CYREG_SFLASH_MACRO_0_FREE_SFLASH343 EQU 0x0ffff557 +CYREG_SFLASH_MACRO_0_FREE_SFLASH343 EQU 0x0ffff357 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH344 -CYREG_SFLASH_MACRO_0_FREE_SFLASH344 EQU 0x0ffff558 +CYREG_SFLASH_MACRO_0_FREE_SFLASH344 EQU 0x0ffff358 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH345 -CYREG_SFLASH_MACRO_0_FREE_SFLASH345 EQU 0x0ffff559 +CYREG_SFLASH_MACRO_0_FREE_SFLASH345 EQU 0x0ffff359 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH346 -CYREG_SFLASH_MACRO_0_FREE_SFLASH346 EQU 0x0ffff55a +CYREG_SFLASH_MACRO_0_FREE_SFLASH346 EQU 0x0ffff35a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH347 -CYREG_SFLASH_MACRO_0_FREE_SFLASH347 EQU 0x0ffff55b +CYREG_SFLASH_MACRO_0_FREE_SFLASH347 EQU 0x0ffff35b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH348 -CYREG_SFLASH_MACRO_0_FREE_SFLASH348 EQU 0x0ffff55c +CYREG_SFLASH_MACRO_0_FREE_SFLASH348 EQU 0x0ffff35c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH349 -CYREG_SFLASH_MACRO_0_FREE_SFLASH349 EQU 0x0ffff55d +CYREG_SFLASH_MACRO_0_FREE_SFLASH349 EQU 0x0ffff35d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH350 -CYREG_SFLASH_MACRO_0_FREE_SFLASH350 EQU 0x0ffff55e +CYREG_SFLASH_MACRO_0_FREE_SFLASH350 EQU 0x0ffff35e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH351 -CYREG_SFLASH_MACRO_0_FREE_SFLASH351 EQU 0x0ffff55f +CYREG_SFLASH_MACRO_0_FREE_SFLASH351 EQU 0x0ffff35f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH352 -CYREG_SFLASH_MACRO_0_FREE_SFLASH352 EQU 0x0ffff560 +CYREG_SFLASH_MACRO_0_FREE_SFLASH352 EQU 0x0ffff360 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH353 -CYREG_SFLASH_MACRO_0_FREE_SFLASH353 EQU 0x0ffff561 +CYREG_SFLASH_MACRO_0_FREE_SFLASH353 EQU 0x0ffff361 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH354 -CYREG_SFLASH_MACRO_0_FREE_SFLASH354 EQU 0x0ffff562 +CYREG_SFLASH_MACRO_0_FREE_SFLASH354 EQU 0x0ffff362 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH355 -CYREG_SFLASH_MACRO_0_FREE_SFLASH355 EQU 0x0ffff563 +CYREG_SFLASH_MACRO_0_FREE_SFLASH355 EQU 0x0ffff363 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH356 -CYREG_SFLASH_MACRO_0_FREE_SFLASH356 EQU 0x0ffff564 +CYREG_SFLASH_MACRO_0_FREE_SFLASH356 EQU 0x0ffff364 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH357 -CYREG_SFLASH_MACRO_0_FREE_SFLASH357 EQU 0x0ffff565 +CYREG_SFLASH_MACRO_0_FREE_SFLASH357 EQU 0x0ffff365 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH358 -CYREG_SFLASH_MACRO_0_FREE_SFLASH358 EQU 0x0ffff566 +CYREG_SFLASH_MACRO_0_FREE_SFLASH358 EQU 0x0ffff366 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH359 -CYREG_SFLASH_MACRO_0_FREE_SFLASH359 EQU 0x0ffff567 +CYREG_SFLASH_MACRO_0_FREE_SFLASH359 EQU 0x0ffff367 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH360 -CYREG_SFLASH_MACRO_0_FREE_SFLASH360 EQU 0x0ffff568 +CYREG_SFLASH_MACRO_0_FREE_SFLASH360 EQU 0x0ffff368 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH361 -CYREG_SFLASH_MACRO_0_FREE_SFLASH361 EQU 0x0ffff569 +CYREG_SFLASH_MACRO_0_FREE_SFLASH361 EQU 0x0ffff369 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH362 -CYREG_SFLASH_MACRO_0_FREE_SFLASH362 EQU 0x0ffff56a +CYREG_SFLASH_MACRO_0_FREE_SFLASH362 EQU 0x0ffff36a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH363 -CYREG_SFLASH_MACRO_0_FREE_SFLASH363 EQU 0x0ffff56b +CYREG_SFLASH_MACRO_0_FREE_SFLASH363 EQU 0x0ffff36b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH364 -CYREG_SFLASH_MACRO_0_FREE_SFLASH364 EQU 0x0ffff56c +CYREG_SFLASH_MACRO_0_FREE_SFLASH364 EQU 0x0ffff36c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH365 -CYREG_SFLASH_MACRO_0_FREE_SFLASH365 EQU 0x0ffff56d +CYREG_SFLASH_MACRO_0_FREE_SFLASH365 EQU 0x0ffff36d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH366 -CYREG_SFLASH_MACRO_0_FREE_SFLASH366 EQU 0x0ffff56e +CYREG_SFLASH_MACRO_0_FREE_SFLASH366 EQU 0x0ffff36e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH367 -CYREG_SFLASH_MACRO_0_FREE_SFLASH367 EQU 0x0ffff56f +CYREG_SFLASH_MACRO_0_FREE_SFLASH367 EQU 0x0ffff36f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH368 -CYREG_SFLASH_MACRO_0_FREE_SFLASH368 EQU 0x0ffff570 +CYREG_SFLASH_MACRO_0_FREE_SFLASH368 EQU 0x0ffff370 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH369 -CYREG_SFLASH_MACRO_0_FREE_SFLASH369 EQU 0x0ffff571 +CYREG_SFLASH_MACRO_0_FREE_SFLASH369 EQU 0x0ffff371 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH370 -CYREG_SFLASH_MACRO_0_FREE_SFLASH370 EQU 0x0ffff572 +CYREG_SFLASH_MACRO_0_FREE_SFLASH370 EQU 0x0ffff372 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH371 -CYREG_SFLASH_MACRO_0_FREE_SFLASH371 EQU 0x0ffff573 +CYREG_SFLASH_MACRO_0_FREE_SFLASH371 EQU 0x0ffff373 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH372 -CYREG_SFLASH_MACRO_0_FREE_SFLASH372 EQU 0x0ffff574 +CYREG_SFLASH_MACRO_0_FREE_SFLASH372 EQU 0x0ffff374 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH373 -CYREG_SFLASH_MACRO_0_FREE_SFLASH373 EQU 0x0ffff575 +CYREG_SFLASH_MACRO_0_FREE_SFLASH373 EQU 0x0ffff375 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH374 -CYREG_SFLASH_MACRO_0_FREE_SFLASH374 EQU 0x0ffff576 +CYREG_SFLASH_MACRO_0_FREE_SFLASH374 EQU 0x0ffff376 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH375 -CYREG_SFLASH_MACRO_0_FREE_SFLASH375 EQU 0x0ffff577 +CYREG_SFLASH_MACRO_0_FREE_SFLASH375 EQU 0x0ffff377 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH376 -CYREG_SFLASH_MACRO_0_FREE_SFLASH376 EQU 0x0ffff578 +CYREG_SFLASH_MACRO_0_FREE_SFLASH376 EQU 0x0ffff378 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH377 -CYREG_SFLASH_MACRO_0_FREE_SFLASH377 EQU 0x0ffff579 +CYREG_SFLASH_MACRO_0_FREE_SFLASH377 EQU 0x0ffff379 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH378 -CYREG_SFLASH_MACRO_0_FREE_SFLASH378 EQU 0x0ffff57a +CYREG_SFLASH_MACRO_0_FREE_SFLASH378 EQU 0x0ffff37a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH379 -CYREG_SFLASH_MACRO_0_FREE_SFLASH379 EQU 0x0ffff57b +CYREG_SFLASH_MACRO_0_FREE_SFLASH379 EQU 0x0ffff37b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH380 -CYREG_SFLASH_MACRO_0_FREE_SFLASH380 EQU 0x0ffff57c +CYREG_SFLASH_MACRO_0_FREE_SFLASH380 EQU 0x0ffff37c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH381 -CYREG_SFLASH_MACRO_0_FREE_SFLASH381 EQU 0x0ffff57d +CYREG_SFLASH_MACRO_0_FREE_SFLASH381 EQU 0x0ffff37d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH382 -CYREG_SFLASH_MACRO_0_FREE_SFLASH382 EQU 0x0ffff57e +CYREG_SFLASH_MACRO_0_FREE_SFLASH382 EQU 0x0ffff37e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH383 -CYREG_SFLASH_MACRO_0_FREE_SFLASH383 EQU 0x0ffff57f +CYREG_SFLASH_MACRO_0_FREE_SFLASH383 EQU 0x0ffff37f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH384 -CYREG_SFLASH_MACRO_0_FREE_SFLASH384 EQU 0x0ffff580 +CYREG_SFLASH_MACRO_0_FREE_SFLASH384 EQU 0x0ffff380 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH385 -CYREG_SFLASH_MACRO_0_FREE_SFLASH385 EQU 0x0ffff581 +CYREG_SFLASH_MACRO_0_FREE_SFLASH385 EQU 0x0ffff381 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH386 -CYREG_SFLASH_MACRO_0_FREE_SFLASH386 EQU 0x0ffff582 +CYREG_SFLASH_MACRO_0_FREE_SFLASH386 EQU 0x0ffff382 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH387 -CYREG_SFLASH_MACRO_0_FREE_SFLASH387 EQU 0x0ffff583 +CYREG_SFLASH_MACRO_0_FREE_SFLASH387 EQU 0x0ffff383 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH388 -CYREG_SFLASH_MACRO_0_FREE_SFLASH388 EQU 0x0ffff584 +CYREG_SFLASH_MACRO_0_FREE_SFLASH388 EQU 0x0ffff384 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH389 -CYREG_SFLASH_MACRO_0_FREE_SFLASH389 EQU 0x0ffff585 +CYREG_SFLASH_MACRO_0_FREE_SFLASH389 EQU 0x0ffff385 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH390 -CYREG_SFLASH_MACRO_0_FREE_SFLASH390 EQU 0x0ffff586 +CYREG_SFLASH_MACRO_0_FREE_SFLASH390 EQU 0x0ffff386 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH391 -CYREG_SFLASH_MACRO_0_FREE_SFLASH391 EQU 0x0ffff587 +CYREG_SFLASH_MACRO_0_FREE_SFLASH391 EQU 0x0ffff387 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH392 -CYREG_SFLASH_MACRO_0_FREE_SFLASH392 EQU 0x0ffff588 +CYREG_SFLASH_MACRO_0_FREE_SFLASH392 EQU 0x0ffff388 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH393 -CYREG_SFLASH_MACRO_0_FREE_SFLASH393 EQU 0x0ffff589 +CYREG_SFLASH_MACRO_0_FREE_SFLASH393 EQU 0x0ffff389 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH394 -CYREG_SFLASH_MACRO_0_FREE_SFLASH394 EQU 0x0ffff58a +CYREG_SFLASH_MACRO_0_FREE_SFLASH394 EQU 0x0ffff38a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH395 -CYREG_SFLASH_MACRO_0_FREE_SFLASH395 EQU 0x0ffff58b +CYREG_SFLASH_MACRO_0_FREE_SFLASH395 EQU 0x0ffff38b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH396 -CYREG_SFLASH_MACRO_0_FREE_SFLASH396 EQU 0x0ffff58c +CYREG_SFLASH_MACRO_0_FREE_SFLASH396 EQU 0x0ffff38c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH397 -CYREG_SFLASH_MACRO_0_FREE_SFLASH397 EQU 0x0ffff58d +CYREG_SFLASH_MACRO_0_FREE_SFLASH397 EQU 0x0ffff38d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH398 -CYREG_SFLASH_MACRO_0_FREE_SFLASH398 EQU 0x0ffff58e +CYREG_SFLASH_MACRO_0_FREE_SFLASH398 EQU 0x0ffff38e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH399 -CYREG_SFLASH_MACRO_0_FREE_SFLASH399 EQU 0x0ffff58f +CYREG_SFLASH_MACRO_0_FREE_SFLASH399 EQU 0x0ffff38f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH400 -CYREG_SFLASH_MACRO_0_FREE_SFLASH400 EQU 0x0ffff590 +CYREG_SFLASH_MACRO_0_FREE_SFLASH400 EQU 0x0ffff390 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH401 -CYREG_SFLASH_MACRO_0_FREE_SFLASH401 EQU 0x0ffff591 +CYREG_SFLASH_MACRO_0_FREE_SFLASH401 EQU 0x0ffff391 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH402 -CYREG_SFLASH_MACRO_0_FREE_SFLASH402 EQU 0x0ffff592 +CYREG_SFLASH_MACRO_0_FREE_SFLASH402 EQU 0x0ffff392 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH403 -CYREG_SFLASH_MACRO_0_FREE_SFLASH403 EQU 0x0ffff593 +CYREG_SFLASH_MACRO_0_FREE_SFLASH403 EQU 0x0ffff393 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH404 -CYREG_SFLASH_MACRO_0_FREE_SFLASH404 EQU 0x0ffff594 +CYREG_SFLASH_MACRO_0_FREE_SFLASH404 EQU 0x0ffff394 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH405 -CYREG_SFLASH_MACRO_0_FREE_SFLASH405 EQU 0x0ffff595 +CYREG_SFLASH_MACRO_0_FREE_SFLASH405 EQU 0x0ffff395 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH406 -CYREG_SFLASH_MACRO_0_FREE_SFLASH406 EQU 0x0ffff596 +CYREG_SFLASH_MACRO_0_FREE_SFLASH406 EQU 0x0ffff396 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH407 -CYREG_SFLASH_MACRO_0_FREE_SFLASH407 EQU 0x0ffff597 +CYREG_SFLASH_MACRO_0_FREE_SFLASH407 EQU 0x0ffff397 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH408 -CYREG_SFLASH_MACRO_0_FREE_SFLASH408 EQU 0x0ffff598 +CYREG_SFLASH_MACRO_0_FREE_SFLASH408 EQU 0x0ffff398 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH409 -CYREG_SFLASH_MACRO_0_FREE_SFLASH409 EQU 0x0ffff599 +CYREG_SFLASH_MACRO_0_FREE_SFLASH409 EQU 0x0ffff399 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH410 -CYREG_SFLASH_MACRO_0_FREE_SFLASH410 EQU 0x0ffff59a +CYREG_SFLASH_MACRO_0_FREE_SFLASH410 EQU 0x0ffff39a ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH411 -CYREG_SFLASH_MACRO_0_FREE_SFLASH411 EQU 0x0ffff59b +CYREG_SFLASH_MACRO_0_FREE_SFLASH411 EQU 0x0ffff39b ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH412 -CYREG_SFLASH_MACRO_0_FREE_SFLASH412 EQU 0x0ffff59c +CYREG_SFLASH_MACRO_0_FREE_SFLASH412 EQU 0x0ffff39c ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH413 -CYREG_SFLASH_MACRO_0_FREE_SFLASH413 EQU 0x0ffff59d +CYREG_SFLASH_MACRO_0_FREE_SFLASH413 EQU 0x0ffff39d ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH414 -CYREG_SFLASH_MACRO_0_FREE_SFLASH414 EQU 0x0ffff59e +CYREG_SFLASH_MACRO_0_FREE_SFLASH414 EQU 0x0ffff39e ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH415 -CYREG_SFLASH_MACRO_0_FREE_SFLASH415 EQU 0x0ffff59f +CYREG_SFLASH_MACRO_0_FREE_SFLASH415 EQU 0x0ffff39f ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH416 -CYREG_SFLASH_MACRO_0_FREE_SFLASH416 EQU 0x0ffff5a0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH416 EQU 0x0ffff3a0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH417 -CYREG_SFLASH_MACRO_0_FREE_SFLASH417 EQU 0x0ffff5a1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH417 EQU 0x0ffff3a1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH418 -CYREG_SFLASH_MACRO_0_FREE_SFLASH418 EQU 0x0ffff5a2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH418 EQU 0x0ffff3a2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH419 -CYREG_SFLASH_MACRO_0_FREE_SFLASH419 EQU 0x0ffff5a3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH419 EQU 0x0ffff3a3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH420 -CYREG_SFLASH_MACRO_0_FREE_SFLASH420 EQU 0x0ffff5a4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH420 EQU 0x0ffff3a4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH421 -CYREG_SFLASH_MACRO_0_FREE_SFLASH421 EQU 0x0ffff5a5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH421 EQU 0x0ffff3a5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH422 -CYREG_SFLASH_MACRO_0_FREE_SFLASH422 EQU 0x0ffff5a6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH422 EQU 0x0ffff3a6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH423 -CYREG_SFLASH_MACRO_0_FREE_SFLASH423 EQU 0x0ffff5a7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH423 EQU 0x0ffff3a7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH424 -CYREG_SFLASH_MACRO_0_FREE_SFLASH424 EQU 0x0ffff5a8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH424 EQU 0x0ffff3a8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH425 -CYREG_SFLASH_MACRO_0_FREE_SFLASH425 EQU 0x0ffff5a9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH425 EQU 0x0ffff3a9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH426 -CYREG_SFLASH_MACRO_0_FREE_SFLASH426 EQU 0x0ffff5aa +CYREG_SFLASH_MACRO_0_FREE_SFLASH426 EQU 0x0ffff3aa ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH427 -CYREG_SFLASH_MACRO_0_FREE_SFLASH427 EQU 0x0ffff5ab +CYREG_SFLASH_MACRO_0_FREE_SFLASH427 EQU 0x0ffff3ab ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH428 -CYREG_SFLASH_MACRO_0_FREE_SFLASH428 EQU 0x0ffff5ac +CYREG_SFLASH_MACRO_0_FREE_SFLASH428 EQU 0x0ffff3ac ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH429 -CYREG_SFLASH_MACRO_0_FREE_SFLASH429 EQU 0x0ffff5ad +CYREG_SFLASH_MACRO_0_FREE_SFLASH429 EQU 0x0ffff3ad ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH430 -CYREG_SFLASH_MACRO_0_FREE_SFLASH430 EQU 0x0ffff5ae +CYREG_SFLASH_MACRO_0_FREE_SFLASH430 EQU 0x0ffff3ae ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH431 -CYREG_SFLASH_MACRO_0_FREE_SFLASH431 EQU 0x0ffff5af +CYREG_SFLASH_MACRO_0_FREE_SFLASH431 EQU 0x0ffff3af ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH432 -CYREG_SFLASH_MACRO_0_FREE_SFLASH432 EQU 0x0ffff5b0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH432 EQU 0x0ffff3b0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH433 -CYREG_SFLASH_MACRO_0_FREE_SFLASH433 EQU 0x0ffff5b1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH433 EQU 0x0ffff3b1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH434 -CYREG_SFLASH_MACRO_0_FREE_SFLASH434 EQU 0x0ffff5b2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH434 EQU 0x0ffff3b2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH435 -CYREG_SFLASH_MACRO_0_FREE_SFLASH435 EQU 0x0ffff5b3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH435 EQU 0x0ffff3b3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH436 -CYREG_SFLASH_MACRO_0_FREE_SFLASH436 EQU 0x0ffff5b4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH436 EQU 0x0ffff3b4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH437 -CYREG_SFLASH_MACRO_0_FREE_SFLASH437 EQU 0x0ffff5b5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH437 EQU 0x0ffff3b5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH438 -CYREG_SFLASH_MACRO_0_FREE_SFLASH438 EQU 0x0ffff5b6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH438 EQU 0x0ffff3b6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH439 -CYREG_SFLASH_MACRO_0_FREE_SFLASH439 EQU 0x0ffff5b7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH439 EQU 0x0ffff3b7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH440 -CYREG_SFLASH_MACRO_0_FREE_SFLASH440 EQU 0x0ffff5b8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH440 EQU 0x0ffff3b8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH441 -CYREG_SFLASH_MACRO_0_FREE_SFLASH441 EQU 0x0ffff5b9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH441 EQU 0x0ffff3b9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH442 -CYREG_SFLASH_MACRO_0_FREE_SFLASH442 EQU 0x0ffff5ba +CYREG_SFLASH_MACRO_0_FREE_SFLASH442 EQU 0x0ffff3ba ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH443 -CYREG_SFLASH_MACRO_0_FREE_SFLASH443 EQU 0x0ffff5bb +CYREG_SFLASH_MACRO_0_FREE_SFLASH443 EQU 0x0ffff3bb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH444 -CYREG_SFLASH_MACRO_0_FREE_SFLASH444 EQU 0x0ffff5bc +CYREG_SFLASH_MACRO_0_FREE_SFLASH444 EQU 0x0ffff3bc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH445 -CYREG_SFLASH_MACRO_0_FREE_SFLASH445 EQU 0x0ffff5bd +CYREG_SFLASH_MACRO_0_FREE_SFLASH445 EQU 0x0ffff3bd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH446 -CYREG_SFLASH_MACRO_0_FREE_SFLASH446 EQU 0x0ffff5be +CYREG_SFLASH_MACRO_0_FREE_SFLASH446 EQU 0x0ffff3be ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH447 -CYREG_SFLASH_MACRO_0_FREE_SFLASH447 EQU 0x0ffff5bf +CYREG_SFLASH_MACRO_0_FREE_SFLASH447 EQU 0x0ffff3bf ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH448 -CYREG_SFLASH_MACRO_0_FREE_SFLASH448 EQU 0x0ffff5c0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH448 EQU 0x0ffff3c0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH449 -CYREG_SFLASH_MACRO_0_FREE_SFLASH449 EQU 0x0ffff5c1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH449 EQU 0x0ffff3c1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH450 -CYREG_SFLASH_MACRO_0_FREE_SFLASH450 EQU 0x0ffff5c2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH450 EQU 0x0ffff3c2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH451 -CYREG_SFLASH_MACRO_0_FREE_SFLASH451 EQU 0x0ffff5c3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH451 EQU 0x0ffff3c3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH452 -CYREG_SFLASH_MACRO_0_FREE_SFLASH452 EQU 0x0ffff5c4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH452 EQU 0x0ffff3c4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH453 -CYREG_SFLASH_MACRO_0_FREE_SFLASH453 EQU 0x0ffff5c5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH453 EQU 0x0ffff3c5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH454 -CYREG_SFLASH_MACRO_0_FREE_SFLASH454 EQU 0x0ffff5c6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH454 EQU 0x0ffff3c6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH455 -CYREG_SFLASH_MACRO_0_FREE_SFLASH455 EQU 0x0ffff5c7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH455 EQU 0x0ffff3c7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH456 -CYREG_SFLASH_MACRO_0_FREE_SFLASH456 EQU 0x0ffff5c8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH456 EQU 0x0ffff3c8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH457 -CYREG_SFLASH_MACRO_0_FREE_SFLASH457 EQU 0x0ffff5c9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH457 EQU 0x0ffff3c9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH458 -CYREG_SFLASH_MACRO_0_FREE_SFLASH458 EQU 0x0ffff5ca +CYREG_SFLASH_MACRO_0_FREE_SFLASH458 EQU 0x0ffff3ca ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH459 -CYREG_SFLASH_MACRO_0_FREE_SFLASH459 EQU 0x0ffff5cb +CYREG_SFLASH_MACRO_0_FREE_SFLASH459 EQU 0x0ffff3cb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH460 -CYREG_SFLASH_MACRO_0_FREE_SFLASH460 EQU 0x0ffff5cc +CYREG_SFLASH_MACRO_0_FREE_SFLASH460 EQU 0x0ffff3cc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH461 -CYREG_SFLASH_MACRO_0_FREE_SFLASH461 EQU 0x0ffff5cd +CYREG_SFLASH_MACRO_0_FREE_SFLASH461 EQU 0x0ffff3cd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH462 -CYREG_SFLASH_MACRO_0_FREE_SFLASH462 EQU 0x0ffff5ce +CYREG_SFLASH_MACRO_0_FREE_SFLASH462 EQU 0x0ffff3ce ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH463 -CYREG_SFLASH_MACRO_0_FREE_SFLASH463 EQU 0x0ffff5cf +CYREG_SFLASH_MACRO_0_FREE_SFLASH463 EQU 0x0ffff3cf ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH464 -CYREG_SFLASH_MACRO_0_FREE_SFLASH464 EQU 0x0ffff5d0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH464 EQU 0x0ffff3d0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH465 -CYREG_SFLASH_MACRO_0_FREE_SFLASH465 EQU 0x0ffff5d1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH465 EQU 0x0ffff3d1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH466 -CYREG_SFLASH_MACRO_0_FREE_SFLASH466 EQU 0x0ffff5d2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH466 EQU 0x0ffff3d2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH467 -CYREG_SFLASH_MACRO_0_FREE_SFLASH467 EQU 0x0ffff5d3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH467 EQU 0x0ffff3d3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH468 -CYREG_SFLASH_MACRO_0_FREE_SFLASH468 EQU 0x0ffff5d4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH468 EQU 0x0ffff3d4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH469 -CYREG_SFLASH_MACRO_0_FREE_SFLASH469 EQU 0x0ffff5d5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH469 EQU 0x0ffff3d5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH470 -CYREG_SFLASH_MACRO_0_FREE_SFLASH470 EQU 0x0ffff5d6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH470 EQU 0x0ffff3d6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH471 -CYREG_SFLASH_MACRO_0_FREE_SFLASH471 EQU 0x0ffff5d7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH471 EQU 0x0ffff3d7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH472 -CYREG_SFLASH_MACRO_0_FREE_SFLASH472 EQU 0x0ffff5d8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH472 EQU 0x0ffff3d8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH473 -CYREG_SFLASH_MACRO_0_FREE_SFLASH473 EQU 0x0ffff5d9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH473 EQU 0x0ffff3d9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH474 -CYREG_SFLASH_MACRO_0_FREE_SFLASH474 EQU 0x0ffff5da +CYREG_SFLASH_MACRO_0_FREE_SFLASH474 EQU 0x0ffff3da ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH475 -CYREG_SFLASH_MACRO_0_FREE_SFLASH475 EQU 0x0ffff5db +CYREG_SFLASH_MACRO_0_FREE_SFLASH475 EQU 0x0ffff3db ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH476 -CYREG_SFLASH_MACRO_0_FREE_SFLASH476 EQU 0x0ffff5dc +CYREG_SFLASH_MACRO_0_FREE_SFLASH476 EQU 0x0ffff3dc ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH477 -CYREG_SFLASH_MACRO_0_FREE_SFLASH477 EQU 0x0ffff5dd +CYREG_SFLASH_MACRO_0_FREE_SFLASH477 EQU 0x0ffff3dd ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH478 -CYREG_SFLASH_MACRO_0_FREE_SFLASH478 EQU 0x0ffff5de +CYREG_SFLASH_MACRO_0_FREE_SFLASH478 EQU 0x0ffff3de ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH479 -CYREG_SFLASH_MACRO_0_FREE_SFLASH479 EQU 0x0ffff5df +CYREG_SFLASH_MACRO_0_FREE_SFLASH479 EQU 0x0ffff3df ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH480 -CYREG_SFLASH_MACRO_0_FREE_SFLASH480 EQU 0x0ffff5e0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH480 EQU 0x0ffff3e0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH481 -CYREG_SFLASH_MACRO_0_FREE_SFLASH481 EQU 0x0ffff5e1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH481 EQU 0x0ffff3e1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH482 -CYREG_SFLASH_MACRO_0_FREE_SFLASH482 EQU 0x0ffff5e2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH482 EQU 0x0ffff3e2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH483 -CYREG_SFLASH_MACRO_0_FREE_SFLASH483 EQU 0x0ffff5e3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH483 EQU 0x0ffff3e3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH484 -CYREG_SFLASH_MACRO_0_FREE_SFLASH484 EQU 0x0ffff5e4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH484 EQU 0x0ffff3e4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH485 -CYREG_SFLASH_MACRO_0_FREE_SFLASH485 EQU 0x0ffff5e5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH485 EQU 0x0ffff3e5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH486 -CYREG_SFLASH_MACRO_0_FREE_SFLASH486 EQU 0x0ffff5e6 +CYREG_SFLASH_MACRO_0_FREE_SFLASH486 EQU 0x0ffff3e6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH487 -CYREG_SFLASH_MACRO_0_FREE_SFLASH487 EQU 0x0ffff5e7 +CYREG_SFLASH_MACRO_0_FREE_SFLASH487 EQU 0x0ffff3e7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH488 -CYREG_SFLASH_MACRO_0_FREE_SFLASH488 EQU 0x0ffff5e8 +CYREG_SFLASH_MACRO_0_FREE_SFLASH488 EQU 0x0ffff3e8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH489 -CYREG_SFLASH_MACRO_0_FREE_SFLASH489 EQU 0x0ffff5e9 +CYREG_SFLASH_MACRO_0_FREE_SFLASH489 EQU 0x0ffff3e9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH490 -CYREG_SFLASH_MACRO_0_FREE_SFLASH490 EQU 0x0ffff5ea +CYREG_SFLASH_MACRO_0_FREE_SFLASH490 EQU 0x0ffff3ea ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH491 -CYREG_SFLASH_MACRO_0_FREE_SFLASH491 EQU 0x0ffff5eb +CYREG_SFLASH_MACRO_0_FREE_SFLASH491 EQU 0x0ffff3eb ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH492 -CYREG_SFLASH_MACRO_0_FREE_SFLASH492 EQU 0x0ffff5ec +CYREG_SFLASH_MACRO_0_FREE_SFLASH492 EQU 0x0ffff3ec ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH493 -CYREG_SFLASH_MACRO_0_FREE_SFLASH493 EQU 0x0ffff5ed +CYREG_SFLASH_MACRO_0_FREE_SFLASH493 EQU 0x0ffff3ed ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH494 -CYREG_SFLASH_MACRO_0_FREE_SFLASH494 EQU 0x0ffff5ee +CYREG_SFLASH_MACRO_0_FREE_SFLASH494 EQU 0x0ffff3ee ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH495 -CYREG_SFLASH_MACRO_0_FREE_SFLASH495 EQU 0x0ffff5ef +CYREG_SFLASH_MACRO_0_FREE_SFLASH495 EQU 0x0ffff3ef ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH496 -CYREG_SFLASH_MACRO_0_FREE_SFLASH496 EQU 0x0ffff5f0 +CYREG_SFLASH_MACRO_0_FREE_SFLASH496 EQU 0x0ffff3f0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH497 -CYREG_SFLASH_MACRO_0_FREE_SFLASH497 EQU 0x0ffff5f1 +CYREG_SFLASH_MACRO_0_FREE_SFLASH497 EQU 0x0ffff3f1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH498 -CYREG_SFLASH_MACRO_0_FREE_SFLASH498 EQU 0x0ffff5f2 +CYREG_SFLASH_MACRO_0_FREE_SFLASH498 EQU 0x0ffff3f2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH499 -CYREG_SFLASH_MACRO_0_FREE_SFLASH499 EQU 0x0ffff5f3 +CYREG_SFLASH_MACRO_0_FREE_SFLASH499 EQU 0x0ffff3f3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH500 -CYREG_SFLASH_MACRO_0_FREE_SFLASH500 EQU 0x0ffff5f4 +CYREG_SFLASH_MACRO_0_FREE_SFLASH500 EQU 0x0ffff3f4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH501 -CYREG_SFLASH_MACRO_0_FREE_SFLASH501 EQU 0x0ffff5f5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH502 -CYREG_SFLASH_MACRO_0_FREE_SFLASH502 EQU 0x0ffff5f6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH503 -CYREG_SFLASH_MACRO_0_FREE_SFLASH503 EQU 0x0ffff5f7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH504 -CYREG_SFLASH_MACRO_0_FREE_SFLASH504 EQU 0x0ffff5f8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH505 -CYREG_SFLASH_MACRO_0_FREE_SFLASH505 EQU 0x0ffff5f9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH506 -CYREG_SFLASH_MACRO_0_FREE_SFLASH506 EQU 0x0ffff5fa - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH507 -CYREG_SFLASH_MACRO_0_FREE_SFLASH507 EQU 0x0ffff5fb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH508 -CYREG_SFLASH_MACRO_0_FREE_SFLASH508 EQU 0x0ffff5fc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH509 -CYREG_SFLASH_MACRO_0_FREE_SFLASH509 EQU 0x0ffff5fd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH510 -CYREG_SFLASH_MACRO_0_FREE_SFLASH510 EQU 0x0ffff5fe - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH511 -CYREG_SFLASH_MACRO_0_FREE_SFLASH511 EQU 0x0ffff5ff - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH512 -CYREG_SFLASH_MACRO_0_FREE_SFLASH512 EQU 0x0ffff600 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH513 -CYREG_SFLASH_MACRO_0_FREE_SFLASH513 EQU 0x0ffff601 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH514 -CYREG_SFLASH_MACRO_0_FREE_SFLASH514 EQU 0x0ffff602 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH515 -CYREG_SFLASH_MACRO_0_FREE_SFLASH515 EQU 0x0ffff603 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH516 -CYREG_SFLASH_MACRO_0_FREE_SFLASH516 EQU 0x0ffff604 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH517 -CYREG_SFLASH_MACRO_0_FREE_SFLASH517 EQU 0x0ffff605 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH518 -CYREG_SFLASH_MACRO_0_FREE_SFLASH518 EQU 0x0ffff606 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH519 -CYREG_SFLASH_MACRO_0_FREE_SFLASH519 EQU 0x0ffff607 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH520 -CYREG_SFLASH_MACRO_0_FREE_SFLASH520 EQU 0x0ffff608 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH521 -CYREG_SFLASH_MACRO_0_FREE_SFLASH521 EQU 0x0ffff609 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH522 -CYREG_SFLASH_MACRO_0_FREE_SFLASH522 EQU 0x0ffff60a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH523 -CYREG_SFLASH_MACRO_0_FREE_SFLASH523 EQU 0x0ffff60b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH524 -CYREG_SFLASH_MACRO_0_FREE_SFLASH524 EQU 0x0ffff60c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH525 -CYREG_SFLASH_MACRO_0_FREE_SFLASH525 EQU 0x0ffff60d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH526 -CYREG_SFLASH_MACRO_0_FREE_SFLASH526 EQU 0x0ffff60e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH527 -CYREG_SFLASH_MACRO_0_FREE_SFLASH527 EQU 0x0ffff60f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH528 -CYREG_SFLASH_MACRO_0_FREE_SFLASH528 EQU 0x0ffff610 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH529 -CYREG_SFLASH_MACRO_0_FREE_SFLASH529 EQU 0x0ffff611 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH530 -CYREG_SFLASH_MACRO_0_FREE_SFLASH530 EQU 0x0ffff612 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH531 -CYREG_SFLASH_MACRO_0_FREE_SFLASH531 EQU 0x0ffff613 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH532 -CYREG_SFLASH_MACRO_0_FREE_SFLASH532 EQU 0x0ffff614 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH533 -CYREG_SFLASH_MACRO_0_FREE_SFLASH533 EQU 0x0ffff615 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH534 -CYREG_SFLASH_MACRO_0_FREE_SFLASH534 EQU 0x0ffff616 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH535 -CYREG_SFLASH_MACRO_0_FREE_SFLASH535 EQU 0x0ffff617 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH536 -CYREG_SFLASH_MACRO_0_FREE_SFLASH536 EQU 0x0ffff618 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH537 -CYREG_SFLASH_MACRO_0_FREE_SFLASH537 EQU 0x0ffff619 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH538 -CYREG_SFLASH_MACRO_0_FREE_SFLASH538 EQU 0x0ffff61a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH539 -CYREG_SFLASH_MACRO_0_FREE_SFLASH539 EQU 0x0ffff61b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH540 -CYREG_SFLASH_MACRO_0_FREE_SFLASH540 EQU 0x0ffff61c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH541 -CYREG_SFLASH_MACRO_0_FREE_SFLASH541 EQU 0x0ffff61d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH542 -CYREG_SFLASH_MACRO_0_FREE_SFLASH542 EQU 0x0ffff61e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH543 -CYREG_SFLASH_MACRO_0_FREE_SFLASH543 EQU 0x0ffff61f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH544 -CYREG_SFLASH_MACRO_0_FREE_SFLASH544 EQU 0x0ffff620 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH545 -CYREG_SFLASH_MACRO_0_FREE_SFLASH545 EQU 0x0ffff621 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH546 -CYREG_SFLASH_MACRO_0_FREE_SFLASH546 EQU 0x0ffff622 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH547 -CYREG_SFLASH_MACRO_0_FREE_SFLASH547 EQU 0x0ffff623 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH548 -CYREG_SFLASH_MACRO_0_FREE_SFLASH548 EQU 0x0ffff624 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH549 -CYREG_SFLASH_MACRO_0_FREE_SFLASH549 EQU 0x0ffff625 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH550 -CYREG_SFLASH_MACRO_0_FREE_SFLASH550 EQU 0x0ffff626 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH551 -CYREG_SFLASH_MACRO_0_FREE_SFLASH551 EQU 0x0ffff627 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH552 -CYREG_SFLASH_MACRO_0_FREE_SFLASH552 EQU 0x0ffff628 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH553 -CYREG_SFLASH_MACRO_0_FREE_SFLASH553 EQU 0x0ffff629 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH554 -CYREG_SFLASH_MACRO_0_FREE_SFLASH554 EQU 0x0ffff62a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH555 -CYREG_SFLASH_MACRO_0_FREE_SFLASH555 EQU 0x0ffff62b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH556 -CYREG_SFLASH_MACRO_0_FREE_SFLASH556 EQU 0x0ffff62c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH557 -CYREG_SFLASH_MACRO_0_FREE_SFLASH557 EQU 0x0ffff62d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH558 -CYREG_SFLASH_MACRO_0_FREE_SFLASH558 EQU 0x0ffff62e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH559 -CYREG_SFLASH_MACRO_0_FREE_SFLASH559 EQU 0x0ffff62f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH560 -CYREG_SFLASH_MACRO_0_FREE_SFLASH560 EQU 0x0ffff630 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH561 -CYREG_SFLASH_MACRO_0_FREE_SFLASH561 EQU 0x0ffff631 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH562 -CYREG_SFLASH_MACRO_0_FREE_SFLASH562 EQU 0x0ffff632 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH563 -CYREG_SFLASH_MACRO_0_FREE_SFLASH563 EQU 0x0ffff633 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH564 -CYREG_SFLASH_MACRO_0_FREE_SFLASH564 EQU 0x0ffff634 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH565 -CYREG_SFLASH_MACRO_0_FREE_SFLASH565 EQU 0x0ffff635 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH566 -CYREG_SFLASH_MACRO_0_FREE_SFLASH566 EQU 0x0ffff636 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH567 -CYREG_SFLASH_MACRO_0_FREE_SFLASH567 EQU 0x0ffff637 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH568 -CYREG_SFLASH_MACRO_0_FREE_SFLASH568 EQU 0x0ffff638 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH569 -CYREG_SFLASH_MACRO_0_FREE_SFLASH569 EQU 0x0ffff639 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH570 -CYREG_SFLASH_MACRO_0_FREE_SFLASH570 EQU 0x0ffff63a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH571 -CYREG_SFLASH_MACRO_0_FREE_SFLASH571 EQU 0x0ffff63b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH572 -CYREG_SFLASH_MACRO_0_FREE_SFLASH572 EQU 0x0ffff63c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH573 -CYREG_SFLASH_MACRO_0_FREE_SFLASH573 EQU 0x0ffff63d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH574 -CYREG_SFLASH_MACRO_0_FREE_SFLASH574 EQU 0x0ffff63e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH575 -CYREG_SFLASH_MACRO_0_FREE_SFLASH575 EQU 0x0ffff63f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH576 -CYREG_SFLASH_MACRO_0_FREE_SFLASH576 EQU 0x0ffff640 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH577 -CYREG_SFLASH_MACRO_0_FREE_SFLASH577 EQU 0x0ffff641 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH578 -CYREG_SFLASH_MACRO_0_FREE_SFLASH578 EQU 0x0ffff642 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH579 -CYREG_SFLASH_MACRO_0_FREE_SFLASH579 EQU 0x0ffff643 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH580 -CYREG_SFLASH_MACRO_0_FREE_SFLASH580 EQU 0x0ffff644 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH581 -CYREG_SFLASH_MACRO_0_FREE_SFLASH581 EQU 0x0ffff645 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH582 -CYREG_SFLASH_MACRO_0_FREE_SFLASH582 EQU 0x0ffff646 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH583 -CYREG_SFLASH_MACRO_0_FREE_SFLASH583 EQU 0x0ffff647 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH584 -CYREG_SFLASH_MACRO_0_FREE_SFLASH584 EQU 0x0ffff648 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH585 -CYREG_SFLASH_MACRO_0_FREE_SFLASH585 EQU 0x0ffff649 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH586 -CYREG_SFLASH_MACRO_0_FREE_SFLASH586 EQU 0x0ffff64a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH587 -CYREG_SFLASH_MACRO_0_FREE_SFLASH587 EQU 0x0ffff64b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH588 -CYREG_SFLASH_MACRO_0_FREE_SFLASH588 EQU 0x0ffff64c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH589 -CYREG_SFLASH_MACRO_0_FREE_SFLASH589 EQU 0x0ffff64d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH590 -CYREG_SFLASH_MACRO_0_FREE_SFLASH590 EQU 0x0ffff64e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH591 -CYREG_SFLASH_MACRO_0_FREE_SFLASH591 EQU 0x0ffff64f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH592 -CYREG_SFLASH_MACRO_0_FREE_SFLASH592 EQU 0x0ffff650 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH593 -CYREG_SFLASH_MACRO_0_FREE_SFLASH593 EQU 0x0ffff651 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH594 -CYREG_SFLASH_MACRO_0_FREE_SFLASH594 EQU 0x0ffff652 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH595 -CYREG_SFLASH_MACRO_0_FREE_SFLASH595 EQU 0x0ffff653 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH596 -CYREG_SFLASH_MACRO_0_FREE_SFLASH596 EQU 0x0ffff654 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH597 -CYREG_SFLASH_MACRO_0_FREE_SFLASH597 EQU 0x0ffff655 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH598 -CYREG_SFLASH_MACRO_0_FREE_SFLASH598 EQU 0x0ffff656 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH599 -CYREG_SFLASH_MACRO_0_FREE_SFLASH599 EQU 0x0ffff657 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH600 -CYREG_SFLASH_MACRO_0_FREE_SFLASH600 EQU 0x0ffff658 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH601 -CYREG_SFLASH_MACRO_0_FREE_SFLASH601 EQU 0x0ffff659 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH602 -CYREG_SFLASH_MACRO_0_FREE_SFLASH602 EQU 0x0ffff65a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH603 -CYREG_SFLASH_MACRO_0_FREE_SFLASH603 EQU 0x0ffff65b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH604 -CYREG_SFLASH_MACRO_0_FREE_SFLASH604 EQU 0x0ffff65c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH605 -CYREG_SFLASH_MACRO_0_FREE_SFLASH605 EQU 0x0ffff65d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH606 -CYREG_SFLASH_MACRO_0_FREE_SFLASH606 EQU 0x0ffff65e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH607 -CYREG_SFLASH_MACRO_0_FREE_SFLASH607 EQU 0x0ffff65f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH608 -CYREG_SFLASH_MACRO_0_FREE_SFLASH608 EQU 0x0ffff660 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH609 -CYREG_SFLASH_MACRO_0_FREE_SFLASH609 EQU 0x0ffff661 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH610 -CYREG_SFLASH_MACRO_0_FREE_SFLASH610 EQU 0x0ffff662 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH611 -CYREG_SFLASH_MACRO_0_FREE_SFLASH611 EQU 0x0ffff663 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH612 -CYREG_SFLASH_MACRO_0_FREE_SFLASH612 EQU 0x0ffff664 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH613 -CYREG_SFLASH_MACRO_0_FREE_SFLASH613 EQU 0x0ffff665 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH614 -CYREG_SFLASH_MACRO_0_FREE_SFLASH614 EQU 0x0ffff666 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH615 -CYREG_SFLASH_MACRO_0_FREE_SFLASH615 EQU 0x0ffff667 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH616 -CYREG_SFLASH_MACRO_0_FREE_SFLASH616 EQU 0x0ffff668 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH617 -CYREG_SFLASH_MACRO_0_FREE_SFLASH617 EQU 0x0ffff669 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH618 -CYREG_SFLASH_MACRO_0_FREE_SFLASH618 EQU 0x0ffff66a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH619 -CYREG_SFLASH_MACRO_0_FREE_SFLASH619 EQU 0x0ffff66b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH620 -CYREG_SFLASH_MACRO_0_FREE_SFLASH620 EQU 0x0ffff66c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH621 -CYREG_SFLASH_MACRO_0_FREE_SFLASH621 EQU 0x0ffff66d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH622 -CYREG_SFLASH_MACRO_0_FREE_SFLASH622 EQU 0x0ffff66e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH623 -CYREG_SFLASH_MACRO_0_FREE_SFLASH623 EQU 0x0ffff66f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH624 -CYREG_SFLASH_MACRO_0_FREE_SFLASH624 EQU 0x0ffff670 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH625 -CYREG_SFLASH_MACRO_0_FREE_SFLASH625 EQU 0x0ffff671 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH626 -CYREG_SFLASH_MACRO_0_FREE_SFLASH626 EQU 0x0ffff672 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH627 -CYREG_SFLASH_MACRO_0_FREE_SFLASH627 EQU 0x0ffff673 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH628 -CYREG_SFLASH_MACRO_0_FREE_SFLASH628 EQU 0x0ffff674 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH629 -CYREG_SFLASH_MACRO_0_FREE_SFLASH629 EQU 0x0ffff675 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH630 -CYREG_SFLASH_MACRO_0_FREE_SFLASH630 EQU 0x0ffff676 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH631 -CYREG_SFLASH_MACRO_0_FREE_SFLASH631 EQU 0x0ffff677 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH632 -CYREG_SFLASH_MACRO_0_FREE_SFLASH632 EQU 0x0ffff678 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH633 -CYREG_SFLASH_MACRO_0_FREE_SFLASH633 EQU 0x0ffff679 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH634 -CYREG_SFLASH_MACRO_0_FREE_SFLASH634 EQU 0x0ffff67a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH635 -CYREG_SFLASH_MACRO_0_FREE_SFLASH635 EQU 0x0ffff67b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH636 -CYREG_SFLASH_MACRO_0_FREE_SFLASH636 EQU 0x0ffff67c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH637 -CYREG_SFLASH_MACRO_0_FREE_SFLASH637 EQU 0x0ffff67d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH638 -CYREG_SFLASH_MACRO_0_FREE_SFLASH638 EQU 0x0ffff67e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH639 -CYREG_SFLASH_MACRO_0_FREE_SFLASH639 EQU 0x0ffff67f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH640 -CYREG_SFLASH_MACRO_0_FREE_SFLASH640 EQU 0x0ffff680 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH641 -CYREG_SFLASH_MACRO_0_FREE_SFLASH641 EQU 0x0ffff681 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH642 -CYREG_SFLASH_MACRO_0_FREE_SFLASH642 EQU 0x0ffff682 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH643 -CYREG_SFLASH_MACRO_0_FREE_SFLASH643 EQU 0x0ffff683 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH644 -CYREG_SFLASH_MACRO_0_FREE_SFLASH644 EQU 0x0ffff684 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH645 -CYREG_SFLASH_MACRO_0_FREE_SFLASH645 EQU 0x0ffff685 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH646 -CYREG_SFLASH_MACRO_0_FREE_SFLASH646 EQU 0x0ffff686 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH647 -CYREG_SFLASH_MACRO_0_FREE_SFLASH647 EQU 0x0ffff687 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH648 -CYREG_SFLASH_MACRO_0_FREE_SFLASH648 EQU 0x0ffff688 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH649 -CYREG_SFLASH_MACRO_0_FREE_SFLASH649 EQU 0x0ffff689 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH650 -CYREG_SFLASH_MACRO_0_FREE_SFLASH650 EQU 0x0ffff68a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH651 -CYREG_SFLASH_MACRO_0_FREE_SFLASH651 EQU 0x0ffff68b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH652 -CYREG_SFLASH_MACRO_0_FREE_SFLASH652 EQU 0x0ffff68c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH653 -CYREG_SFLASH_MACRO_0_FREE_SFLASH653 EQU 0x0ffff68d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH654 -CYREG_SFLASH_MACRO_0_FREE_SFLASH654 EQU 0x0ffff68e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH655 -CYREG_SFLASH_MACRO_0_FREE_SFLASH655 EQU 0x0ffff68f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH656 -CYREG_SFLASH_MACRO_0_FREE_SFLASH656 EQU 0x0ffff690 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH657 -CYREG_SFLASH_MACRO_0_FREE_SFLASH657 EQU 0x0ffff691 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH658 -CYREG_SFLASH_MACRO_0_FREE_SFLASH658 EQU 0x0ffff692 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH659 -CYREG_SFLASH_MACRO_0_FREE_SFLASH659 EQU 0x0ffff693 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH660 -CYREG_SFLASH_MACRO_0_FREE_SFLASH660 EQU 0x0ffff694 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH661 -CYREG_SFLASH_MACRO_0_FREE_SFLASH661 EQU 0x0ffff695 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH662 -CYREG_SFLASH_MACRO_0_FREE_SFLASH662 EQU 0x0ffff696 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH663 -CYREG_SFLASH_MACRO_0_FREE_SFLASH663 EQU 0x0ffff697 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH664 -CYREG_SFLASH_MACRO_0_FREE_SFLASH664 EQU 0x0ffff698 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH665 -CYREG_SFLASH_MACRO_0_FREE_SFLASH665 EQU 0x0ffff699 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH666 -CYREG_SFLASH_MACRO_0_FREE_SFLASH666 EQU 0x0ffff69a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH667 -CYREG_SFLASH_MACRO_0_FREE_SFLASH667 EQU 0x0ffff69b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH668 -CYREG_SFLASH_MACRO_0_FREE_SFLASH668 EQU 0x0ffff69c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH669 -CYREG_SFLASH_MACRO_0_FREE_SFLASH669 EQU 0x0ffff69d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH670 -CYREG_SFLASH_MACRO_0_FREE_SFLASH670 EQU 0x0ffff69e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH671 -CYREG_SFLASH_MACRO_0_FREE_SFLASH671 EQU 0x0ffff69f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH672 -CYREG_SFLASH_MACRO_0_FREE_SFLASH672 EQU 0x0ffff6a0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH673 -CYREG_SFLASH_MACRO_0_FREE_SFLASH673 EQU 0x0ffff6a1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH674 -CYREG_SFLASH_MACRO_0_FREE_SFLASH674 EQU 0x0ffff6a2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH675 -CYREG_SFLASH_MACRO_0_FREE_SFLASH675 EQU 0x0ffff6a3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH676 -CYREG_SFLASH_MACRO_0_FREE_SFLASH676 EQU 0x0ffff6a4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH677 -CYREG_SFLASH_MACRO_0_FREE_SFLASH677 EQU 0x0ffff6a5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH678 -CYREG_SFLASH_MACRO_0_FREE_SFLASH678 EQU 0x0ffff6a6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH679 -CYREG_SFLASH_MACRO_0_FREE_SFLASH679 EQU 0x0ffff6a7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH680 -CYREG_SFLASH_MACRO_0_FREE_SFLASH680 EQU 0x0ffff6a8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH681 -CYREG_SFLASH_MACRO_0_FREE_SFLASH681 EQU 0x0ffff6a9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH682 -CYREG_SFLASH_MACRO_0_FREE_SFLASH682 EQU 0x0ffff6aa - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH683 -CYREG_SFLASH_MACRO_0_FREE_SFLASH683 EQU 0x0ffff6ab - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH684 -CYREG_SFLASH_MACRO_0_FREE_SFLASH684 EQU 0x0ffff6ac - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH685 -CYREG_SFLASH_MACRO_0_FREE_SFLASH685 EQU 0x0ffff6ad - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH686 -CYREG_SFLASH_MACRO_0_FREE_SFLASH686 EQU 0x0ffff6ae - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH687 -CYREG_SFLASH_MACRO_0_FREE_SFLASH687 EQU 0x0ffff6af - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH688 -CYREG_SFLASH_MACRO_0_FREE_SFLASH688 EQU 0x0ffff6b0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH689 -CYREG_SFLASH_MACRO_0_FREE_SFLASH689 EQU 0x0ffff6b1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH690 -CYREG_SFLASH_MACRO_0_FREE_SFLASH690 EQU 0x0ffff6b2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH691 -CYREG_SFLASH_MACRO_0_FREE_SFLASH691 EQU 0x0ffff6b3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH692 -CYREG_SFLASH_MACRO_0_FREE_SFLASH692 EQU 0x0ffff6b4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH693 -CYREG_SFLASH_MACRO_0_FREE_SFLASH693 EQU 0x0ffff6b5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH694 -CYREG_SFLASH_MACRO_0_FREE_SFLASH694 EQU 0x0ffff6b6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH695 -CYREG_SFLASH_MACRO_0_FREE_SFLASH695 EQU 0x0ffff6b7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH696 -CYREG_SFLASH_MACRO_0_FREE_SFLASH696 EQU 0x0ffff6b8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH697 -CYREG_SFLASH_MACRO_0_FREE_SFLASH697 EQU 0x0ffff6b9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH698 -CYREG_SFLASH_MACRO_0_FREE_SFLASH698 EQU 0x0ffff6ba - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH699 -CYREG_SFLASH_MACRO_0_FREE_SFLASH699 EQU 0x0ffff6bb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH700 -CYREG_SFLASH_MACRO_0_FREE_SFLASH700 EQU 0x0ffff6bc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH701 -CYREG_SFLASH_MACRO_0_FREE_SFLASH701 EQU 0x0ffff6bd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH702 -CYREG_SFLASH_MACRO_0_FREE_SFLASH702 EQU 0x0ffff6be - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH703 -CYREG_SFLASH_MACRO_0_FREE_SFLASH703 EQU 0x0ffff6bf - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH704 -CYREG_SFLASH_MACRO_0_FREE_SFLASH704 EQU 0x0ffff6c0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH705 -CYREG_SFLASH_MACRO_0_FREE_SFLASH705 EQU 0x0ffff6c1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH706 -CYREG_SFLASH_MACRO_0_FREE_SFLASH706 EQU 0x0ffff6c2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH707 -CYREG_SFLASH_MACRO_0_FREE_SFLASH707 EQU 0x0ffff6c3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH708 -CYREG_SFLASH_MACRO_0_FREE_SFLASH708 EQU 0x0ffff6c4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH709 -CYREG_SFLASH_MACRO_0_FREE_SFLASH709 EQU 0x0ffff6c5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH710 -CYREG_SFLASH_MACRO_0_FREE_SFLASH710 EQU 0x0ffff6c6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH711 -CYREG_SFLASH_MACRO_0_FREE_SFLASH711 EQU 0x0ffff6c7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH712 -CYREG_SFLASH_MACRO_0_FREE_SFLASH712 EQU 0x0ffff6c8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH713 -CYREG_SFLASH_MACRO_0_FREE_SFLASH713 EQU 0x0ffff6c9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH714 -CYREG_SFLASH_MACRO_0_FREE_SFLASH714 EQU 0x0ffff6ca - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH715 -CYREG_SFLASH_MACRO_0_FREE_SFLASH715 EQU 0x0ffff6cb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH716 -CYREG_SFLASH_MACRO_0_FREE_SFLASH716 EQU 0x0ffff6cc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH717 -CYREG_SFLASH_MACRO_0_FREE_SFLASH717 EQU 0x0ffff6cd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH718 -CYREG_SFLASH_MACRO_0_FREE_SFLASH718 EQU 0x0ffff6ce - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH719 -CYREG_SFLASH_MACRO_0_FREE_SFLASH719 EQU 0x0ffff6cf - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH720 -CYREG_SFLASH_MACRO_0_FREE_SFLASH720 EQU 0x0ffff6d0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH721 -CYREG_SFLASH_MACRO_0_FREE_SFLASH721 EQU 0x0ffff6d1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH722 -CYREG_SFLASH_MACRO_0_FREE_SFLASH722 EQU 0x0ffff6d2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH723 -CYREG_SFLASH_MACRO_0_FREE_SFLASH723 EQU 0x0ffff6d3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH724 -CYREG_SFLASH_MACRO_0_FREE_SFLASH724 EQU 0x0ffff6d4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH725 -CYREG_SFLASH_MACRO_0_FREE_SFLASH725 EQU 0x0ffff6d5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH726 -CYREG_SFLASH_MACRO_0_FREE_SFLASH726 EQU 0x0ffff6d6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH727 -CYREG_SFLASH_MACRO_0_FREE_SFLASH727 EQU 0x0ffff6d7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH728 -CYREG_SFLASH_MACRO_0_FREE_SFLASH728 EQU 0x0ffff6d8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH729 -CYREG_SFLASH_MACRO_0_FREE_SFLASH729 EQU 0x0ffff6d9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH730 -CYREG_SFLASH_MACRO_0_FREE_SFLASH730 EQU 0x0ffff6da - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH731 -CYREG_SFLASH_MACRO_0_FREE_SFLASH731 EQU 0x0ffff6db - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH732 -CYREG_SFLASH_MACRO_0_FREE_SFLASH732 EQU 0x0ffff6dc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH733 -CYREG_SFLASH_MACRO_0_FREE_SFLASH733 EQU 0x0ffff6dd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH734 -CYREG_SFLASH_MACRO_0_FREE_SFLASH734 EQU 0x0ffff6de - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH735 -CYREG_SFLASH_MACRO_0_FREE_SFLASH735 EQU 0x0ffff6df - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH736 -CYREG_SFLASH_MACRO_0_FREE_SFLASH736 EQU 0x0ffff6e0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH737 -CYREG_SFLASH_MACRO_0_FREE_SFLASH737 EQU 0x0ffff6e1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH738 -CYREG_SFLASH_MACRO_0_FREE_SFLASH738 EQU 0x0ffff6e2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH739 -CYREG_SFLASH_MACRO_0_FREE_SFLASH739 EQU 0x0ffff6e3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH740 -CYREG_SFLASH_MACRO_0_FREE_SFLASH740 EQU 0x0ffff6e4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH741 -CYREG_SFLASH_MACRO_0_FREE_SFLASH741 EQU 0x0ffff6e5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH742 -CYREG_SFLASH_MACRO_0_FREE_SFLASH742 EQU 0x0ffff6e6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH743 -CYREG_SFLASH_MACRO_0_FREE_SFLASH743 EQU 0x0ffff6e7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH744 -CYREG_SFLASH_MACRO_0_FREE_SFLASH744 EQU 0x0ffff6e8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH745 -CYREG_SFLASH_MACRO_0_FREE_SFLASH745 EQU 0x0ffff6e9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH746 -CYREG_SFLASH_MACRO_0_FREE_SFLASH746 EQU 0x0ffff6ea - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH747 -CYREG_SFLASH_MACRO_0_FREE_SFLASH747 EQU 0x0ffff6eb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH748 -CYREG_SFLASH_MACRO_0_FREE_SFLASH748 EQU 0x0ffff6ec - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH749 -CYREG_SFLASH_MACRO_0_FREE_SFLASH749 EQU 0x0ffff6ed - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH750 -CYREG_SFLASH_MACRO_0_FREE_SFLASH750 EQU 0x0ffff6ee - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH751 -CYREG_SFLASH_MACRO_0_FREE_SFLASH751 EQU 0x0ffff6ef - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH752 -CYREG_SFLASH_MACRO_0_FREE_SFLASH752 EQU 0x0ffff6f0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH753 -CYREG_SFLASH_MACRO_0_FREE_SFLASH753 EQU 0x0ffff6f1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH754 -CYREG_SFLASH_MACRO_0_FREE_SFLASH754 EQU 0x0ffff6f2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH755 -CYREG_SFLASH_MACRO_0_FREE_SFLASH755 EQU 0x0ffff6f3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH756 -CYREG_SFLASH_MACRO_0_FREE_SFLASH756 EQU 0x0ffff6f4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH757 -CYREG_SFLASH_MACRO_0_FREE_SFLASH757 EQU 0x0ffff6f5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH758 -CYREG_SFLASH_MACRO_0_FREE_SFLASH758 EQU 0x0ffff6f6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH759 -CYREG_SFLASH_MACRO_0_FREE_SFLASH759 EQU 0x0ffff6f7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH760 -CYREG_SFLASH_MACRO_0_FREE_SFLASH760 EQU 0x0ffff6f8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH761 -CYREG_SFLASH_MACRO_0_FREE_SFLASH761 EQU 0x0ffff6f9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH762 -CYREG_SFLASH_MACRO_0_FREE_SFLASH762 EQU 0x0ffff6fa - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH763 -CYREG_SFLASH_MACRO_0_FREE_SFLASH763 EQU 0x0ffff6fb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH764 -CYREG_SFLASH_MACRO_0_FREE_SFLASH764 EQU 0x0ffff6fc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH765 -CYREG_SFLASH_MACRO_0_FREE_SFLASH765 EQU 0x0ffff6fd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH766 -CYREG_SFLASH_MACRO_0_FREE_SFLASH766 EQU 0x0ffff6fe - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH767 -CYREG_SFLASH_MACRO_0_FREE_SFLASH767 EQU 0x0ffff6ff - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH768 -CYREG_SFLASH_MACRO_0_FREE_SFLASH768 EQU 0x0ffff700 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH769 -CYREG_SFLASH_MACRO_0_FREE_SFLASH769 EQU 0x0ffff701 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH770 -CYREG_SFLASH_MACRO_0_FREE_SFLASH770 EQU 0x0ffff702 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH771 -CYREG_SFLASH_MACRO_0_FREE_SFLASH771 EQU 0x0ffff703 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH772 -CYREG_SFLASH_MACRO_0_FREE_SFLASH772 EQU 0x0ffff704 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH773 -CYREG_SFLASH_MACRO_0_FREE_SFLASH773 EQU 0x0ffff705 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH774 -CYREG_SFLASH_MACRO_0_FREE_SFLASH774 EQU 0x0ffff706 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH775 -CYREG_SFLASH_MACRO_0_FREE_SFLASH775 EQU 0x0ffff707 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH776 -CYREG_SFLASH_MACRO_0_FREE_SFLASH776 EQU 0x0ffff708 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH777 -CYREG_SFLASH_MACRO_0_FREE_SFLASH777 EQU 0x0ffff709 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH778 -CYREG_SFLASH_MACRO_0_FREE_SFLASH778 EQU 0x0ffff70a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH779 -CYREG_SFLASH_MACRO_0_FREE_SFLASH779 EQU 0x0ffff70b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH780 -CYREG_SFLASH_MACRO_0_FREE_SFLASH780 EQU 0x0ffff70c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH781 -CYREG_SFLASH_MACRO_0_FREE_SFLASH781 EQU 0x0ffff70d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH782 -CYREG_SFLASH_MACRO_0_FREE_SFLASH782 EQU 0x0ffff70e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH783 -CYREG_SFLASH_MACRO_0_FREE_SFLASH783 EQU 0x0ffff70f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH784 -CYREG_SFLASH_MACRO_0_FREE_SFLASH784 EQU 0x0ffff710 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH785 -CYREG_SFLASH_MACRO_0_FREE_SFLASH785 EQU 0x0ffff711 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH786 -CYREG_SFLASH_MACRO_0_FREE_SFLASH786 EQU 0x0ffff712 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH787 -CYREG_SFLASH_MACRO_0_FREE_SFLASH787 EQU 0x0ffff713 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH788 -CYREG_SFLASH_MACRO_0_FREE_SFLASH788 EQU 0x0ffff714 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH789 -CYREG_SFLASH_MACRO_0_FREE_SFLASH789 EQU 0x0ffff715 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH790 -CYREG_SFLASH_MACRO_0_FREE_SFLASH790 EQU 0x0ffff716 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH791 -CYREG_SFLASH_MACRO_0_FREE_SFLASH791 EQU 0x0ffff717 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH792 -CYREG_SFLASH_MACRO_0_FREE_SFLASH792 EQU 0x0ffff718 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH793 -CYREG_SFLASH_MACRO_0_FREE_SFLASH793 EQU 0x0ffff719 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH794 -CYREG_SFLASH_MACRO_0_FREE_SFLASH794 EQU 0x0ffff71a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH795 -CYREG_SFLASH_MACRO_0_FREE_SFLASH795 EQU 0x0ffff71b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH796 -CYREG_SFLASH_MACRO_0_FREE_SFLASH796 EQU 0x0ffff71c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH797 -CYREG_SFLASH_MACRO_0_FREE_SFLASH797 EQU 0x0ffff71d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH798 -CYREG_SFLASH_MACRO_0_FREE_SFLASH798 EQU 0x0ffff71e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH799 -CYREG_SFLASH_MACRO_0_FREE_SFLASH799 EQU 0x0ffff71f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH800 -CYREG_SFLASH_MACRO_0_FREE_SFLASH800 EQU 0x0ffff720 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH801 -CYREG_SFLASH_MACRO_0_FREE_SFLASH801 EQU 0x0ffff721 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH802 -CYREG_SFLASH_MACRO_0_FREE_SFLASH802 EQU 0x0ffff722 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH803 -CYREG_SFLASH_MACRO_0_FREE_SFLASH803 EQU 0x0ffff723 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH804 -CYREG_SFLASH_MACRO_0_FREE_SFLASH804 EQU 0x0ffff724 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH805 -CYREG_SFLASH_MACRO_0_FREE_SFLASH805 EQU 0x0ffff725 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH806 -CYREG_SFLASH_MACRO_0_FREE_SFLASH806 EQU 0x0ffff726 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH807 -CYREG_SFLASH_MACRO_0_FREE_SFLASH807 EQU 0x0ffff727 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH808 -CYREG_SFLASH_MACRO_0_FREE_SFLASH808 EQU 0x0ffff728 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH809 -CYREG_SFLASH_MACRO_0_FREE_SFLASH809 EQU 0x0ffff729 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH810 -CYREG_SFLASH_MACRO_0_FREE_SFLASH810 EQU 0x0ffff72a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH811 -CYREG_SFLASH_MACRO_0_FREE_SFLASH811 EQU 0x0ffff72b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH812 -CYREG_SFLASH_MACRO_0_FREE_SFLASH812 EQU 0x0ffff72c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH813 -CYREG_SFLASH_MACRO_0_FREE_SFLASH813 EQU 0x0ffff72d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH814 -CYREG_SFLASH_MACRO_0_FREE_SFLASH814 EQU 0x0ffff72e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH815 -CYREG_SFLASH_MACRO_0_FREE_SFLASH815 EQU 0x0ffff72f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH816 -CYREG_SFLASH_MACRO_0_FREE_SFLASH816 EQU 0x0ffff730 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH817 -CYREG_SFLASH_MACRO_0_FREE_SFLASH817 EQU 0x0ffff731 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH818 -CYREG_SFLASH_MACRO_0_FREE_SFLASH818 EQU 0x0ffff732 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH819 -CYREG_SFLASH_MACRO_0_FREE_SFLASH819 EQU 0x0ffff733 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH820 -CYREG_SFLASH_MACRO_0_FREE_SFLASH820 EQU 0x0ffff734 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH821 -CYREG_SFLASH_MACRO_0_FREE_SFLASH821 EQU 0x0ffff735 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH822 -CYREG_SFLASH_MACRO_0_FREE_SFLASH822 EQU 0x0ffff736 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH823 -CYREG_SFLASH_MACRO_0_FREE_SFLASH823 EQU 0x0ffff737 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH824 -CYREG_SFLASH_MACRO_0_FREE_SFLASH824 EQU 0x0ffff738 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH825 -CYREG_SFLASH_MACRO_0_FREE_SFLASH825 EQU 0x0ffff739 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH826 -CYREG_SFLASH_MACRO_0_FREE_SFLASH826 EQU 0x0ffff73a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH827 -CYREG_SFLASH_MACRO_0_FREE_SFLASH827 EQU 0x0ffff73b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH828 -CYREG_SFLASH_MACRO_0_FREE_SFLASH828 EQU 0x0ffff73c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH829 -CYREG_SFLASH_MACRO_0_FREE_SFLASH829 EQU 0x0ffff73d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH830 -CYREG_SFLASH_MACRO_0_FREE_SFLASH830 EQU 0x0ffff73e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH831 -CYREG_SFLASH_MACRO_0_FREE_SFLASH831 EQU 0x0ffff73f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH832 -CYREG_SFLASH_MACRO_0_FREE_SFLASH832 EQU 0x0ffff740 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH833 -CYREG_SFLASH_MACRO_0_FREE_SFLASH833 EQU 0x0ffff741 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH834 -CYREG_SFLASH_MACRO_0_FREE_SFLASH834 EQU 0x0ffff742 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH835 -CYREG_SFLASH_MACRO_0_FREE_SFLASH835 EQU 0x0ffff743 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH836 -CYREG_SFLASH_MACRO_0_FREE_SFLASH836 EQU 0x0ffff744 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH837 -CYREG_SFLASH_MACRO_0_FREE_SFLASH837 EQU 0x0ffff745 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH838 -CYREG_SFLASH_MACRO_0_FREE_SFLASH838 EQU 0x0ffff746 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH839 -CYREG_SFLASH_MACRO_0_FREE_SFLASH839 EQU 0x0ffff747 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH840 -CYREG_SFLASH_MACRO_0_FREE_SFLASH840 EQU 0x0ffff748 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH841 -CYREG_SFLASH_MACRO_0_FREE_SFLASH841 EQU 0x0ffff749 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH842 -CYREG_SFLASH_MACRO_0_FREE_SFLASH842 EQU 0x0ffff74a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH843 -CYREG_SFLASH_MACRO_0_FREE_SFLASH843 EQU 0x0ffff74b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH844 -CYREG_SFLASH_MACRO_0_FREE_SFLASH844 EQU 0x0ffff74c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH845 -CYREG_SFLASH_MACRO_0_FREE_SFLASH845 EQU 0x0ffff74d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH846 -CYREG_SFLASH_MACRO_0_FREE_SFLASH846 EQU 0x0ffff74e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH847 -CYREG_SFLASH_MACRO_0_FREE_SFLASH847 EQU 0x0ffff74f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH848 -CYREG_SFLASH_MACRO_0_FREE_SFLASH848 EQU 0x0ffff750 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH849 -CYREG_SFLASH_MACRO_0_FREE_SFLASH849 EQU 0x0ffff751 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH850 -CYREG_SFLASH_MACRO_0_FREE_SFLASH850 EQU 0x0ffff752 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH851 -CYREG_SFLASH_MACRO_0_FREE_SFLASH851 EQU 0x0ffff753 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH852 -CYREG_SFLASH_MACRO_0_FREE_SFLASH852 EQU 0x0ffff754 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH853 -CYREG_SFLASH_MACRO_0_FREE_SFLASH853 EQU 0x0ffff755 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH854 -CYREG_SFLASH_MACRO_0_FREE_SFLASH854 EQU 0x0ffff756 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH855 -CYREG_SFLASH_MACRO_0_FREE_SFLASH855 EQU 0x0ffff757 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH856 -CYREG_SFLASH_MACRO_0_FREE_SFLASH856 EQU 0x0ffff758 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH857 -CYREG_SFLASH_MACRO_0_FREE_SFLASH857 EQU 0x0ffff759 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH858 -CYREG_SFLASH_MACRO_0_FREE_SFLASH858 EQU 0x0ffff75a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH859 -CYREG_SFLASH_MACRO_0_FREE_SFLASH859 EQU 0x0ffff75b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH860 -CYREG_SFLASH_MACRO_0_FREE_SFLASH860 EQU 0x0ffff75c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH861 -CYREG_SFLASH_MACRO_0_FREE_SFLASH861 EQU 0x0ffff75d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH862 -CYREG_SFLASH_MACRO_0_FREE_SFLASH862 EQU 0x0ffff75e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH863 -CYREG_SFLASH_MACRO_0_FREE_SFLASH863 EQU 0x0ffff75f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH864 -CYREG_SFLASH_MACRO_0_FREE_SFLASH864 EQU 0x0ffff760 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH865 -CYREG_SFLASH_MACRO_0_FREE_SFLASH865 EQU 0x0ffff761 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH866 -CYREG_SFLASH_MACRO_0_FREE_SFLASH866 EQU 0x0ffff762 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH867 -CYREG_SFLASH_MACRO_0_FREE_SFLASH867 EQU 0x0ffff763 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH868 -CYREG_SFLASH_MACRO_0_FREE_SFLASH868 EQU 0x0ffff764 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH869 -CYREG_SFLASH_MACRO_0_FREE_SFLASH869 EQU 0x0ffff765 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH870 -CYREG_SFLASH_MACRO_0_FREE_SFLASH870 EQU 0x0ffff766 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH871 -CYREG_SFLASH_MACRO_0_FREE_SFLASH871 EQU 0x0ffff767 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH872 -CYREG_SFLASH_MACRO_0_FREE_SFLASH872 EQU 0x0ffff768 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH873 -CYREG_SFLASH_MACRO_0_FREE_SFLASH873 EQU 0x0ffff769 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH874 -CYREG_SFLASH_MACRO_0_FREE_SFLASH874 EQU 0x0ffff76a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH875 -CYREG_SFLASH_MACRO_0_FREE_SFLASH875 EQU 0x0ffff76b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH876 -CYREG_SFLASH_MACRO_0_FREE_SFLASH876 EQU 0x0ffff76c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH877 -CYREG_SFLASH_MACRO_0_FREE_SFLASH877 EQU 0x0ffff76d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH878 -CYREG_SFLASH_MACRO_0_FREE_SFLASH878 EQU 0x0ffff76e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH879 -CYREG_SFLASH_MACRO_0_FREE_SFLASH879 EQU 0x0ffff76f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH880 -CYREG_SFLASH_MACRO_0_FREE_SFLASH880 EQU 0x0ffff770 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH881 -CYREG_SFLASH_MACRO_0_FREE_SFLASH881 EQU 0x0ffff771 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH882 -CYREG_SFLASH_MACRO_0_FREE_SFLASH882 EQU 0x0ffff772 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH883 -CYREG_SFLASH_MACRO_0_FREE_SFLASH883 EQU 0x0ffff773 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH884 -CYREG_SFLASH_MACRO_0_FREE_SFLASH884 EQU 0x0ffff774 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH885 -CYREG_SFLASH_MACRO_0_FREE_SFLASH885 EQU 0x0ffff775 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH886 -CYREG_SFLASH_MACRO_0_FREE_SFLASH886 EQU 0x0ffff776 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH887 -CYREG_SFLASH_MACRO_0_FREE_SFLASH887 EQU 0x0ffff777 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH888 -CYREG_SFLASH_MACRO_0_FREE_SFLASH888 EQU 0x0ffff778 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH889 -CYREG_SFLASH_MACRO_0_FREE_SFLASH889 EQU 0x0ffff779 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH890 -CYREG_SFLASH_MACRO_0_FREE_SFLASH890 EQU 0x0ffff77a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH891 -CYREG_SFLASH_MACRO_0_FREE_SFLASH891 EQU 0x0ffff77b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH892 -CYREG_SFLASH_MACRO_0_FREE_SFLASH892 EQU 0x0ffff77c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH893 -CYREG_SFLASH_MACRO_0_FREE_SFLASH893 EQU 0x0ffff77d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH894 -CYREG_SFLASH_MACRO_0_FREE_SFLASH894 EQU 0x0ffff77e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH895 -CYREG_SFLASH_MACRO_0_FREE_SFLASH895 EQU 0x0ffff77f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH896 -CYREG_SFLASH_MACRO_0_FREE_SFLASH896 EQU 0x0ffff780 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH897 -CYREG_SFLASH_MACRO_0_FREE_SFLASH897 EQU 0x0ffff781 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH898 -CYREG_SFLASH_MACRO_0_FREE_SFLASH898 EQU 0x0ffff782 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH899 -CYREG_SFLASH_MACRO_0_FREE_SFLASH899 EQU 0x0ffff783 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH900 -CYREG_SFLASH_MACRO_0_FREE_SFLASH900 EQU 0x0ffff784 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH901 -CYREG_SFLASH_MACRO_0_FREE_SFLASH901 EQU 0x0ffff785 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH902 -CYREG_SFLASH_MACRO_0_FREE_SFLASH902 EQU 0x0ffff786 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH903 -CYREG_SFLASH_MACRO_0_FREE_SFLASH903 EQU 0x0ffff787 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH904 -CYREG_SFLASH_MACRO_0_FREE_SFLASH904 EQU 0x0ffff788 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH905 -CYREG_SFLASH_MACRO_0_FREE_SFLASH905 EQU 0x0ffff789 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH906 -CYREG_SFLASH_MACRO_0_FREE_SFLASH906 EQU 0x0ffff78a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH907 -CYREG_SFLASH_MACRO_0_FREE_SFLASH907 EQU 0x0ffff78b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH908 -CYREG_SFLASH_MACRO_0_FREE_SFLASH908 EQU 0x0ffff78c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH909 -CYREG_SFLASH_MACRO_0_FREE_SFLASH909 EQU 0x0ffff78d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH910 -CYREG_SFLASH_MACRO_0_FREE_SFLASH910 EQU 0x0ffff78e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH911 -CYREG_SFLASH_MACRO_0_FREE_SFLASH911 EQU 0x0ffff78f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH912 -CYREG_SFLASH_MACRO_0_FREE_SFLASH912 EQU 0x0ffff790 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH913 -CYREG_SFLASH_MACRO_0_FREE_SFLASH913 EQU 0x0ffff791 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH914 -CYREG_SFLASH_MACRO_0_FREE_SFLASH914 EQU 0x0ffff792 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH915 -CYREG_SFLASH_MACRO_0_FREE_SFLASH915 EQU 0x0ffff793 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH916 -CYREG_SFLASH_MACRO_0_FREE_SFLASH916 EQU 0x0ffff794 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH917 -CYREG_SFLASH_MACRO_0_FREE_SFLASH917 EQU 0x0ffff795 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH918 -CYREG_SFLASH_MACRO_0_FREE_SFLASH918 EQU 0x0ffff796 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH919 -CYREG_SFLASH_MACRO_0_FREE_SFLASH919 EQU 0x0ffff797 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH920 -CYREG_SFLASH_MACRO_0_FREE_SFLASH920 EQU 0x0ffff798 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH921 -CYREG_SFLASH_MACRO_0_FREE_SFLASH921 EQU 0x0ffff799 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH922 -CYREG_SFLASH_MACRO_0_FREE_SFLASH922 EQU 0x0ffff79a - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH923 -CYREG_SFLASH_MACRO_0_FREE_SFLASH923 EQU 0x0ffff79b - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH924 -CYREG_SFLASH_MACRO_0_FREE_SFLASH924 EQU 0x0ffff79c - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH925 -CYREG_SFLASH_MACRO_0_FREE_SFLASH925 EQU 0x0ffff79d - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH926 -CYREG_SFLASH_MACRO_0_FREE_SFLASH926 EQU 0x0ffff79e - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH927 -CYREG_SFLASH_MACRO_0_FREE_SFLASH927 EQU 0x0ffff79f - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH928 -CYREG_SFLASH_MACRO_0_FREE_SFLASH928 EQU 0x0ffff7a0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH929 -CYREG_SFLASH_MACRO_0_FREE_SFLASH929 EQU 0x0ffff7a1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH930 -CYREG_SFLASH_MACRO_0_FREE_SFLASH930 EQU 0x0ffff7a2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH931 -CYREG_SFLASH_MACRO_0_FREE_SFLASH931 EQU 0x0ffff7a3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH932 -CYREG_SFLASH_MACRO_0_FREE_SFLASH932 EQU 0x0ffff7a4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH933 -CYREG_SFLASH_MACRO_0_FREE_SFLASH933 EQU 0x0ffff7a5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH934 -CYREG_SFLASH_MACRO_0_FREE_SFLASH934 EQU 0x0ffff7a6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH935 -CYREG_SFLASH_MACRO_0_FREE_SFLASH935 EQU 0x0ffff7a7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH936 -CYREG_SFLASH_MACRO_0_FREE_SFLASH936 EQU 0x0ffff7a8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH937 -CYREG_SFLASH_MACRO_0_FREE_SFLASH937 EQU 0x0ffff7a9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH938 -CYREG_SFLASH_MACRO_0_FREE_SFLASH938 EQU 0x0ffff7aa - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH939 -CYREG_SFLASH_MACRO_0_FREE_SFLASH939 EQU 0x0ffff7ab - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH940 -CYREG_SFLASH_MACRO_0_FREE_SFLASH940 EQU 0x0ffff7ac - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH941 -CYREG_SFLASH_MACRO_0_FREE_SFLASH941 EQU 0x0ffff7ad - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH942 -CYREG_SFLASH_MACRO_0_FREE_SFLASH942 EQU 0x0ffff7ae - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH943 -CYREG_SFLASH_MACRO_0_FREE_SFLASH943 EQU 0x0ffff7af - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH944 -CYREG_SFLASH_MACRO_0_FREE_SFLASH944 EQU 0x0ffff7b0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH945 -CYREG_SFLASH_MACRO_0_FREE_SFLASH945 EQU 0x0ffff7b1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH946 -CYREG_SFLASH_MACRO_0_FREE_SFLASH946 EQU 0x0ffff7b2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH947 -CYREG_SFLASH_MACRO_0_FREE_SFLASH947 EQU 0x0ffff7b3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH948 -CYREG_SFLASH_MACRO_0_FREE_SFLASH948 EQU 0x0ffff7b4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH949 -CYREG_SFLASH_MACRO_0_FREE_SFLASH949 EQU 0x0ffff7b5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH950 -CYREG_SFLASH_MACRO_0_FREE_SFLASH950 EQU 0x0ffff7b6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH951 -CYREG_SFLASH_MACRO_0_FREE_SFLASH951 EQU 0x0ffff7b7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH952 -CYREG_SFLASH_MACRO_0_FREE_SFLASH952 EQU 0x0ffff7b8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH953 -CYREG_SFLASH_MACRO_0_FREE_SFLASH953 EQU 0x0ffff7b9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH954 -CYREG_SFLASH_MACRO_0_FREE_SFLASH954 EQU 0x0ffff7ba - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH955 -CYREG_SFLASH_MACRO_0_FREE_SFLASH955 EQU 0x0ffff7bb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH956 -CYREG_SFLASH_MACRO_0_FREE_SFLASH956 EQU 0x0ffff7bc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH957 -CYREG_SFLASH_MACRO_0_FREE_SFLASH957 EQU 0x0ffff7bd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH958 -CYREG_SFLASH_MACRO_0_FREE_SFLASH958 EQU 0x0ffff7be - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH959 -CYREG_SFLASH_MACRO_0_FREE_SFLASH959 EQU 0x0ffff7bf - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH960 -CYREG_SFLASH_MACRO_0_FREE_SFLASH960 EQU 0x0ffff7c0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH961 -CYREG_SFLASH_MACRO_0_FREE_SFLASH961 EQU 0x0ffff7c1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH962 -CYREG_SFLASH_MACRO_0_FREE_SFLASH962 EQU 0x0ffff7c2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH963 -CYREG_SFLASH_MACRO_0_FREE_SFLASH963 EQU 0x0ffff7c3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH964 -CYREG_SFLASH_MACRO_0_FREE_SFLASH964 EQU 0x0ffff7c4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH965 -CYREG_SFLASH_MACRO_0_FREE_SFLASH965 EQU 0x0ffff7c5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH966 -CYREG_SFLASH_MACRO_0_FREE_SFLASH966 EQU 0x0ffff7c6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH967 -CYREG_SFLASH_MACRO_0_FREE_SFLASH967 EQU 0x0ffff7c7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH968 -CYREG_SFLASH_MACRO_0_FREE_SFLASH968 EQU 0x0ffff7c8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH969 -CYREG_SFLASH_MACRO_0_FREE_SFLASH969 EQU 0x0ffff7c9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH970 -CYREG_SFLASH_MACRO_0_FREE_SFLASH970 EQU 0x0ffff7ca - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH971 -CYREG_SFLASH_MACRO_0_FREE_SFLASH971 EQU 0x0ffff7cb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH972 -CYREG_SFLASH_MACRO_0_FREE_SFLASH972 EQU 0x0ffff7cc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH973 -CYREG_SFLASH_MACRO_0_FREE_SFLASH973 EQU 0x0ffff7cd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH974 -CYREG_SFLASH_MACRO_0_FREE_SFLASH974 EQU 0x0ffff7ce - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH975 -CYREG_SFLASH_MACRO_0_FREE_SFLASH975 EQU 0x0ffff7cf - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH976 -CYREG_SFLASH_MACRO_0_FREE_SFLASH976 EQU 0x0ffff7d0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH977 -CYREG_SFLASH_MACRO_0_FREE_SFLASH977 EQU 0x0ffff7d1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH978 -CYREG_SFLASH_MACRO_0_FREE_SFLASH978 EQU 0x0ffff7d2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH979 -CYREG_SFLASH_MACRO_0_FREE_SFLASH979 EQU 0x0ffff7d3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH980 -CYREG_SFLASH_MACRO_0_FREE_SFLASH980 EQU 0x0ffff7d4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH981 -CYREG_SFLASH_MACRO_0_FREE_SFLASH981 EQU 0x0ffff7d5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH982 -CYREG_SFLASH_MACRO_0_FREE_SFLASH982 EQU 0x0ffff7d6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH983 -CYREG_SFLASH_MACRO_0_FREE_SFLASH983 EQU 0x0ffff7d7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH984 -CYREG_SFLASH_MACRO_0_FREE_SFLASH984 EQU 0x0ffff7d8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH985 -CYREG_SFLASH_MACRO_0_FREE_SFLASH985 EQU 0x0ffff7d9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH986 -CYREG_SFLASH_MACRO_0_FREE_SFLASH986 EQU 0x0ffff7da - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH987 -CYREG_SFLASH_MACRO_0_FREE_SFLASH987 EQU 0x0ffff7db - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH988 -CYREG_SFLASH_MACRO_0_FREE_SFLASH988 EQU 0x0ffff7dc - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH989 -CYREG_SFLASH_MACRO_0_FREE_SFLASH989 EQU 0x0ffff7dd - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH990 -CYREG_SFLASH_MACRO_0_FREE_SFLASH990 EQU 0x0ffff7de - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH991 -CYREG_SFLASH_MACRO_0_FREE_SFLASH991 EQU 0x0ffff7df - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH992 -CYREG_SFLASH_MACRO_0_FREE_SFLASH992 EQU 0x0ffff7e0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH993 -CYREG_SFLASH_MACRO_0_FREE_SFLASH993 EQU 0x0ffff7e1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH994 -CYREG_SFLASH_MACRO_0_FREE_SFLASH994 EQU 0x0ffff7e2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH995 -CYREG_SFLASH_MACRO_0_FREE_SFLASH995 EQU 0x0ffff7e3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH996 -CYREG_SFLASH_MACRO_0_FREE_SFLASH996 EQU 0x0ffff7e4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH997 -CYREG_SFLASH_MACRO_0_FREE_SFLASH997 EQU 0x0ffff7e5 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH998 -CYREG_SFLASH_MACRO_0_FREE_SFLASH998 EQU 0x0ffff7e6 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH999 -CYREG_SFLASH_MACRO_0_FREE_SFLASH999 EQU 0x0ffff7e7 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 EQU 0x0ffff7e8 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 EQU 0x0ffff7e9 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 EQU 0x0ffff7ea - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 EQU 0x0ffff7eb - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 EQU 0x0ffff7ec - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 EQU 0x0ffff7ed - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 EQU 0x0ffff7ee - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 EQU 0x0ffff7ef - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 EQU 0x0ffff7f0 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 EQU 0x0ffff7f1 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 EQU 0x0ffff7f2 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 EQU 0x0ffff7f3 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 EQU 0x0ffff7f4 - ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 EQU 0x0ffff7f5 +CYREG_SFLASH_MACRO_0_FREE_SFLASH501 EQU 0x0ffff3f5 ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 EQU 0x0ffff7f6 + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH502 +CYREG_SFLASH_MACRO_0_FREE_SFLASH502 EQU 0x0ffff3f6 ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 EQU 0x0ffff7f7 + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH503 +CYREG_SFLASH_MACRO_0_FREE_SFLASH503 EQU 0x0ffff3f7 ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 EQU 0x0ffff7f8 + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH504 +CYREG_SFLASH_MACRO_0_FREE_SFLASH504 EQU 0x0ffff3f8 ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 EQU 0x0ffff7f9 + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH505 +CYREG_SFLASH_MACRO_0_FREE_SFLASH505 EQU 0x0ffff3f9 ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 EQU 0x0ffff7fa + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH506 +CYREG_SFLASH_MACRO_0_FREE_SFLASH506 EQU 0x0ffff3fa ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 EQU 0x0ffff7fb + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH507 +CYREG_SFLASH_MACRO_0_FREE_SFLASH507 EQU 0x0ffff3fb ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 EQU 0x0ffff7fc + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH508 +CYREG_SFLASH_MACRO_0_FREE_SFLASH508 EQU 0x0ffff3fc ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 EQU 0x0ffff7fd + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH509 +CYREG_SFLASH_MACRO_0_FREE_SFLASH509 EQU 0x0ffff3fd ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 EQU 0x0ffff7fe + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH510 +CYREG_SFLASH_MACRO_0_FREE_SFLASH510 EQU 0x0ffff3fe ENDIF - IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 -CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 EQU 0x0ffff7ff + IF :LNOT::DEF:CYREG_SFLASH_MACRO_0_FREE_SFLASH511 +CYREG_SFLASH_MACRO_0_FREE_SFLASH511 EQU 0x0ffff3ff ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW0 -CYREG_SFLASH_ALT_PROT_ROW0 EQU 0x0ffff800 +CYREG_SFLASH_ALT_PROT_ROW0 EQU 0x0ffff400 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW1 -CYREG_SFLASH_ALT_PROT_ROW1 EQU 0x0ffff801 +CYREG_SFLASH_ALT_PROT_ROW1 EQU 0x0ffff401 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW2 -CYREG_SFLASH_ALT_PROT_ROW2 EQU 0x0ffff802 +CYREG_SFLASH_ALT_PROT_ROW2 EQU 0x0ffff402 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW3 -CYREG_SFLASH_ALT_PROT_ROW3 EQU 0x0ffff803 +CYREG_SFLASH_ALT_PROT_ROW3 EQU 0x0ffff403 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW4 -CYREG_SFLASH_ALT_PROT_ROW4 EQU 0x0ffff804 +CYREG_SFLASH_ALT_PROT_ROW4 EQU 0x0ffff404 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW5 -CYREG_SFLASH_ALT_PROT_ROW5 EQU 0x0ffff805 +CYREG_SFLASH_ALT_PROT_ROW5 EQU 0x0ffff405 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW6 -CYREG_SFLASH_ALT_PROT_ROW6 EQU 0x0ffff806 +CYREG_SFLASH_ALT_PROT_ROW6 EQU 0x0ffff406 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW7 -CYREG_SFLASH_ALT_PROT_ROW7 EQU 0x0ffff807 +CYREG_SFLASH_ALT_PROT_ROW7 EQU 0x0ffff407 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW8 -CYREG_SFLASH_ALT_PROT_ROW8 EQU 0x0ffff808 +CYREG_SFLASH_ALT_PROT_ROW8 EQU 0x0ffff408 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW9 -CYREG_SFLASH_ALT_PROT_ROW9 EQU 0x0ffff809 +CYREG_SFLASH_ALT_PROT_ROW9 EQU 0x0ffff409 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW10 -CYREG_SFLASH_ALT_PROT_ROW10 EQU 0x0ffff80a +CYREG_SFLASH_ALT_PROT_ROW10 EQU 0x0ffff40a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW11 -CYREG_SFLASH_ALT_PROT_ROW11 EQU 0x0ffff80b +CYREG_SFLASH_ALT_PROT_ROW11 EQU 0x0ffff40b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW12 -CYREG_SFLASH_ALT_PROT_ROW12 EQU 0x0ffff80c +CYREG_SFLASH_ALT_PROT_ROW12 EQU 0x0ffff40c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW13 -CYREG_SFLASH_ALT_PROT_ROW13 EQU 0x0ffff80d +CYREG_SFLASH_ALT_PROT_ROW13 EQU 0x0ffff40d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW14 -CYREG_SFLASH_ALT_PROT_ROW14 EQU 0x0ffff80e +CYREG_SFLASH_ALT_PROT_ROW14 EQU 0x0ffff40e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW15 -CYREG_SFLASH_ALT_PROT_ROW15 EQU 0x0ffff80f +CYREG_SFLASH_ALT_PROT_ROW15 EQU 0x0ffff40f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW16 -CYREG_SFLASH_ALT_PROT_ROW16 EQU 0x0ffff810 +CYREG_SFLASH_ALT_PROT_ROW16 EQU 0x0ffff410 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW17 -CYREG_SFLASH_ALT_PROT_ROW17 EQU 0x0ffff811 +CYREG_SFLASH_ALT_PROT_ROW17 EQU 0x0ffff411 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW18 -CYREG_SFLASH_ALT_PROT_ROW18 EQU 0x0ffff812 +CYREG_SFLASH_ALT_PROT_ROW18 EQU 0x0ffff412 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW19 -CYREG_SFLASH_ALT_PROT_ROW19 EQU 0x0ffff813 +CYREG_SFLASH_ALT_PROT_ROW19 EQU 0x0ffff413 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW20 -CYREG_SFLASH_ALT_PROT_ROW20 EQU 0x0ffff814 +CYREG_SFLASH_ALT_PROT_ROW20 EQU 0x0ffff414 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW21 -CYREG_SFLASH_ALT_PROT_ROW21 EQU 0x0ffff815 +CYREG_SFLASH_ALT_PROT_ROW21 EQU 0x0ffff415 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW22 -CYREG_SFLASH_ALT_PROT_ROW22 EQU 0x0ffff816 +CYREG_SFLASH_ALT_PROT_ROW22 EQU 0x0ffff416 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW23 -CYREG_SFLASH_ALT_PROT_ROW23 EQU 0x0ffff817 +CYREG_SFLASH_ALT_PROT_ROW23 EQU 0x0ffff417 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW24 -CYREG_SFLASH_ALT_PROT_ROW24 EQU 0x0ffff818 +CYREG_SFLASH_ALT_PROT_ROW24 EQU 0x0ffff418 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW25 -CYREG_SFLASH_ALT_PROT_ROW25 EQU 0x0ffff819 +CYREG_SFLASH_ALT_PROT_ROW25 EQU 0x0ffff419 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW26 -CYREG_SFLASH_ALT_PROT_ROW26 EQU 0x0ffff81a +CYREG_SFLASH_ALT_PROT_ROW26 EQU 0x0ffff41a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW27 -CYREG_SFLASH_ALT_PROT_ROW27 EQU 0x0ffff81b +CYREG_SFLASH_ALT_PROT_ROW27 EQU 0x0ffff41b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW28 -CYREG_SFLASH_ALT_PROT_ROW28 EQU 0x0ffff81c +CYREG_SFLASH_ALT_PROT_ROW28 EQU 0x0ffff41c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW29 -CYREG_SFLASH_ALT_PROT_ROW29 EQU 0x0ffff81d +CYREG_SFLASH_ALT_PROT_ROW29 EQU 0x0ffff41d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW30 -CYREG_SFLASH_ALT_PROT_ROW30 EQU 0x0ffff81e +CYREG_SFLASH_ALT_PROT_ROW30 EQU 0x0ffff41e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW31 -CYREG_SFLASH_ALT_PROT_ROW31 EQU 0x0ffff81f +CYREG_SFLASH_ALT_PROT_ROW31 EQU 0x0ffff41f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW32 -CYREG_SFLASH_ALT_PROT_ROW32 EQU 0x0ffff820 +CYREG_SFLASH_ALT_PROT_ROW32 EQU 0x0ffff420 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW33 -CYREG_SFLASH_ALT_PROT_ROW33 EQU 0x0ffff821 +CYREG_SFLASH_ALT_PROT_ROW33 EQU 0x0ffff421 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW34 -CYREG_SFLASH_ALT_PROT_ROW34 EQU 0x0ffff822 +CYREG_SFLASH_ALT_PROT_ROW34 EQU 0x0ffff422 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW35 -CYREG_SFLASH_ALT_PROT_ROW35 EQU 0x0ffff823 +CYREG_SFLASH_ALT_PROT_ROW35 EQU 0x0ffff423 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW36 -CYREG_SFLASH_ALT_PROT_ROW36 EQU 0x0ffff824 +CYREG_SFLASH_ALT_PROT_ROW36 EQU 0x0ffff424 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW37 -CYREG_SFLASH_ALT_PROT_ROW37 EQU 0x0ffff825 +CYREG_SFLASH_ALT_PROT_ROW37 EQU 0x0ffff425 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW38 -CYREG_SFLASH_ALT_PROT_ROW38 EQU 0x0ffff826 +CYREG_SFLASH_ALT_PROT_ROW38 EQU 0x0ffff426 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW39 -CYREG_SFLASH_ALT_PROT_ROW39 EQU 0x0ffff827 +CYREG_SFLASH_ALT_PROT_ROW39 EQU 0x0ffff427 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW40 -CYREG_SFLASH_ALT_PROT_ROW40 EQU 0x0ffff828 +CYREG_SFLASH_ALT_PROT_ROW40 EQU 0x0ffff428 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW41 -CYREG_SFLASH_ALT_PROT_ROW41 EQU 0x0ffff829 +CYREG_SFLASH_ALT_PROT_ROW41 EQU 0x0ffff429 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW42 -CYREG_SFLASH_ALT_PROT_ROW42 EQU 0x0ffff82a +CYREG_SFLASH_ALT_PROT_ROW42 EQU 0x0ffff42a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW43 -CYREG_SFLASH_ALT_PROT_ROW43 EQU 0x0ffff82b +CYREG_SFLASH_ALT_PROT_ROW43 EQU 0x0ffff42b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW44 -CYREG_SFLASH_ALT_PROT_ROW44 EQU 0x0ffff82c +CYREG_SFLASH_ALT_PROT_ROW44 EQU 0x0ffff42c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW45 -CYREG_SFLASH_ALT_PROT_ROW45 EQU 0x0ffff82d +CYREG_SFLASH_ALT_PROT_ROW45 EQU 0x0ffff42d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW46 -CYREG_SFLASH_ALT_PROT_ROW46 EQU 0x0ffff82e +CYREG_SFLASH_ALT_PROT_ROW46 EQU 0x0ffff42e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW47 -CYREG_SFLASH_ALT_PROT_ROW47 EQU 0x0ffff82f +CYREG_SFLASH_ALT_PROT_ROW47 EQU 0x0ffff42f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW48 -CYREG_SFLASH_ALT_PROT_ROW48 EQU 0x0ffff830 +CYREG_SFLASH_ALT_PROT_ROW48 EQU 0x0ffff430 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW49 -CYREG_SFLASH_ALT_PROT_ROW49 EQU 0x0ffff831 +CYREG_SFLASH_ALT_PROT_ROW49 EQU 0x0ffff431 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW50 -CYREG_SFLASH_ALT_PROT_ROW50 EQU 0x0ffff832 +CYREG_SFLASH_ALT_PROT_ROW50 EQU 0x0ffff432 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW51 -CYREG_SFLASH_ALT_PROT_ROW51 EQU 0x0ffff833 +CYREG_SFLASH_ALT_PROT_ROW51 EQU 0x0ffff433 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW52 -CYREG_SFLASH_ALT_PROT_ROW52 EQU 0x0ffff834 +CYREG_SFLASH_ALT_PROT_ROW52 EQU 0x0ffff434 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW53 -CYREG_SFLASH_ALT_PROT_ROW53 EQU 0x0ffff835 +CYREG_SFLASH_ALT_PROT_ROW53 EQU 0x0ffff435 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW54 -CYREG_SFLASH_ALT_PROT_ROW54 EQU 0x0ffff836 +CYREG_SFLASH_ALT_PROT_ROW54 EQU 0x0ffff436 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW55 -CYREG_SFLASH_ALT_PROT_ROW55 EQU 0x0ffff837 +CYREG_SFLASH_ALT_PROT_ROW55 EQU 0x0ffff437 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW56 -CYREG_SFLASH_ALT_PROT_ROW56 EQU 0x0ffff838 +CYREG_SFLASH_ALT_PROT_ROW56 EQU 0x0ffff438 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW57 -CYREG_SFLASH_ALT_PROT_ROW57 EQU 0x0ffff839 +CYREG_SFLASH_ALT_PROT_ROW57 EQU 0x0ffff439 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW58 -CYREG_SFLASH_ALT_PROT_ROW58 EQU 0x0ffff83a +CYREG_SFLASH_ALT_PROT_ROW58 EQU 0x0ffff43a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW59 -CYREG_SFLASH_ALT_PROT_ROW59 EQU 0x0ffff83b +CYREG_SFLASH_ALT_PROT_ROW59 EQU 0x0ffff43b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW60 -CYREG_SFLASH_ALT_PROT_ROW60 EQU 0x0ffff83c +CYREG_SFLASH_ALT_PROT_ROW60 EQU 0x0ffff43c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW61 -CYREG_SFLASH_ALT_PROT_ROW61 EQU 0x0ffff83d +CYREG_SFLASH_ALT_PROT_ROW61 EQU 0x0ffff43d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW62 -CYREG_SFLASH_ALT_PROT_ROW62 EQU 0x0ffff83e +CYREG_SFLASH_ALT_PROT_ROW62 EQU 0x0ffff43e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW63 -CYREG_SFLASH_ALT_PROT_ROW63 EQU 0x0ffff83f +CYREG_SFLASH_ALT_PROT_ROW63 EQU 0x0ffff43f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW64 -CYREG_SFLASH_ALT_PROT_ROW64 EQU 0x0ffff840 +CYREG_SFLASH_ALT_PROT_ROW64 EQU 0x0ffff440 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW65 -CYREG_SFLASH_ALT_PROT_ROW65 EQU 0x0ffff841 +CYREG_SFLASH_ALT_PROT_ROW65 EQU 0x0ffff441 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW66 -CYREG_SFLASH_ALT_PROT_ROW66 EQU 0x0ffff842 +CYREG_SFLASH_ALT_PROT_ROW66 EQU 0x0ffff442 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW67 -CYREG_SFLASH_ALT_PROT_ROW67 EQU 0x0ffff843 +CYREG_SFLASH_ALT_PROT_ROW67 EQU 0x0ffff443 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW68 -CYREG_SFLASH_ALT_PROT_ROW68 EQU 0x0ffff844 +CYREG_SFLASH_ALT_PROT_ROW68 EQU 0x0ffff444 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW69 -CYREG_SFLASH_ALT_PROT_ROW69 EQU 0x0ffff845 +CYREG_SFLASH_ALT_PROT_ROW69 EQU 0x0ffff445 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW70 -CYREG_SFLASH_ALT_PROT_ROW70 EQU 0x0ffff846 +CYREG_SFLASH_ALT_PROT_ROW70 EQU 0x0ffff446 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW71 -CYREG_SFLASH_ALT_PROT_ROW71 EQU 0x0ffff847 +CYREG_SFLASH_ALT_PROT_ROW71 EQU 0x0ffff447 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW72 -CYREG_SFLASH_ALT_PROT_ROW72 EQU 0x0ffff848 +CYREG_SFLASH_ALT_PROT_ROW72 EQU 0x0ffff448 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW73 -CYREG_SFLASH_ALT_PROT_ROW73 EQU 0x0ffff849 +CYREG_SFLASH_ALT_PROT_ROW73 EQU 0x0ffff449 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW74 -CYREG_SFLASH_ALT_PROT_ROW74 EQU 0x0ffff84a +CYREG_SFLASH_ALT_PROT_ROW74 EQU 0x0ffff44a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW75 -CYREG_SFLASH_ALT_PROT_ROW75 EQU 0x0ffff84b +CYREG_SFLASH_ALT_PROT_ROW75 EQU 0x0ffff44b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW76 -CYREG_SFLASH_ALT_PROT_ROW76 EQU 0x0ffff84c +CYREG_SFLASH_ALT_PROT_ROW76 EQU 0x0ffff44c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW77 -CYREG_SFLASH_ALT_PROT_ROW77 EQU 0x0ffff84d +CYREG_SFLASH_ALT_PROT_ROW77 EQU 0x0ffff44d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW78 -CYREG_SFLASH_ALT_PROT_ROW78 EQU 0x0ffff84e +CYREG_SFLASH_ALT_PROT_ROW78 EQU 0x0ffff44e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW79 -CYREG_SFLASH_ALT_PROT_ROW79 EQU 0x0ffff84f +CYREG_SFLASH_ALT_PROT_ROW79 EQU 0x0ffff44f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW80 -CYREG_SFLASH_ALT_PROT_ROW80 EQU 0x0ffff850 +CYREG_SFLASH_ALT_PROT_ROW80 EQU 0x0ffff450 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW81 -CYREG_SFLASH_ALT_PROT_ROW81 EQU 0x0ffff851 +CYREG_SFLASH_ALT_PROT_ROW81 EQU 0x0ffff451 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW82 -CYREG_SFLASH_ALT_PROT_ROW82 EQU 0x0ffff852 +CYREG_SFLASH_ALT_PROT_ROW82 EQU 0x0ffff452 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW83 -CYREG_SFLASH_ALT_PROT_ROW83 EQU 0x0ffff853 +CYREG_SFLASH_ALT_PROT_ROW83 EQU 0x0ffff453 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW84 -CYREG_SFLASH_ALT_PROT_ROW84 EQU 0x0ffff854 +CYREG_SFLASH_ALT_PROT_ROW84 EQU 0x0ffff454 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW85 -CYREG_SFLASH_ALT_PROT_ROW85 EQU 0x0ffff855 +CYREG_SFLASH_ALT_PROT_ROW85 EQU 0x0ffff455 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW86 -CYREG_SFLASH_ALT_PROT_ROW86 EQU 0x0ffff856 +CYREG_SFLASH_ALT_PROT_ROW86 EQU 0x0ffff456 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW87 -CYREG_SFLASH_ALT_PROT_ROW87 EQU 0x0ffff857 +CYREG_SFLASH_ALT_PROT_ROW87 EQU 0x0ffff457 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW88 -CYREG_SFLASH_ALT_PROT_ROW88 EQU 0x0ffff858 +CYREG_SFLASH_ALT_PROT_ROW88 EQU 0x0ffff458 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW89 -CYREG_SFLASH_ALT_PROT_ROW89 EQU 0x0ffff859 +CYREG_SFLASH_ALT_PROT_ROW89 EQU 0x0ffff459 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW90 -CYREG_SFLASH_ALT_PROT_ROW90 EQU 0x0ffff85a +CYREG_SFLASH_ALT_PROT_ROW90 EQU 0x0ffff45a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW91 -CYREG_SFLASH_ALT_PROT_ROW91 EQU 0x0ffff85b +CYREG_SFLASH_ALT_PROT_ROW91 EQU 0x0ffff45b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW92 -CYREG_SFLASH_ALT_PROT_ROW92 EQU 0x0ffff85c +CYREG_SFLASH_ALT_PROT_ROW92 EQU 0x0ffff45c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW93 -CYREG_SFLASH_ALT_PROT_ROW93 EQU 0x0ffff85d +CYREG_SFLASH_ALT_PROT_ROW93 EQU 0x0ffff45d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW94 -CYREG_SFLASH_ALT_PROT_ROW94 EQU 0x0ffff85e +CYREG_SFLASH_ALT_PROT_ROW94 EQU 0x0ffff45e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW95 -CYREG_SFLASH_ALT_PROT_ROW95 EQU 0x0ffff85f +CYREG_SFLASH_ALT_PROT_ROW95 EQU 0x0ffff45f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW96 -CYREG_SFLASH_ALT_PROT_ROW96 EQU 0x0ffff860 +CYREG_SFLASH_ALT_PROT_ROW96 EQU 0x0ffff460 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW97 -CYREG_SFLASH_ALT_PROT_ROW97 EQU 0x0ffff861 +CYREG_SFLASH_ALT_PROT_ROW97 EQU 0x0ffff461 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW98 -CYREG_SFLASH_ALT_PROT_ROW98 EQU 0x0ffff862 +CYREG_SFLASH_ALT_PROT_ROW98 EQU 0x0ffff462 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW99 -CYREG_SFLASH_ALT_PROT_ROW99 EQU 0x0ffff863 +CYREG_SFLASH_ALT_PROT_ROW99 EQU 0x0ffff463 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW100 -CYREG_SFLASH_ALT_PROT_ROW100 EQU 0x0ffff864 +CYREG_SFLASH_ALT_PROT_ROW100 EQU 0x0ffff464 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW101 -CYREG_SFLASH_ALT_PROT_ROW101 EQU 0x0ffff865 +CYREG_SFLASH_ALT_PROT_ROW101 EQU 0x0ffff465 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW102 -CYREG_SFLASH_ALT_PROT_ROW102 EQU 0x0ffff866 +CYREG_SFLASH_ALT_PROT_ROW102 EQU 0x0ffff466 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW103 -CYREG_SFLASH_ALT_PROT_ROW103 EQU 0x0ffff867 +CYREG_SFLASH_ALT_PROT_ROW103 EQU 0x0ffff467 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW104 -CYREG_SFLASH_ALT_PROT_ROW104 EQU 0x0ffff868 +CYREG_SFLASH_ALT_PROT_ROW104 EQU 0x0ffff468 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW105 -CYREG_SFLASH_ALT_PROT_ROW105 EQU 0x0ffff869 +CYREG_SFLASH_ALT_PROT_ROW105 EQU 0x0ffff469 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW106 -CYREG_SFLASH_ALT_PROT_ROW106 EQU 0x0ffff86a +CYREG_SFLASH_ALT_PROT_ROW106 EQU 0x0ffff46a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW107 -CYREG_SFLASH_ALT_PROT_ROW107 EQU 0x0ffff86b +CYREG_SFLASH_ALT_PROT_ROW107 EQU 0x0ffff46b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW108 -CYREG_SFLASH_ALT_PROT_ROW108 EQU 0x0ffff86c +CYREG_SFLASH_ALT_PROT_ROW108 EQU 0x0ffff46c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW109 -CYREG_SFLASH_ALT_PROT_ROW109 EQU 0x0ffff86d +CYREG_SFLASH_ALT_PROT_ROW109 EQU 0x0ffff46d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW110 -CYREG_SFLASH_ALT_PROT_ROW110 EQU 0x0ffff86e +CYREG_SFLASH_ALT_PROT_ROW110 EQU 0x0ffff46e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW111 -CYREG_SFLASH_ALT_PROT_ROW111 EQU 0x0ffff86f +CYREG_SFLASH_ALT_PROT_ROW111 EQU 0x0ffff46f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW112 -CYREG_SFLASH_ALT_PROT_ROW112 EQU 0x0ffff870 +CYREG_SFLASH_ALT_PROT_ROW112 EQU 0x0ffff470 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW113 -CYREG_SFLASH_ALT_PROT_ROW113 EQU 0x0ffff871 +CYREG_SFLASH_ALT_PROT_ROW113 EQU 0x0ffff471 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW114 -CYREG_SFLASH_ALT_PROT_ROW114 EQU 0x0ffff872 +CYREG_SFLASH_ALT_PROT_ROW114 EQU 0x0ffff472 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW115 -CYREG_SFLASH_ALT_PROT_ROW115 EQU 0x0ffff873 +CYREG_SFLASH_ALT_PROT_ROW115 EQU 0x0ffff473 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW116 -CYREG_SFLASH_ALT_PROT_ROW116 EQU 0x0ffff874 +CYREG_SFLASH_ALT_PROT_ROW116 EQU 0x0ffff474 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW117 -CYREG_SFLASH_ALT_PROT_ROW117 EQU 0x0ffff875 +CYREG_SFLASH_ALT_PROT_ROW117 EQU 0x0ffff475 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW118 -CYREG_SFLASH_ALT_PROT_ROW118 EQU 0x0ffff876 +CYREG_SFLASH_ALT_PROT_ROW118 EQU 0x0ffff476 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW119 -CYREG_SFLASH_ALT_PROT_ROW119 EQU 0x0ffff877 +CYREG_SFLASH_ALT_PROT_ROW119 EQU 0x0ffff477 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW120 -CYREG_SFLASH_ALT_PROT_ROW120 EQU 0x0ffff878 +CYREG_SFLASH_ALT_PROT_ROW120 EQU 0x0ffff478 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW121 -CYREG_SFLASH_ALT_PROT_ROW121 EQU 0x0ffff879 +CYREG_SFLASH_ALT_PROT_ROW121 EQU 0x0ffff479 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW122 -CYREG_SFLASH_ALT_PROT_ROW122 EQU 0x0ffff87a +CYREG_SFLASH_ALT_PROT_ROW122 EQU 0x0ffff47a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW123 -CYREG_SFLASH_ALT_PROT_ROW123 EQU 0x0ffff87b +CYREG_SFLASH_ALT_PROT_ROW123 EQU 0x0ffff47b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW124 -CYREG_SFLASH_ALT_PROT_ROW124 EQU 0x0ffff87c +CYREG_SFLASH_ALT_PROT_ROW124 EQU 0x0ffff47c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW125 -CYREG_SFLASH_ALT_PROT_ROW125 EQU 0x0ffff87d +CYREG_SFLASH_ALT_PROT_ROW125 EQU 0x0ffff47d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW126 -CYREG_SFLASH_ALT_PROT_ROW126 EQU 0x0ffff87e +CYREG_SFLASH_ALT_PROT_ROW126 EQU 0x0ffff47e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW127 -CYREG_SFLASH_ALT_PROT_ROW127 EQU 0x0ffff87f +CYREG_SFLASH_ALT_PROT_ROW127 EQU 0x0ffff47f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW128 -CYREG_SFLASH_ALT_PROT_ROW128 EQU 0x0ffff880 +CYREG_SFLASH_ALT_PROT_ROW128 EQU 0x0ffff480 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW129 -CYREG_SFLASH_ALT_PROT_ROW129 EQU 0x0ffff881 +CYREG_SFLASH_ALT_PROT_ROW129 EQU 0x0ffff481 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW130 -CYREG_SFLASH_ALT_PROT_ROW130 EQU 0x0ffff882 +CYREG_SFLASH_ALT_PROT_ROW130 EQU 0x0ffff482 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW131 -CYREG_SFLASH_ALT_PROT_ROW131 EQU 0x0ffff883 +CYREG_SFLASH_ALT_PROT_ROW131 EQU 0x0ffff483 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW132 -CYREG_SFLASH_ALT_PROT_ROW132 EQU 0x0ffff884 +CYREG_SFLASH_ALT_PROT_ROW132 EQU 0x0ffff484 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW133 -CYREG_SFLASH_ALT_PROT_ROW133 EQU 0x0ffff885 +CYREG_SFLASH_ALT_PROT_ROW133 EQU 0x0ffff485 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW134 -CYREG_SFLASH_ALT_PROT_ROW134 EQU 0x0ffff886 +CYREG_SFLASH_ALT_PROT_ROW134 EQU 0x0ffff486 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW135 -CYREG_SFLASH_ALT_PROT_ROW135 EQU 0x0ffff887 +CYREG_SFLASH_ALT_PROT_ROW135 EQU 0x0ffff487 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW136 -CYREG_SFLASH_ALT_PROT_ROW136 EQU 0x0ffff888 +CYREG_SFLASH_ALT_PROT_ROW136 EQU 0x0ffff488 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW137 -CYREG_SFLASH_ALT_PROT_ROW137 EQU 0x0ffff889 +CYREG_SFLASH_ALT_PROT_ROW137 EQU 0x0ffff489 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW138 -CYREG_SFLASH_ALT_PROT_ROW138 EQU 0x0ffff88a +CYREG_SFLASH_ALT_PROT_ROW138 EQU 0x0ffff48a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW139 -CYREG_SFLASH_ALT_PROT_ROW139 EQU 0x0ffff88b +CYREG_SFLASH_ALT_PROT_ROW139 EQU 0x0ffff48b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW140 -CYREG_SFLASH_ALT_PROT_ROW140 EQU 0x0ffff88c +CYREG_SFLASH_ALT_PROT_ROW140 EQU 0x0ffff48c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW141 -CYREG_SFLASH_ALT_PROT_ROW141 EQU 0x0ffff88d +CYREG_SFLASH_ALT_PROT_ROW141 EQU 0x0ffff48d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW142 -CYREG_SFLASH_ALT_PROT_ROW142 EQU 0x0ffff88e +CYREG_SFLASH_ALT_PROT_ROW142 EQU 0x0ffff48e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW143 -CYREG_SFLASH_ALT_PROT_ROW143 EQU 0x0ffff88f +CYREG_SFLASH_ALT_PROT_ROW143 EQU 0x0ffff48f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW144 -CYREG_SFLASH_ALT_PROT_ROW144 EQU 0x0ffff890 +CYREG_SFLASH_ALT_PROT_ROW144 EQU 0x0ffff490 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW145 -CYREG_SFLASH_ALT_PROT_ROW145 EQU 0x0ffff891 +CYREG_SFLASH_ALT_PROT_ROW145 EQU 0x0ffff491 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW146 -CYREG_SFLASH_ALT_PROT_ROW146 EQU 0x0ffff892 +CYREG_SFLASH_ALT_PROT_ROW146 EQU 0x0ffff492 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW147 -CYREG_SFLASH_ALT_PROT_ROW147 EQU 0x0ffff893 +CYREG_SFLASH_ALT_PROT_ROW147 EQU 0x0ffff493 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW148 -CYREG_SFLASH_ALT_PROT_ROW148 EQU 0x0ffff894 +CYREG_SFLASH_ALT_PROT_ROW148 EQU 0x0ffff494 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW149 -CYREG_SFLASH_ALT_PROT_ROW149 EQU 0x0ffff895 +CYREG_SFLASH_ALT_PROT_ROW149 EQU 0x0ffff495 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW150 -CYREG_SFLASH_ALT_PROT_ROW150 EQU 0x0ffff896 +CYREG_SFLASH_ALT_PROT_ROW150 EQU 0x0ffff496 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW151 -CYREG_SFLASH_ALT_PROT_ROW151 EQU 0x0ffff897 +CYREG_SFLASH_ALT_PROT_ROW151 EQU 0x0ffff497 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW152 -CYREG_SFLASH_ALT_PROT_ROW152 EQU 0x0ffff898 +CYREG_SFLASH_ALT_PROT_ROW152 EQU 0x0ffff498 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW153 -CYREG_SFLASH_ALT_PROT_ROW153 EQU 0x0ffff899 +CYREG_SFLASH_ALT_PROT_ROW153 EQU 0x0ffff499 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW154 -CYREG_SFLASH_ALT_PROT_ROW154 EQU 0x0ffff89a +CYREG_SFLASH_ALT_PROT_ROW154 EQU 0x0ffff49a ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW155 -CYREG_SFLASH_ALT_PROT_ROW155 EQU 0x0ffff89b +CYREG_SFLASH_ALT_PROT_ROW155 EQU 0x0ffff49b ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW156 -CYREG_SFLASH_ALT_PROT_ROW156 EQU 0x0ffff89c +CYREG_SFLASH_ALT_PROT_ROW156 EQU 0x0ffff49c ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW157 -CYREG_SFLASH_ALT_PROT_ROW157 EQU 0x0ffff89d +CYREG_SFLASH_ALT_PROT_ROW157 EQU 0x0ffff49d ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW158 -CYREG_SFLASH_ALT_PROT_ROW158 EQU 0x0ffff89e +CYREG_SFLASH_ALT_PROT_ROW158 EQU 0x0ffff49e ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW159 -CYREG_SFLASH_ALT_PROT_ROW159 EQU 0x0ffff89f +CYREG_SFLASH_ALT_PROT_ROW159 EQU 0x0ffff49f ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW160 -CYREG_SFLASH_ALT_PROT_ROW160 EQU 0x0ffff8a0 +CYREG_SFLASH_ALT_PROT_ROW160 EQU 0x0ffff4a0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW161 -CYREG_SFLASH_ALT_PROT_ROW161 EQU 0x0ffff8a1 +CYREG_SFLASH_ALT_PROT_ROW161 EQU 0x0ffff4a1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW162 -CYREG_SFLASH_ALT_PROT_ROW162 EQU 0x0ffff8a2 +CYREG_SFLASH_ALT_PROT_ROW162 EQU 0x0ffff4a2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW163 -CYREG_SFLASH_ALT_PROT_ROW163 EQU 0x0ffff8a3 +CYREG_SFLASH_ALT_PROT_ROW163 EQU 0x0ffff4a3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW164 -CYREG_SFLASH_ALT_PROT_ROW164 EQU 0x0ffff8a4 +CYREG_SFLASH_ALT_PROT_ROW164 EQU 0x0ffff4a4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW165 -CYREG_SFLASH_ALT_PROT_ROW165 EQU 0x0ffff8a5 +CYREG_SFLASH_ALT_PROT_ROW165 EQU 0x0ffff4a5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW166 -CYREG_SFLASH_ALT_PROT_ROW166 EQU 0x0ffff8a6 +CYREG_SFLASH_ALT_PROT_ROW166 EQU 0x0ffff4a6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW167 -CYREG_SFLASH_ALT_PROT_ROW167 EQU 0x0ffff8a7 +CYREG_SFLASH_ALT_PROT_ROW167 EQU 0x0ffff4a7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW168 -CYREG_SFLASH_ALT_PROT_ROW168 EQU 0x0ffff8a8 +CYREG_SFLASH_ALT_PROT_ROW168 EQU 0x0ffff4a8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW169 -CYREG_SFLASH_ALT_PROT_ROW169 EQU 0x0ffff8a9 +CYREG_SFLASH_ALT_PROT_ROW169 EQU 0x0ffff4a9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW170 -CYREG_SFLASH_ALT_PROT_ROW170 EQU 0x0ffff8aa +CYREG_SFLASH_ALT_PROT_ROW170 EQU 0x0ffff4aa ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW171 -CYREG_SFLASH_ALT_PROT_ROW171 EQU 0x0ffff8ab +CYREG_SFLASH_ALT_PROT_ROW171 EQU 0x0ffff4ab ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW172 -CYREG_SFLASH_ALT_PROT_ROW172 EQU 0x0ffff8ac +CYREG_SFLASH_ALT_PROT_ROW172 EQU 0x0ffff4ac ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW173 -CYREG_SFLASH_ALT_PROT_ROW173 EQU 0x0ffff8ad +CYREG_SFLASH_ALT_PROT_ROW173 EQU 0x0ffff4ad ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW174 -CYREG_SFLASH_ALT_PROT_ROW174 EQU 0x0ffff8ae +CYREG_SFLASH_ALT_PROT_ROW174 EQU 0x0ffff4ae ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW175 -CYREG_SFLASH_ALT_PROT_ROW175 EQU 0x0ffff8af +CYREG_SFLASH_ALT_PROT_ROW175 EQU 0x0ffff4af ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW176 -CYREG_SFLASH_ALT_PROT_ROW176 EQU 0x0ffff8b0 +CYREG_SFLASH_ALT_PROT_ROW176 EQU 0x0ffff4b0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW177 -CYREG_SFLASH_ALT_PROT_ROW177 EQU 0x0ffff8b1 +CYREG_SFLASH_ALT_PROT_ROW177 EQU 0x0ffff4b1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW178 -CYREG_SFLASH_ALT_PROT_ROW178 EQU 0x0ffff8b2 +CYREG_SFLASH_ALT_PROT_ROW178 EQU 0x0ffff4b2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW179 -CYREG_SFLASH_ALT_PROT_ROW179 EQU 0x0ffff8b3 +CYREG_SFLASH_ALT_PROT_ROW179 EQU 0x0ffff4b3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW180 -CYREG_SFLASH_ALT_PROT_ROW180 EQU 0x0ffff8b4 +CYREG_SFLASH_ALT_PROT_ROW180 EQU 0x0ffff4b4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW181 -CYREG_SFLASH_ALT_PROT_ROW181 EQU 0x0ffff8b5 +CYREG_SFLASH_ALT_PROT_ROW181 EQU 0x0ffff4b5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW182 -CYREG_SFLASH_ALT_PROT_ROW182 EQU 0x0ffff8b6 +CYREG_SFLASH_ALT_PROT_ROW182 EQU 0x0ffff4b6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW183 -CYREG_SFLASH_ALT_PROT_ROW183 EQU 0x0ffff8b7 +CYREG_SFLASH_ALT_PROT_ROW183 EQU 0x0ffff4b7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW184 -CYREG_SFLASH_ALT_PROT_ROW184 EQU 0x0ffff8b8 +CYREG_SFLASH_ALT_PROT_ROW184 EQU 0x0ffff4b8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW185 -CYREG_SFLASH_ALT_PROT_ROW185 EQU 0x0ffff8b9 +CYREG_SFLASH_ALT_PROT_ROW185 EQU 0x0ffff4b9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW186 -CYREG_SFLASH_ALT_PROT_ROW186 EQU 0x0ffff8ba +CYREG_SFLASH_ALT_PROT_ROW186 EQU 0x0ffff4ba ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW187 -CYREG_SFLASH_ALT_PROT_ROW187 EQU 0x0ffff8bb +CYREG_SFLASH_ALT_PROT_ROW187 EQU 0x0ffff4bb ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW188 -CYREG_SFLASH_ALT_PROT_ROW188 EQU 0x0ffff8bc +CYREG_SFLASH_ALT_PROT_ROW188 EQU 0x0ffff4bc ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW189 -CYREG_SFLASH_ALT_PROT_ROW189 EQU 0x0ffff8bd +CYREG_SFLASH_ALT_PROT_ROW189 EQU 0x0ffff4bd ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW190 -CYREG_SFLASH_ALT_PROT_ROW190 EQU 0x0ffff8be +CYREG_SFLASH_ALT_PROT_ROW190 EQU 0x0ffff4be ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW191 -CYREG_SFLASH_ALT_PROT_ROW191 EQU 0x0ffff8bf +CYREG_SFLASH_ALT_PROT_ROW191 EQU 0x0ffff4bf ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW192 -CYREG_SFLASH_ALT_PROT_ROW192 EQU 0x0ffff8c0 +CYREG_SFLASH_ALT_PROT_ROW192 EQU 0x0ffff4c0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW193 -CYREG_SFLASH_ALT_PROT_ROW193 EQU 0x0ffff8c1 +CYREG_SFLASH_ALT_PROT_ROW193 EQU 0x0ffff4c1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW194 -CYREG_SFLASH_ALT_PROT_ROW194 EQU 0x0ffff8c2 +CYREG_SFLASH_ALT_PROT_ROW194 EQU 0x0ffff4c2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW195 -CYREG_SFLASH_ALT_PROT_ROW195 EQU 0x0ffff8c3 +CYREG_SFLASH_ALT_PROT_ROW195 EQU 0x0ffff4c3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW196 -CYREG_SFLASH_ALT_PROT_ROW196 EQU 0x0ffff8c4 +CYREG_SFLASH_ALT_PROT_ROW196 EQU 0x0ffff4c4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW197 -CYREG_SFLASH_ALT_PROT_ROW197 EQU 0x0ffff8c5 +CYREG_SFLASH_ALT_PROT_ROW197 EQU 0x0ffff4c5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW198 -CYREG_SFLASH_ALT_PROT_ROW198 EQU 0x0ffff8c6 +CYREG_SFLASH_ALT_PROT_ROW198 EQU 0x0ffff4c6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW199 -CYREG_SFLASH_ALT_PROT_ROW199 EQU 0x0ffff8c7 +CYREG_SFLASH_ALT_PROT_ROW199 EQU 0x0ffff4c7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW200 -CYREG_SFLASH_ALT_PROT_ROW200 EQU 0x0ffff8c8 +CYREG_SFLASH_ALT_PROT_ROW200 EQU 0x0ffff4c8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW201 -CYREG_SFLASH_ALT_PROT_ROW201 EQU 0x0ffff8c9 +CYREG_SFLASH_ALT_PROT_ROW201 EQU 0x0ffff4c9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW202 -CYREG_SFLASH_ALT_PROT_ROW202 EQU 0x0ffff8ca +CYREG_SFLASH_ALT_PROT_ROW202 EQU 0x0ffff4ca ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW203 -CYREG_SFLASH_ALT_PROT_ROW203 EQU 0x0ffff8cb +CYREG_SFLASH_ALT_PROT_ROW203 EQU 0x0ffff4cb ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW204 -CYREG_SFLASH_ALT_PROT_ROW204 EQU 0x0ffff8cc +CYREG_SFLASH_ALT_PROT_ROW204 EQU 0x0ffff4cc ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW205 -CYREG_SFLASH_ALT_PROT_ROW205 EQU 0x0ffff8cd +CYREG_SFLASH_ALT_PROT_ROW205 EQU 0x0ffff4cd ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW206 -CYREG_SFLASH_ALT_PROT_ROW206 EQU 0x0ffff8ce +CYREG_SFLASH_ALT_PROT_ROW206 EQU 0x0ffff4ce ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW207 -CYREG_SFLASH_ALT_PROT_ROW207 EQU 0x0ffff8cf +CYREG_SFLASH_ALT_PROT_ROW207 EQU 0x0ffff4cf ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW208 -CYREG_SFLASH_ALT_PROT_ROW208 EQU 0x0ffff8d0 +CYREG_SFLASH_ALT_PROT_ROW208 EQU 0x0ffff4d0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW209 -CYREG_SFLASH_ALT_PROT_ROW209 EQU 0x0ffff8d1 +CYREG_SFLASH_ALT_PROT_ROW209 EQU 0x0ffff4d1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW210 -CYREG_SFLASH_ALT_PROT_ROW210 EQU 0x0ffff8d2 +CYREG_SFLASH_ALT_PROT_ROW210 EQU 0x0ffff4d2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW211 -CYREG_SFLASH_ALT_PROT_ROW211 EQU 0x0ffff8d3 +CYREG_SFLASH_ALT_PROT_ROW211 EQU 0x0ffff4d3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW212 -CYREG_SFLASH_ALT_PROT_ROW212 EQU 0x0ffff8d4 +CYREG_SFLASH_ALT_PROT_ROW212 EQU 0x0ffff4d4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW213 -CYREG_SFLASH_ALT_PROT_ROW213 EQU 0x0ffff8d5 +CYREG_SFLASH_ALT_PROT_ROW213 EQU 0x0ffff4d5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW214 -CYREG_SFLASH_ALT_PROT_ROW214 EQU 0x0ffff8d6 +CYREG_SFLASH_ALT_PROT_ROW214 EQU 0x0ffff4d6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW215 -CYREG_SFLASH_ALT_PROT_ROW215 EQU 0x0ffff8d7 +CYREG_SFLASH_ALT_PROT_ROW215 EQU 0x0ffff4d7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW216 -CYREG_SFLASH_ALT_PROT_ROW216 EQU 0x0ffff8d8 +CYREG_SFLASH_ALT_PROT_ROW216 EQU 0x0ffff4d8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW217 -CYREG_SFLASH_ALT_PROT_ROW217 EQU 0x0ffff8d9 +CYREG_SFLASH_ALT_PROT_ROW217 EQU 0x0ffff4d9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW218 -CYREG_SFLASH_ALT_PROT_ROW218 EQU 0x0ffff8da +CYREG_SFLASH_ALT_PROT_ROW218 EQU 0x0ffff4da ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW219 -CYREG_SFLASH_ALT_PROT_ROW219 EQU 0x0ffff8db +CYREG_SFLASH_ALT_PROT_ROW219 EQU 0x0ffff4db ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW220 -CYREG_SFLASH_ALT_PROT_ROW220 EQU 0x0ffff8dc +CYREG_SFLASH_ALT_PROT_ROW220 EQU 0x0ffff4dc ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW221 -CYREG_SFLASH_ALT_PROT_ROW221 EQU 0x0ffff8dd +CYREG_SFLASH_ALT_PROT_ROW221 EQU 0x0ffff4dd ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW222 -CYREG_SFLASH_ALT_PROT_ROW222 EQU 0x0ffff8de +CYREG_SFLASH_ALT_PROT_ROW222 EQU 0x0ffff4de ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW223 -CYREG_SFLASH_ALT_PROT_ROW223 EQU 0x0ffff8df +CYREG_SFLASH_ALT_PROT_ROW223 EQU 0x0ffff4df ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW224 -CYREG_SFLASH_ALT_PROT_ROW224 EQU 0x0ffff8e0 +CYREG_SFLASH_ALT_PROT_ROW224 EQU 0x0ffff4e0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW225 -CYREG_SFLASH_ALT_PROT_ROW225 EQU 0x0ffff8e1 +CYREG_SFLASH_ALT_PROT_ROW225 EQU 0x0ffff4e1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW226 -CYREG_SFLASH_ALT_PROT_ROW226 EQU 0x0ffff8e2 +CYREG_SFLASH_ALT_PROT_ROW226 EQU 0x0ffff4e2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW227 -CYREG_SFLASH_ALT_PROT_ROW227 EQU 0x0ffff8e3 +CYREG_SFLASH_ALT_PROT_ROW227 EQU 0x0ffff4e3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW228 -CYREG_SFLASH_ALT_PROT_ROW228 EQU 0x0ffff8e4 +CYREG_SFLASH_ALT_PROT_ROW228 EQU 0x0ffff4e4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW229 -CYREG_SFLASH_ALT_PROT_ROW229 EQU 0x0ffff8e5 +CYREG_SFLASH_ALT_PROT_ROW229 EQU 0x0ffff4e5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW230 -CYREG_SFLASH_ALT_PROT_ROW230 EQU 0x0ffff8e6 +CYREG_SFLASH_ALT_PROT_ROW230 EQU 0x0ffff4e6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW231 -CYREG_SFLASH_ALT_PROT_ROW231 EQU 0x0ffff8e7 +CYREG_SFLASH_ALT_PROT_ROW231 EQU 0x0ffff4e7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW232 -CYREG_SFLASH_ALT_PROT_ROW232 EQU 0x0ffff8e8 +CYREG_SFLASH_ALT_PROT_ROW232 EQU 0x0ffff4e8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW233 -CYREG_SFLASH_ALT_PROT_ROW233 EQU 0x0ffff8e9 +CYREG_SFLASH_ALT_PROT_ROW233 EQU 0x0ffff4e9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW234 -CYREG_SFLASH_ALT_PROT_ROW234 EQU 0x0ffff8ea +CYREG_SFLASH_ALT_PROT_ROW234 EQU 0x0ffff4ea ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW235 -CYREG_SFLASH_ALT_PROT_ROW235 EQU 0x0ffff8eb +CYREG_SFLASH_ALT_PROT_ROW235 EQU 0x0ffff4eb ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW236 -CYREG_SFLASH_ALT_PROT_ROW236 EQU 0x0ffff8ec +CYREG_SFLASH_ALT_PROT_ROW236 EQU 0x0ffff4ec ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW237 -CYREG_SFLASH_ALT_PROT_ROW237 EQU 0x0ffff8ed +CYREG_SFLASH_ALT_PROT_ROW237 EQU 0x0ffff4ed ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW238 -CYREG_SFLASH_ALT_PROT_ROW238 EQU 0x0ffff8ee +CYREG_SFLASH_ALT_PROT_ROW238 EQU 0x0ffff4ee ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW239 -CYREG_SFLASH_ALT_PROT_ROW239 EQU 0x0ffff8ef +CYREG_SFLASH_ALT_PROT_ROW239 EQU 0x0ffff4ef ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW240 -CYREG_SFLASH_ALT_PROT_ROW240 EQU 0x0ffff8f0 +CYREG_SFLASH_ALT_PROT_ROW240 EQU 0x0ffff4f0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW241 -CYREG_SFLASH_ALT_PROT_ROW241 EQU 0x0ffff8f1 +CYREG_SFLASH_ALT_PROT_ROW241 EQU 0x0ffff4f1 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW242 -CYREG_SFLASH_ALT_PROT_ROW242 EQU 0x0ffff8f2 +CYREG_SFLASH_ALT_PROT_ROW242 EQU 0x0ffff4f2 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW243 -CYREG_SFLASH_ALT_PROT_ROW243 EQU 0x0ffff8f3 +CYREG_SFLASH_ALT_PROT_ROW243 EQU 0x0ffff4f3 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW244 -CYREG_SFLASH_ALT_PROT_ROW244 EQU 0x0ffff8f4 +CYREG_SFLASH_ALT_PROT_ROW244 EQU 0x0ffff4f4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW245 -CYREG_SFLASH_ALT_PROT_ROW245 EQU 0x0ffff8f5 +CYREG_SFLASH_ALT_PROT_ROW245 EQU 0x0ffff4f5 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW246 -CYREG_SFLASH_ALT_PROT_ROW246 EQU 0x0ffff8f6 +CYREG_SFLASH_ALT_PROT_ROW246 EQU 0x0ffff4f6 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW247 -CYREG_SFLASH_ALT_PROT_ROW247 EQU 0x0ffff8f7 +CYREG_SFLASH_ALT_PROT_ROW247 EQU 0x0ffff4f7 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW248 -CYREG_SFLASH_ALT_PROT_ROW248 EQU 0x0ffff8f8 +CYREG_SFLASH_ALT_PROT_ROW248 EQU 0x0ffff4f8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW249 -CYREG_SFLASH_ALT_PROT_ROW249 EQU 0x0ffff8f9 +CYREG_SFLASH_ALT_PROT_ROW249 EQU 0x0ffff4f9 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW250 -CYREG_SFLASH_ALT_PROT_ROW250 EQU 0x0ffff8fa +CYREG_SFLASH_ALT_PROT_ROW250 EQU 0x0ffff4fa ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW251 -CYREG_SFLASH_ALT_PROT_ROW251 EQU 0x0ffff8fb +CYREG_SFLASH_ALT_PROT_ROW251 EQU 0x0ffff4fb ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW252 -CYREG_SFLASH_ALT_PROT_ROW252 EQU 0x0ffff8fc +CYREG_SFLASH_ALT_PROT_ROW252 EQU 0x0ffff4fc ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW253 -CYREG_SFLASH_ALT_PROT_ROW253 EQU 0x0ffff8fd +CYREG_SFLASH_ALT_PROT_ROW253 EQU 0x0ffff4fd ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW254 -CYREG_SFLASH_ALT_PROT_ROW254 EQU 0x0ffff8fe +CYREG_SFLASH_ALT_PROT_ROW254 EQU 0x0ffff4fe ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PROT_ROW255 -CYREG_SFLASH_ALT_PROT_ROW255 EQU 0x0ffff8ff +CYREG_SFLASH_ALT_PROT_ROW255 EQU 0x0ffff4ff ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_PP -CYREG_SFLASH_ALT_PP EQU 0x0ffffb20 +CYREG_SFLASH_ALT_PP EQU 0x0ffff5a0 ENDIF IF :LNOT::DEF:CYFLD_SFLASH_PERIOD__OFFSET CYFLD_SFLASH_PERIOD__OFFSET EQU 0x00000000 @@ -5297,25 +3623,25 @@ CYFLD_SFLASH_NDAC__OFFSET EQU 0x0000001c CYFLD_SFLASH_NDAC__SIZE EQU 0x00000004 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_E -CYREG_SFLASH_ALT_E EQU 0x0ffffb24 +CYREG_SFLASH_ALT_E EQU 0x0ffff5a4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_P -CYREG_SFLASH_ALT_P EQU 0x0ffffb28 +CYREG_SFLASH_ALT_P EQU 0x0ffff5a8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_EA_E -CYREG_SFLASH_ALT_EA_E EQU 0x0ffffb2c +CYREG_SFLASH_ALT_EA_E EQU 0x0ffff5ac ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_EA_P -CYREG_SFLASH_ALT_EA_P EQU 0x0ffffb30 +CYREG_SFLASH_ALT_EA_P EQU 0x0ffff5b0 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_ES_E -CYREG_SFLASH_ALT_ES_E EQU 0x0ffffb34 +CYREG_SFLASH_ALT_ES_E EQU 0x0ffff5b4 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_ES_P_EO -CYREG_SFLASH_ALT_ES_P_EO EQU 0x0ffffb38 +CYREG_SFLASH_ALT_ES_P_EO EQU 0x0ffff5b8 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_E_VCTAT -CYREG_SFLASH_ALT_E_VCTAT EQU 0x0ffffb3c +CYREG_SFLASH_ALT_E_VCTAT EQU 0x0ffff5bc ENDIF IF :LNOT::DEF:CYFLD_SFLASH_VCTAT_SLOPE__OFFSET CYFLD_SFLASH_VCTAT_SLOPE__OFFSET EQU 0x00000000 @@ -5336,7 +3662,7 @@ CYFLD_SFLASH_VCTAT_ENABLE__OFFSET EQU 0x00000006 CYFLD_SFLASH_VCTAT_ENABLE__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_SFLASH_ALT_P_VCTAT -CYREG_SFLASH_ALT_P_VCTAT EQU 0x0ffffb3d +CYREG_SFLASH_ALT_P_VCTAT EQU 0x0ffff5bd ENDIF IF :LNOT::DEF:CYDEV_ROM_BASE CYDEV_ROM_BASE EQU 0x10000000 @@ -5354,13 +3680,13 @@ CYREG_ROM_DATA_MSIZE EQU 0x00002000 CYDEV_SRAM_BASE EQU 0x20000000 ENDIF IF :LNOT::DEF:CYDEV_SRAM_SIZE -CYDEV_SRAM_SIZE EQU 0x00008000 +CYDEV_SRAM_SIZE EQU 0x00004000 ENDIF IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE CYREG_SRAM_DATA_MBASE EQU 0x20000000 ENDIF IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE -CYREG_SRAM_DATA_MSIZE EQU 0x00008000 +CYREG_SRAM_DATA_MSIZE EQU 0x00004000 ENDIF IF :LNOT::DEF:CYDEV_PERI_BASE CYDEV_PERI_BASE EQU 0x40010000 @@ -5508,75 +3834,6 @@ CYFLD_PERI_FRAC5_DIV__SIZE EQU 0x00000005 ENDIF IF :LNOT::DEF:CYREG_PERI_DIV_16_5_CTL1 CYREG_PERI_DIV_16_5_CTL1 EQU 0x40010404 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_CTL -CYREG_PERI_TR_CTL EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_SEL__OFFSET -CYFLD_PERI_TR_SEL__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_SEL__SIZE -CYFLD_PERI_TR_SEL__SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_GROUP__OFFSET -CYFLD_PERI_TR_GROUP__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_GROUP__SIZE -CYFLD_PERI_TR_GROUP__SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_COUNT__OFFSET -CYFLD_PERI_TR_COUNT__OFFSET EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_COUNT__SIZE -CYFLD_PERI_TR_COUNT__SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_OUT__OFFSET -CYFLD_PERI_TR_OUT__OFFSET EQU 0x0000001e - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_OUT__SIZE -CYFLD_PERI_TR_OUT__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_ACT__OFFSET -CYFLD_PERI_TR_ACT__OFFSET EQU 0x0000001f - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_ACT__SIZE -CYFLD_PERI_TR_ACT__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PERI_TR_GROUP_BASE -CYDEV_PERI_TR_GROUP_BASE EQU 0x40012000 - ENDIF - IF :LNOT::DEF:CYDEV_PERI_TR_GROUP_SIZE -CYDEV_PERI_TR_GROUP_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL0 -CYREG_PERI_TR_GROUP_TR_OUT_CTL0 EQU 0x40012000 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_GROUP_SEL__OFFSET -CYFLD_PERI_TR_GROUP_SEL__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_PERI_TR_GROUP_SEL__SIZE -CYFLD_PERI_TR_GROUP_SEL__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL1 -CYREG_PERI_TR_GROUP_TR_OUT_CTL1 EQU 0x40012004 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL2 -CYREG_PERI_TR_GROUP_TR_OUT_CTL2 EQU 0x40012008 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL3 -CYREG_PERI_TR_GROUP_TR_OUT_CTL3 EQU 0x4001200c - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL4 -CYREG_PERI_TR_GROUP_TR_OUT_CTL4 EQU 0x40012010 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL5 -CYREG_PERI_TR_GROUP_TR_OUT_CTL5 EQU 0x40012014 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL6 -CYREG_PERI_TR_GROUP_TR_OUT_CTL6 EQU 0x40012018 - ENDIF - IF :LNOT::DEF:CYREG_PERI_TR_GROUP_TR_OUT_CTL7 -CYREG_PERI_TR_GROUP_TR_OUT_CTL7 EQU 0x4001201c ENDIF IF :LNOT::DEF:CYDEV_HSIOM_BASE CYDEV_HSIOM_BASE EQU 0x40020000 @@ -18632,574 +16889,106 @@ CYFLD_CPUSS_FLASH_LOCK__SIZE EQU 0x00000001 CYFLD_CPUSS_PROTECTION_LOCK__OFFSET EQU 0x0000001f ENDIF IF :LNOT::DEF:CYFLD_CPUSS_PROTECTION_LOCK__SIZE -CYFLD_CPUSS_PROTECTION_LOCK__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_PRIV_ROM -CYREG_CPUSS_PRIV_ROM EQU 0x40100010 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET -CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE -CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_PRIV_RAM -CYREG_CPUSS_PRIV_RAM EQU 0x40100014 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET -CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE -CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_PRIV_FLASH -CYREG_CPUSS_PRIV_FLASH EQU 0x40100018 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET -CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE -CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_WOUNDING -CYREG_CPUSS_WOUNDING EQU 0x4010001c - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__OFFSET -CYFLD_CPUSS_RAM_WOUND__OFFSET EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__SIZE -CYFLD_CPUSS_RAM_WOUND__SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__OFFSET -CYFLD_CPUSS_FLASH_WOUND__OFFSET EQU 0x00000014 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__SIZE -CYFLD_CPUSS_FLASH_WOUND__SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_INT_SEL -CYREG_CPUSS_INT_SEL EQU 0x40100020 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_DSI__OFFSET -CYFLD_CPUSS_DSI__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_DSI__SIZE -CYFLD_CPUSS_DSI__SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_INT_MODE -CYREG_CPUSS_INT_MODE EQU 0x40100024 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_DSI_INT_PULSE__OFFSET -CYFLD_CPUSS_DSI_INT_PULSE__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_DSI_INT_PULSE__SIZE -CYFLD_CPUSS_DSI_INT_PULSE__SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_NMI_MODE -CYREG_CPUSS_NMI_MODE EQU 0x40100028 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_DSI_NMI_PULSE__OFFSET -CYFLD_CPUSS_DSI_NMI_PULSE__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_DSI_NMI_PULSE__SIZE -CYFLD_CPUSS_DSI_NMI_PULSE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_FLASH_CTL -CYREG_CPUSS_FLASH_CTL EQU 0x40100030 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WS__OFFSET -CYFLD_CPUSS_FLASH_WS__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WS__SIZE -CYFLD_CPUSS_FLASH_WS__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_PREF_EN__OFFSET -CYFLD_CPUSS_PREF_EN__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_PREF_EN__SIZE -CYFLD_CPUSS_PREF_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET -CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_FLASH_INVALIDATE__SIZE -CYFLD_CPUSS_FLASH_INVALIDATE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_ARB__OFFSET -CYFLD_CPUSS_ARB__OFFSET EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_ARB__SIZE -CYFLD_CPUSS_ARB__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_ROM_CTL -CYREG_CPUSS_ROM_CTL EQU 0x40100034 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_ROM_WS__OFFSET -CYFLD_CPUSS_ROM_WS__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_CPUSS_ROM_WS__SIZE -CYFLD_CPUSS_ROM_WS__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_RAM_CTL -CYREG_CPUSS_RAM_CTL EQU 0x40100038 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_DMAC_CTL -CYREG_CPUSS_DMAC_CTL EQU 0x4010003c - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_SL_CTL0 -CYREG_CPUSS_SL_CTL0 EQU 0x40100100 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_SL_CTL1 -CYREG_CPUSS_SL_CTL1 EQU 0x40100104 - ENDIF - IF :LNOT::DEF:CYREG_CPUSS_SL_CTL2 -CYREG_CPUSS_SL_CTL2 EQU 0x40100108 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_BASE -CYDEV_DMAC_BASE EQU 0x40101000 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_SIZE -CYDEV_DMAC_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CTL -CYREG_DMAC_CTL EQU 0x40101000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_ENABLED__OFFSET -CYFLD_DMAC_ENABLED__OFFSET EQU 0x0000001f - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_ENABLED__SIZE -CYFLD_DMAC_ENABLED__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_STATUS -CYREG_DMAC_STATUS EQU 0x40101010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DATA_NR__OFFSET -CYFLD_DMAC_DATA_NR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DATA_NR__SIZE -CYFLD_DMAC_DATA_NR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_CH_ADDR__OFFSET -CYFLD_DMAC_CH_ADDR__OFFSET EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_CH_ADDR__SIZE -CYFLD_DMAC_CH_ADDR__SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_STATE__OFFSET -CYFLD_DMAC_STATE__OFFSET EQU 0x00000018 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_STATE__SIZE -CYFLD_DMAC_STATE__SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_PRIO__OFFSET -CYFLD_DMAC_PRIO__OFFSET EQU 0x0000001c - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_PRIO__SIZE -CYFLD_DMAC_PRIO__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_PING_PONG__OFFSET -CYFLD_DMAC_PING_PONG__OFFSET EQU 0x0000001e - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_PING_PONG__SIZE -CYFLD_DMAC_PING_PONG__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_ACTIVE__OFFSET -CYFLD_DMAC_ACTIVE__OFFSET EQU 0x0000001f - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_ACTIVE__SIZE -CYFLD_DMAC_ACTIVE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_STATUS_SRC_ADDR -CYREG_DMAC_STATUS_SRC_ADDR EQU 0x40101014 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_ADDR__OFFSET -CYFLD_DMAC_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_ADDR__SIZE -CYFLD_DMAC_ADDR__SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_STATUS_DST_ADDR -CYREG_DMAC_STATUS_DST_ADDR EQU 0x40101018 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_STATUS_CH_ACT -CYREG_DMAC_STATUS_CH_ACT EQU 0x4010101c - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_CH__OFFSET -CYFLD_DMAC_CH__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_CH__SIZE -CYFLD_DMAC_CH__SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL0 -CYREG_DMAC_CH_CTL0 EQU 0x40101080 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL1 -CYREG_DMAC_CH_CTL1 EQU 0x40101084 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL2 -CYREG_DMAC_CH_CTL2 EQU 0x40101088 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL3 -CYREG_DMAC_CH_CTL3 EQU 0x4010108c - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL4 -CYREG_DMAC_CH_CTL4 EQU 0x40101090 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL5 -CYREG_DMAC_CH_CTL5 EQU 0x40101094 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL6 -CYREG_DMAC_CH_CTL6 EQU 0x40101098 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_CH_CTL7 -CYREG_DMAC_CH_CTL7 EQU 0x4010109c - ENDIF - IF :LNOT::DEF:CYREG_DMAC_INTR -CYREG_DMAC_INTR EQU 0x401017f0 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_INTR_SET -CYREG_DMAC_INTR_SET EQU 0x401017f4 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_INTR_MASK -CYREG_DMAC_INTR_MASK EQU 0x401017f8 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_INTR_MASKED -CYREG_DMAC_INTR_MASKED EQU 0x401017fc - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR0_BASE -CYDEV_DMAC_DESCR0_BASE EQU 0x40101800 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR0_SIZE -CYDEV_DMAC_DESCR0_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_SRC -CYREG_DMAC_DESCR0_PING_SRC EQU 0x40101800 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_ADDR__OFFSET -CYFLD_DMAC_DESCR_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_ADDR__SIZE -CYFLD_DMAC_DESCR_ADDR__SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_DST -CYREG_DMAC_DESCR0_PING_DST EQU 0x40101804 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_CTL -CYREG_DMAC_DESCR0_PING_CTL EQU 0x40101808 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_NR__OFFSET -CYFLD_DMAC_DESCR_DATA_NR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_NR__SIZE -CYFLD_DMAC_DESCR_DATA_NR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET -CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DATA_SIZE__SIZE -CYFLD_DMAC_DESCR_DATA_SIZE__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET -CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET EQU 0x00000014 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE -CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET -CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET EQU 0x00000015 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE -CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET -CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET EQU 0x00000016 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE -CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET -CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET EQU 0x00000017 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE -CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET -CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET EQU 0x00000018 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE -CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_INV_DESCR__OFFSET -CYFLD_DMAC_DESCR_INV_DESCR__OFFSET EQU 0x0000001a - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_INV_DESCR__SIZE -CYFLD_DMAC_DESCR_INV_DESCR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET -CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET EQU 0x0000001b - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_SET_CAUSE__SIZE -CYFLD_DMAC_DESCR_SET_CAUSE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET -CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET EQU 0x0000001c - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE -CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_FLIPPING__OFFSET -CYFLD_DMAC_DESCR_FLIPPING__OFFSET EQU 0x0000001d - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_FLIPPING__SIZE -CYFLD_DMAC_DESCR_FLIPPING__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_OPCODE__OFFSET -CYFLD_DMAC_DESCR_OPCODE__OFFSET EQU 0x0000001e - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_OPCODE__SIZE -CYFLD_DMAC_DESCR_OPCODE__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PING_STATUS -CYREG_DMAC_DESCR0_PING_STATUS EQU 0x4010180c - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET -CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE -CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_RESPONSE__OFFSET -CYFLD_DMAC_DESCR_RESPONSE__OFFSET EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_RESPONSE__SIZE -CYFLD_DMAC_DESCR_RESPONSE__SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_VALID__OFFSET -CYFLD_DMAC_DESCR_VALID__OFFSET EQU 0x0000001f - ENDIF - IF :LNOT::DEF:CYFLD_DMAC_DESCR_VALID__SIZE -CYFLD_DMAC_DESCR_VALID__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_SRC -CYREG_DMAC_DESCR0_PONG_SRC EQU 0x40101810 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_DST -CYREG_DMAC_DESCR0_PONG_DST EQU 0x40101814 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_CTL -CYREG_DMAC_DESCR0_PONG_CTL EQU 0x40101818 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR0_PONG_STATUS -CYREG_DMAC_DESCR0_PONG_STATUS EQU 0x4010181c - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR1_BASE -CYDEV_DMAC_DESCR1_BASE EQU 0x40101820 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR1_SIZE -CYDEV_DMAC_DESCR1_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_SRC -CYREG_DMAC_DESCR1_PING_SRC EQU 0x40101820 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_DST -CYREG_DMAC_DESCR1_PING_DST EQU 0x40101824 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_CTL -CYREG_DMAC_DESCR1_PING_CTL EQU 0x40101828 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PING_STATUS -CYREG_DMAC_DESCR1_PING_STATUS EQU 0x4010182c - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_SRC -CYREG_DMAC_DESCR1_PONG_SRC EQU 0x40101830 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_DST -CYREG_DMAC_DESCR1_PONG_DST EQU 0x40101834 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_CTL -CYREG_DMAC_DESCR1_PONG_CTL EQU 0x40101838 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR1_PONG_STATUS -CYREG_DMAC_DESCR1_PONG_STATUS EQU 0x4010183c - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR2_BASE -CYDEV_DMAC_DESCR2_BASE EQU 0x40101840 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR2_SIZE -CYDEV_DMAC_DESCR2_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_SRC -CYREG_DMAC_DESCR2_PING_SRC EQU 0x40101840 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_DST -CYREG_DMAC_DESCR2_PING_DST EQU 0x40101844 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_CTL -CYREG_DMAC_DESCR2_PING_CTL EQU 0x40101848 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PING_STATUS -CYREG_DMAC_DESCR2_PING_STATUS EQU 0x4010184c - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_SRC -CYREG_DMAC_DESCR2_PONG_SRC EQU 0x40101850 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_DST -CYREG_DMAC_DESCR2_PONG_DST EQU 0x40101854 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_CTL -CYREG_DMAC_DESCR2_PONG_CTL EQU 0x40101858 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR2_PONG_STATUS -CYREG_DMAC_DESCR2_PONG_STATUS EQU 0x4010185c - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR3_BASE -CYDEV_DMAC_DESCR3_BASE EQU 0x40101860 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR3_SIZE -CYDEV_DMAC_DESCR3_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_SRC -CYREG_DMAC_DESCR3_PING_SRC EQU 0x40101860 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_DST -CYREG_DMAC_DESCR3_PING_DST EQU 0x40101864 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_CTL -CYREG_DMAC_DESCR3_PING_CTL EQU 0x40101868 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PING_STATUS -CYREG_DMAC_DESCR3_PING_STATUS EQU 0x4010186c - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_SRC -CYREG_DMAC_DESCR3_PONG_SRC EQU 0x40101870 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_DST -CYREG_DMAC_DESCR3_PONG_DST EQU 0x40101874 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_CTL -CYREG_DMAC_DESCR3_PONG_CTL EQU 0x40101878 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR3_PONG_STATUS -CYREG_DMAC_DESCR3_PONG_STATUS EQU 0x4010187c - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR4_BASE -CYDEV_DMAC_DESCR4_BASE EQU 0x40101880 - ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR4_SIZE -CYDEV_DMAC_DESCR4_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_SRC -CYREG_DMAC_DESCR4_PING_SRC EQU 0x40101880 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_DST -CYREG_DMAC_DESCR4_PING_DST EQU 0x40101884 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_CTL -CYREG_DMAC_DESCR4_PING_CTL EQU 0x40101888 - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PING_STATUS -CYREG_DMAC_DESCR4_PING_STATUS EQU 0x4010188c - ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_SRC -CYREG_DMAC_DESCR4_PONG_SRC EQU 0x40101890 +CYFLD_CPUSS_PROTECTION_LOCK__SIZE EQU 0x00000001 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_DST -CYREG_DMAC_DESCR4_PONG_DST EQU 0x40101894 + IF :LNOT::DEF:CYREG_CPUSS_PRIV_ROM +CYREG_CPUSS_PRIV_ROM EQU 0x40100010 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_CTL -CYREG_DMAC_DESCR4_PONG_CTL EQU 0x40101898 + IF :LNOT::DEF:CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET +CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR4_PONG_STATUS -CYREG_DMAC_DESCR4_PONG_STATUS EQU 0x4010189c + IF :LNOT::DEF:CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE +CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE EQU 0x00000008 ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR5_BASE -CYDEV_DMAC_DESCR5_BASE EQU 0x401018a0 + IF :LNOT::DEF:CYREG_CPUSS_PRIV_RAM +CYREG_CPUSS_PRIV_RAM EQU 0x40100014 ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR5_SIZE -CYDEV_DMAC_DESCR5_SIZE EQU 0x00000020 + IF :LNOT::DEF:CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET +CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_SRC -CYREG_DMAC_DESCR5_PING_SRC EQU 0x401018a0 + IF :LNOT::DEF:CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE +CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE EQU 0x00000009 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_DST -CYREG_DMAC_DESCR5_PING_DST EQU 0x401018a4 + IF :LNOT::DEF:CYREG_CPUSS_PRIV_FLASH +CYREG_CPUSS_PRIV_FLASH EQU 0x40100018 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_CTL -CYREG_DMAC_DESCR5_PING_CTL EQU 0x401018a8 + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET +CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PING_STATUS -CYREG_DMAC_DESCR5_PING_STATUS EQU 0x401018ac + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE +CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE EQU 0x0000000b ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_SRC -CYREG_DMAC_DESCR5_PONG_SRC EQU 0x401018b0 + IF :LNOT::DEF:CYREG_CPUSS_WOUNDING +CYREG_CPUSS_WOUNDING EQU 0x4010001c ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_DST -CYREG_DMAC_DESCR5_PONG_DST EQU 0x401018b4 + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__OFFSET +CYFLD_CPUSS_RAM_WOUND__OFFSET EQU 0x00000010 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_CTL -CYREG_DMAC_DESCR5_PONG_CTL EQU 0x401018b8 + IF :LNOT::DEF:CYFLD_CPUSS_RAM_WOUND__SIZE +CYFLD_CPUSS_RAM_WOUND__SIZE EQU 0x00000003 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR5_PONG_STATUS -CYREG_DMAC_DESCR5_PONG_STATUS EQU 0x401018bc + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__OFFSET +CYFLD_CPUSS_FLASH_WOUND__OFFSET EQU 0x00000014 ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR6_BASE -CYDEV_DMAC_DESCR6_BASE EQU 0x401018c0 + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WOUND__SIZE +CYFLD_CPUSS_FLASH_WOUND__SIZE EQU 0x00000003 ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR6_SIZE -CYDEV_DMAC_DESCR6_SIZE EQU 0x00000020 + IF :LNOT::DEF:CYREG_CPUSS_INT_SEL +CYREG_CPUSS_INT_SEL EQU 0x40100020 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_SRC -CYREG_DMAC_DESCR6_PING_SRC EQU 0x401018c0 + IF :LNOT::DEF:CYFLD_CPUSS_DSI__OFFSET +CYFLD_CPUSS_DSI__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_DST -CYREG_DMAC_DESCR6_PING_DST EQU 0x401018c4 + IF :LNOT::DEF:CYFLD_CPUSS_DSI__SIZE +CYFLD_CPUSS_DSI__SIZE EQU 0x00000020 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_CTL -CYREG_DMAC_DESCR6_PING_CTL EQU 0x401018c8 + IF :LNOT::DEF:CYREG_CPUSS_INT_MODE +CYREG_CPUSS_INT_MODE EQU 0x40100024 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PING_STATUS -CYREG_DMAC_DESCR6_PING_STATUS EQU 0x401018cc + IF :LNOT::DEF:CYFLD_CPUSS_DSI_INT_PULSE__OFFSET +CYFLD_CPUSS_DSI_INT_PULSE__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_SRC -CYREG_DMAC_DESCR6_PONG_SRC EQU 0x401018d0 + IF :LNOT::DEF:CYFLD_CPUSS_DSI_INT_PULSE__SIZE +CYFLD_CPUSS_DSI_INT_PULSE__SIZE EQU 0x00000020 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_DST -CYREG_DMAC_DESCR6_PONG_DST EQU 0x401018d4 + IF :LNOT::DEF:CYREG_CPUSS_NMI_MODE +CYREG_CPUSS_NMI_MODE EQU 0x40100028 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_CTL -CYREG_DMAC_DESCR6_PONG_CTL EQU 0x401018d8 + IF :LNOT::DEF:CYFLD_CPUSS_DSI_NMI_PULSE__OFFSET +CYFLD_CPUSS_DSI_NMI_PULSE__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR6_PONG_STATUS -CYREG_DMAC_DESCR6_PONG_STATUS EQU 0x401018dc + IF :LNOT::DEF:CYFLD_CPUSS_DSI_NMI_PULSE__SIZE +CYFLD_CPUSS_DSI_NMI_PULSE__SIZE EQU 0x00000001 ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR7_BASE -CYDEV_DMAC_DESCR7_BASE EQU 0x401018e0 + IF :LNOT::DEF:CYREG_CPUSS_FLASH_CTL +CYREG_CPUSS_FLASH_CTL EQU 0x40100030 ENDIF - IF :LNOT::DEF:CYDEV_DMAC_DESCR7_SIZE -CYDEV_DMAC_DESCR7_SIZE EQU 0x00000020 + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WS__OFFSET +CYFLD_CPUSS_FLASH_WS__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_SRC -CYREG_DMAC_DESCR7_PING_SRC EQU 0x401018e0 + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_WS__SIZE +CYFLD_CPUSS_FLASH_WS__SIZE EQU 0x00000002 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_DST -CYREG_DMAC_DESCR7_PING_DST EQU 0x401018e4 + IF :LNOT::DEF:CYFLD_CPUSS_PREF_EN__OFFSET +CYFLD_CPUSS_PREF_EN__OFFSET EQU 0x00000004 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_CTL -CYREG_DMAC_DESCR7_PING_CTL EQU 0x401018e8 + IF :LNOT::DEF:CYFLD_CPUSS_PREF_EN__SIZE +CYFLD_CPUSS_PREF_EN__SIZE EQU 0x00000001 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PING_STATUS -CYREG_DMAC_DESCR7_PING_STATUS EQU 0x401018ec + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET +CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET EQU 0x00000008 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_SRC -CYREG_DMAC_DESCR7_PONG_SRC EQU 0x401018f0 + IF :LNOT::DEF:CYFLD_CPUSS_FLASH_INVALIDATE__SIZE +CYFLD_CPUSS_FLASH_INVALIDATE__SIZE EQU 0x00000001 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_DST -CYREG_DMAC_DESCR7_PONG_DST EQU 0x401018f4 + IF :LNOT::DEF:CYREG_CPUSS_ROM_CTL +CYREG_CPUSS_ROM_CTL EQU 0x40100034 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_CTL -CYREG_DMAC_DESCR7_PONG_CTL EQU 0x401018f8 + IF :LNOT::DEF:CYFLD_CPUSS_ROM_WS__OFFSET +CYFLD_CPUSS_ROM_WS__OFFSET EQU 0x00000000 ENDIF - IF :LNOT::DEF:CYREG_DMAC_DESCR7_PONG_STATUS -CYREG_DMAC_DESCR7_PONG_STATUS EQU 0x401018fc + IF :LNOT::DEF:CYFLD_CPUSS_ROM_WS__SIZE +CYFLD_CPUSS_ROM_WS__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYDEV_SPCIF_BASE CYDEV_SPCIF_BASE EQU 0x40110000 @@ -24204,87 +21993,12 @@ CYFLD_BLE_BLERD_ADC_4__OFFSET EQU 0x00000000 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLERD_ADC_4__SIZE CYFLD_BLE_BLERD_ADC_4__SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLERD_AGC_GAIN_COMP_1 -CYREG_BLE_BLERD_AGC_GAIN_COMP_1 EQU 0x402e0180 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_5__OFFSET -CYFLD_BLE_BLERD_GAIN_5__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_5__SIZE -CYFLD_BLE_BLERD_GAIN_5__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_4__OFFSET -CYFLD_BLE_BLERD_GAIN_4__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_4__SIZE -CYFLD_BLE_BLERD_GAIN_4__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_3__OFFSET -CYFLD_BLE_BLERD_GAIN_3__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_3__SIZE -CYFLD_BLE_BLERD_GAIN_3__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLERD_AGC_GAIN_COMP_2 -CYREG_BLE_BLERD_AGC_GAIN_COMP_2 EQU 0x402e0184 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_2__OFFSET -CYFLD_BLE_BLERD_GAIN_2__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_2__SIZE -CYFLD_BLE_BLERD_GAIN_2__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_1__OFFSET -CYFLD_BLE_BLERD_GAIN_1__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_1__SIZE -CYFLD_BLE_BLERD_GAIN_1__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_0__OFFSET -CYFLD_BLE_BLERD_GAIN_0__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_GAIN_0__SIZE -CYFLD_BLE_BLERD_GAIN_0__SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLERD_PA_RSSI_NEW -CYREG_BLE_BLERD_PA_RSSI_NEW EQU 0x402e0188 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_PA_RAMP_STEP__OFFSET -CYFLD_BLE_BLERD_PA_RAMP_STEP__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_PA_RAMP_STEP__SIZE -CYFLD_BLE_BLERD_PA_RAMP_STEP__SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_PA_RAMP_NEW__OFFSET -CYFLD_BLE_BLERD_PA_RAMP_NEW__OFFSET EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_PA_RAMP_NEW__SIZE -CYFLD_BLE_BLERD_PA_RAMP_NEW__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_MIN_RSSI_NEW__OFFSET -CYFLD_BLE_BLERD_MIN_RSSI_NEW__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_MIN_RSSI_NEW__SIZE -CYFLD_BLE_BLERD_MIN_RSSI_NEW__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__OFFSET -CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE -CYFLD_BLE_BLERD_AGCDIS_RSSI_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__OFFSET -CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__SIZE -CYFLD_BLE_BLERD_DEMOD_DC_PARAM_NEW__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYDEV_BLE_BLELL_BASE CYDEV_BLE_BLELL_BASE EQU 0x402e1000 ENDIF IF :LNOT::DEF:CYDEV_BLE_BLELL_SIZE -CYDEV_BLE_BLELL_SIZE EQU 0x00003000 +CYDEV_BLE_BLELL_SIZE EQU 0x00001000 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_COMMAND_REGISTER CYREG_BLE_BLELL_COMMAND_REGISTER EQU 0x402e1000 @@ -24423,30 +22137,6 @@ CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__OFFSET EQU 0x0000000a ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__SIZE CYFLD_BLE_BLELL_ADV_LOW_DUTY_CYCLE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INITA_RPA_CHECK__OFFSET -CYFLD_BLE_BLELL_INITA_RPA_CHECK__OFFSET EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE -CYFLD_BLE_BLELL_INITA_RPA_CHECK__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET -CYFLD_BLE_BLELL_TX_ADDR_PRIV__OFFSET EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE -CYFLD_BLE_BLELL_TX_ADDR_PRIV__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__OFFSET -CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__OFFSET EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__SIZE -CYFLD_BLE_BLELL_ADV_RCV_IA_IN_PRIV__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET -CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE -CYFLD_BLE_BLELL_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET CYFLD_BLE_BLELL_RCV_TX_ADDR__OFFSET EQU 0x0000000f @@ -24519,30 +22209,6 @@ CYFLD_BLE_BLELL_ADV_ON__OFFSET EQU 0x00000008 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_ON__SIZE CYFLD_BLE_BLELL_ADV_ON__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__OFFSET -CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE -CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_UNMCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET -CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE -CYFLD_BLE_BLELL_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET -CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE -CYFLD_BLE_BLELL_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET -CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE -CYFLD_BLE_BLELL_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_ADV_NEXT_INSTANT CYREG_BLE_BLELL_ADV_NEXT_INSTANT EQU 0x402e1024 @@ -24591,30 +22257,6 @@ CYFLD_BLE_BLELL_DUP_FILT_EN__OFFSET EQU 0x00000005 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE CYFLD_BLE_BLELL_DUP_FILT_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__OFFSET -CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE -CYFLD_BLE_BLELL_DUP_FILT_CHK_ADV_DIR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET -CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE -CYFLD_BLE_BLELL_SCAN_RSP_ADVA_CHECK__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET -CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE -CYFLD_BLE_BLELL_SCAN_RCV_IA_IN_PRIV__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET -CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE -CYFLD_BLE_BLELL_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_SCAN_INTR CYREG_BLE_BLELL_SCAN_INTR EQU 0x402e1038 @@ -24648,42 +22290,12 @@ CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__OFFSET EQU 0x00000004 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE CYFLD_BLE_BLELL_SCAN_RSP_RX_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__OFFSET -CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__SIZE -CYFLD_BLE_BLELL_ADV_RX_PEER_RPA_UNMCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__OFFSET -CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__SIZE -CYFLD_BLE_BLELL_ADV_RX_SELF_RPA_UNMCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET -CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE -CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_ON__OFFSET CYFLD_BLE_BLELL_SCAN_ON__OFFSET EQU 0x00000008 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_SCAN_ON__SIZE CYFLD_BLE_BLELL_SCAN_ON__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET -CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE -CYFLD_BLE_BLELL_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET -CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE -CYFLD_BLE_BLELL_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_SCAN_NEXT_INSTANT CYREG_BLE_BLELL_SCAN_NEXT_INSTANT EQU 0x402e103c @@ -24726,12 +22338,6 @@ CYFLD_BLE_BLELL_INIT_FILT_POLICY__OFFSET EQU 0x00000003 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE CYFLD_BLE_BLELL_INIT_FILT_POLICY__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__OFFSET -CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE -CYFLD_BLE_BLELL_INIT_RCV_IA_IN_PRIV__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_INIT_INTR CYREG_BLE_BLELL_INIT_INTR EQU 0x402e1050 @@ -24759,36 +22365,6 @@ CYFLD_BLE_BLELL_MASTER_CONN_CREATED__OFFSET EQU 0x00000004 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE CYFLD_BLE_BLELL_MASTER_CONN_CREATED__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__OFFSET -CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__SIZE -CYFLD_BLE_BLELL_ADV_RX_SELF_ADDR_UNMCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__OFFSET -CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__SIZE -CYFLD_BLE_BLELL_ADV_RX_PEER_ADDR_UNMCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__OFFSET -CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE -CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET -CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE -CYFLD_BLE_BLELL_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET -CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE -CYFLD_BLE_BLELL_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_INIT_NEXT_INSTANT CYREG_BLE_BLELL_INIT_NEXT_INSTANT EQU 0x402e1054 @@ -25373,7 +22949,7 @@ CYFLD_BLE_BLELL_LLID__SIZE EQU 0x00000002 CYFLD_BLE_BLELL_DATA_LENGTH__OFFSET EQU 0x00000002 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_DATA_LENGTH__SIZE -CYFLD_BLE_BLELL_DATA_LENGTH__SIZE EQU 0x00000008 +CYFLD_BLE_BLELL_DATA_LENGTH__SIZE EQU 0x00000005 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1 EQU 0x402e1144 @@ -25440,15 +23016,6 @@ CYFLD_BLE_BLELL_RX_PACKET_COUNT__OFFSET EQU 0x00000000 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE CYFLD_BLE_BLELL_RX_PACKET_COUNT__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT -CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT EQU 0x402e1178 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET -CYFLD_BLE_BLELL_TEST_LENGTH_EXT__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_TEST_LENGTH_EXT__SIZE -CYFLD_BLE_BLELL_TEST_LENGTH_EXT__SIZE EQU 0x00000003 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_TXRX_HOP CYREG_BLE_BLELL_TXRX_HOP EQU 0x402e1188 @@ -25581,18 +23148,6 @@ CYFLD_BLE_BLELL_ADV_RAND_DISABLE__OFFSET EQU 0x00000008 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_RAND_DISABLE__SIZE CYFLD_BLE_BLELL_ADV_RAND_DISABLE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__OFFSET -CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE -CYFLD_BLE_BLELL_ADV_SCN_PEER_RPA_UNMCH_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__OFFSET -CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__SIZE -CYFLD_BLE_BLELL_ADV_CONN_PEER_RPA_UNMCH_EN__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__OFFSET CYFLD_BLE_BLELL_ADV_PKT_INTERVAL__OFFSET EQU 0x0000000b @@ -25632,30 +23187,6 @@ CYFLD_BLE_BLELL_SCN_RSP_RX_EN__OFFSET EQU 0x00000004 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE CYFLD_BLE_BLELL_SCN_RSP_RX_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET -CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE -CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET -CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE -CYFLD_BLE_BLELL_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET -CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE -CYFLD_BLE_BLELL_SCANA_TX_ADDR_NOT_SET_INTR_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET -CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE -CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET CYFLD_BLE_BLELL_BACKOFF_ENABLE__OFFSET EQU 0x0000000b @@ -25695,24 +23226,6 @@ CYFLD_BLE_BLELL_CONN_CREATED__OFFSET EQU 0x00000004 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_CONN_CREATED__SIZE CYFLD_BLE_BLELL_CONN_CREATED__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__OFFSET -CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE -CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__OFFSET -CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE -CYFLD_BLE_BLELL_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__OFFSET -CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE -CYFLD_BLE_BLELL_INITA_TX_ADDR_NOT_SET_INTR_EN__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__OFFSET CYFLD_BLE_BLELL_INIT_CHANNEL_MAP__OFFSET EQU 0x0000000d @@ -26346,18 +23859,6 @@ CYFLD_BLE_BLELL_DIRECTION__OFFSET EQU 0x00000007 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_DIRECTION__SIZE CYFLD_BLE_BLELL_DIRECTION__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__OFFSET -CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__SIZE -CYFLD_BLE_BLELL_PAYLOAD_LENGTH_MSB__SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__OFFSET -CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__OFFSET EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE -CYFLD_BLE_BLELL_MEM_LATENCY_HIDE__SIZE EQU 0x00000001 ENDIF IF :LNOT::DEF:CYREG_BLE_BLELL_ENC_CONFIG CYREG_BLE_BLELL_ENC_CONFIG EQU 0x402e1490 @@ -26580,279 +24081,6 @@ CYFLD_BLE_BLELL_TX_EN_DELAY__OFFSET EQU 0x00000008 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLELL_TX_EN_DELAY__SIZE CYFLD_BLE_BLELL_TX_EN_DELAY__SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_LL_CONTROL -CYREG_BLE_BLELL_LL_CONTROL EQU 0x402e1f00 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2__OFFSET -CYFLD_BLE_BLELL_PRIV_1_2__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2__SIZE -CYFLD_BLE_BLELL_PRIV_1_2__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DLE__OFFSET -CYFLD_BLE_BLELL_DLE__OFFSET EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DLE__SIZE -CYFLD_BLE_BLELL_DLE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_WL_READ_AS_MEM__OFFSET -CYFLD_BLE_BLELL_WL_READ_AS_MEM__OFFSET EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE -CYFLD_BLE_BLELL_WL_READ_AS_MEM__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__OFFSET -CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__OFFSET EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE -CYFLD_BLE_BLELL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__OFFSET -CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE -CYFLD_BLE_BLELL_HW_RSLV_LIST_FULL__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET -CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE -CYFLD_BLE_BLELL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET -CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE -CYFLD_BLE_BLELL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET -CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE -CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET -CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE -CYFLD_BLE_BLELL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET -CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE -CYFLD_BLE_BLELL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET -CYFLD_BLE_BLELL_PRIV_1_2_ADV__OFFSET EQU 0x0000000a - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE -CYFLD_BLE_BLELL_PRIV_1_2_ADV__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET -CYFLD_BLE_BLELL_PRIV_1_2_SCAN__OFFSET EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE -CYFLD_BLE_BLELL_PRIV_1_2_SCAN__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET -CYFLD_BLE_BLELL_PRIV_1_2_INIT__OFFSET EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE -CYFLD_BLE_BLELL_PRIV_1_2_INIT__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__OFFSET -CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__OFFSET EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE -CYFLD_BLE_BLELL_EN_CONN_RX_EN_MOD__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__OFFSET -CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__OFFSET EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE -CYFLD_BLE_BLELL_SLV_CONN_PEER_RPA_NOT_RSLVD__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__OFFSET -CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__OFFSET EQU 0x0000000f - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE -CYFLD_BLE_BLELL_ADVCH_FIFO_FLUSH__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_DEV_PA_ADDR_L -CYREG_BLE_BLELL_DEV_PA_ADDR_L EQU 0x402e1f04 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DEV_PA_ADDR_L__OFFSET -CYFLD_BLE_BLELL_DEV_PA_ADDR_L__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DEV_PA_ADDR_L__SIZE -CYFLD_BLE_BLELL_DEV_PA_ADDR_L__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_DEV_PA_ADDR_M -CYREG_BLE_BLELL_DEV_PA_ADDR_M EQU 0x402e1f08 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DEV_PA_ADDR_M__OFFSET -CYFLD_BLE_BLELL_DEV_PA_ADDR_M__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DEV_PA_ADDR_M__SIZE -CYFLD_BLE_BLELL_DEV_PA_ADDR_M__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_DEV_PA_ADDR_H -CYREG_BLE_BLELL_DEV_PA_ADDR_H EQU 0x402e1f0c - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DEV_PA_ADDR_H__OFFSET -CYFLD_BLE_BLELL_DEV_PA_ADDR_H__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_DEV_PA_ADDR_H__SIZE -CYFLD_BLE_BLELL_DEV_PA_ADDR_H__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 EQU 0x402e1f10 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_VALID_ENTRY__OFFSET -CYFLD_BLE_BLELL_VALID_ENTRY__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_VALID_ENTRY__SIZE -CYFLD_BLE_BLELL_VALID_ENTRY__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET -CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__OFFSET EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE -CYFLD_BLE_BLELL_PEER_ADDR_IRK_SET__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET -CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__OFFSET EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE -CYFLD_BLE_BLELL_SELF_ADDR_IRK_SET_RX__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_WHITELISTED_PEER__OFFSET -CYFLD_BLE_BLELL_WHITELISTED_PEER__OFFSET EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE -CYFLD_BLE_BLELL_WHITELISTED_PEER__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET -CYFLD_BLE_BLELL_PEER_ADDR_TYPE__OFFSET EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE -CYFLD_BLE_BLELL_PEER_ADDR_TYPE__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET -CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__OFFSET EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE -CYFLD_BLE_BLELL_PEER_ADDR_RPA_VAL__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET -CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__OFFSET EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE -CYFLD_BLE_BLELL_SELF_ADDR_RXD_RPA_VAL__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET -CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__OFFSET EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE -CYFLD_BLE_BLELL_SELF_ADDR_TX_RPA_VAL__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET -CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__OFFSET EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE -CYFLD_BLE_BLELL_SELF_ADDR_INIT_RPA_SEL__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET -CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__OFFSET EQU 0x00000009 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE -CYFLD_BLE_BLELL_SELF_ADDR_TYPE_TX__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 EQU 0x402e1f14 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 EQU 0x402e1f18 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 EQU 0x402e1f1c - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 EQU 0x402e1f20 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 EQU 0x402e1f24 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 EQU 0x402e1f28 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 -CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 EQU 0x402e1f2c - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR -CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR EQU 0x402e2000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET -CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE -CYFLD_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR -CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR EQU 0x402e2060 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET -CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE -CYFLD_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR -CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR EQU 0x402e20c0 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET -CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE -CYFLD_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR -CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR EQU 0x402e2120 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET -CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE -CYFLD_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR -CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR EQU 0x402e2200 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET -CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__SIZE -CYFLD_BLE_BLELL_ENC_MEM_BASE_ADDR__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE -CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE EQU 0x402e2800 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__OFFSET -CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__SIZE -CYFLD_BLE_BLELL_CONN_RX_MEM_BASE_ADDR_DLE__SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE -CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE EQU 0x402e3000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__OFFSET -CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__OFFSET EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__SIZE -CYFLD_BLE_BLELL_CONN_TX_MEM_BASE_ADDR_DLE__SIZE EQU 0x00000010 ENDIF IF :LNOT::DEF:CYDEV_BLE_BLESS_BASE CYDEV_BLE_BLESS_BASE EQU 0x402ef000 @@ -27021,12 +24249,6 @@ CYFLD_BLE_BLESS_DISABLE_LF_CLK__OFFSET EQU 0x00000000 ENDIF IF :LNOT::DEF:CYFLD_BLE_BLESS_DISABLE_LF_CLK__SIZE CYFLD_BLE_BLESS_DISABLE_LF_CLK__SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__OFFSET -CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__OFFSET EQU 0x0000001d - ENDIF - IF :LNOT::DEF:CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__SIZE -CYFLD_BLE_BLESS_M0S8BLESS_REV_ID__SIZE EQU 0x00000003 ENDIF IF :LNOT::DEF:CYREG_BLE_BLESS_WCO_TRIM CYREG_BLE_BLESS_WCO_TRIM EQU 0x402eff00 @@ -29714,10 +26936,10 @@ CYREG_ROMTABLE_CID2 EQU 0xf0000ff8 CYREG_ROMTABLE_CID3 EQU 0xf0000ffc ENDIF IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE -CYDEV_FLS_SECTOR_SIZE EQU 0x00020000 +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 ENDIF IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE -CYDEV_FLS_ROW_SIZE EQU 0x00000100 +CYDEV_FLS_ROW_SIZE EQU 0x00000080 ENDIF IF :LNOT::DEF:CYREG_SFLASH_PROT_ROW00 CYREG_SFLASH_PROT_ROW00 EQU CYREG_SFLASH_PROT_ROW0 diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyfitter.h b/BLE.cydsn/Generated_Source/PSoC4/cyfitter.h index f845491..17e2b7b 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyfitter.h +++ b/BLE.cydsn/Generated_Source/PSoC4/cyfitter.h @@ -39,8 +39,6 @@ #define BLE_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO #define BLE_cy_m0s8_ble__ADV_TX_DATA_FIFO CYREG_BLE_BLELL_ADV_TX_DATA_FIFO #define BLE_cy_m0s8_ble__AGC CYREG_BLE_BLERD_AGC -#define BLE_cy_m0s8_ble__AGC_GAIN_COMP_1 CYREG_BLE_BLERD_AGC_GAIN_COMP_1 -#define BLE_cy_m0s8_ble__AGC_GAIN_COMP_2 CYREG_BLE_BLERD_AGC_GAIN_COMP_2 #define BLE_cy_m0s8_ble__BALUN CYREG_BLE_BLERD_BALUN #define BLE_cy_m0s8_ble__BB_BUMP1 CYREG_BLE_BLERD_BB_BUMP1 #define BLE_cy_m0s8_ble__BB_BUMP2 CYREG_BLE_BLERD_BB_BUMP2 @@ -82,10 +80,8 @@ #define BLE_cy_m0s8_ble__CONN_REQ_WORD8 CYREG_BLE_BLELL_CONN_REQ_WORD8 #define BLE_cy_m0s8_ble__CONN_REQ_WORD9 CYREG_BLE_BLELL_CONN_REQ_WORD9 #define BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR -#define BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR_DLE CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE #define BLE_cy_m0s8_ble__CONN_STATUS CYREG_BLE_BLELL_CONN_STATUS #define BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR -#define BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR_DLE CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE #define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL #define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY #define BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL @@ -125,9 +121,6 @@ #define BLE_cy_m0s8_ble__DBUS CYREG_BLE_BLERD_DBUS #define BLE_cy_m0s8_ble__DC CYREG_BLE_BLERD_DC #define BLE_cy_m0s8_ble__DCCAL CYREG_BLE_BLERD_DCCAL -#define BLE_cy_m0s8_ble__DEV_PA_ADDR_H CYREG_BLE_BLELL_DEV_PA_ADDR_H -#define BLE_cy_m0s8_ble__DEV_PA_ADDR_L CYREG_BLE_BLELL_DEV_PA_ADDR_L -#define BLE_cy_m0s8_ble__DEV_PA_ADDR_M CYREG_BLE_BLELL_DEV_PA_ADDR_M #define BLE_cy_m0s8_ble__DEV_PUB_ADDR_H CYREG_BLE_BLELL_DEV_PUB_ADDR_H #define BLE_cy_m0s8_ble__DEV_PUB_ADDR_L CYREG_BLE_BLELL_DEV_PUB_ADDR_L #define BLE_cy_m0s8_ble__DEV_PUB_ADDR_M CYREG_BLE_BLELL_DEV_PUB_ADDR_M @@ -154,7 +147,6 @@ #define BLE_cy_m0s8_ble__ENC_KEY5 CYREG_BLE_BLELL_ENC_KEY5 #define BLE_cy_m0s8_ble__ENC_KEY6 CYREG_BLE_BLELL_ENC_KEY6 #define BLE_cy_m0s8_ble__ENC_KEY7 CYREG_BLE_BLELL_ENC_KEY7 -#define BLE_cy_m0s8_ble__ENC_MEM_BASE_ADDR CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR #define BLE_cy_m0s8_ble__ENC_PARAMS CYREG_BLE_BLELL_ENC_PARAMS #define BLE_cy_m0s8_ble__EVENT_ENABLE CYREG_BLE_BLELL_EVENT_ENABLE #define BLE_cy_m0s8_ble__EVENT_INTR CYREG_BLE_BLELL_EVENT_INTR @@ -182,10 +174,8 @@ #define BLE_cy_m0s8_ble__LE_PING_TIMER_OFFSET CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET #define BLE_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT #define BLE_cy_m0s8_ble__LE_RF_TEST_MODE CYREG_BLE_BLELL_LE_RF_TEST_MODE -#define BLE_cy_m0s8_ble__LE_RF_TEST_MODE_EXT CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT #define BLE_cy_m0s8_ble__LF_CLK_CTRL CYREG_BLE_BLESS_LF_CLK_CTRL #define BLE_cy_m0s8_ble__LL_CLK_EN CYREG_BLE_BLESS_LL_CLK_EN -#define BLE_cy_m0s8_ble__LL_CONTROL CYREG_BLE_BLELL_LL_CONTROL #define BLE_cy_m0s8_ble__LL_DSM_CTRL CYREG_BLE_BLESS_LL_DSM_CTRL #define BLE_cy_m0s8_ble__LL_DSM_INTR_STAT CYREG_BLE_BLESS_LL_DSM_INTR_STAT #define BLE_cy_m0s8_ble__LLH_FEATURE_CONFIG CYREG_BLE_BLELL_LLH_FEATURE_CONFIG @@ -199,7 +189,6 @@ #define BLE_cy_m0s8_ble__NEXT_RESP_TIMER_EXP CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP #define BLE_cy_m0s8_ble__NEXT_SUP_TO CYREG_BLE_BLELL_NEXT_SUP_TO #define BLE_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT -#define BLE_cy_m0s8_ble__PA_RSSI_NEW CYREG_BLE_BLERD_PA_RSSI_NEW #define BLE_cy_m0s8_ble__PACKET_COUNTER0 CYREG_BLE_BLELL_PACKET_COUNTER0 #define BLE_cy_m0s8_ble__PACKET_COUNTER1 CYREG_BLE_BLELL_PACKET_COUNTER1 #define BLE_cy_m0s8_ble__PACKET_COUNTER2 CYREG_BLE_BLELL_PACKET_COUNTER2 @@ -218,18 +207,6 @@ #define BLE_cy_m0s8_ble__RECEIVE_TRIG_CTRL CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL #define BLE_cy_m0s8_ble__RF_CONFIG CYREG_BLE_BLESS_RF_CONFIG #define BLE_cy_m0s8_ble__RMAP CYREG_BLE_BLERD_RMAP -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE0 CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE1 CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE2 CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE3 CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE4 CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE5 CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE6 CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 -#define BLE_cy_m0s8_ble__RSLV_LIST_ENABLE7 CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 -#define BLE_cy_m0s8_ble__RSLV_LIST_PEER_IDNTT_BASE_ADDR CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR -#define BLE_cy_m0s8_ble__RSLV_LIST_PEER_RPA_BASE_ADDR CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR -#define BLE_cy_m0s8_ble__RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR -#define BLE_cy_m0s8_ble__RSLV_LIST_TX_INIT_RPA_BASE_ADDR CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR #define BLE_cy_m0s8_ble__RSSI CYREG_BLE_BLERD_RSSI #define BLE_cy_m0s8_ble__RX CYREG_BLE_BLERD_RX #define BLE_cy_m0s8_ble__RX_BUMP1 CYREG_BLE_BLERD_RX_BUMP1 @@ -509,257 +486,68 @@ #define SCB_sda__SHIFT 4u /* SW2 */ -#define SW2__0__DR CYREG_GPIO_PRT2_DR -#define SW2__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR -#define SW2__0__DR_INV CYREG_GPIO_PRT2_DR_INV -#define SW2__0__DR_SET CYREG_GPIO_PRT2_DR_SET -#define SW2__0__HSIOM CYREG_HSIOM_PORT_SEL2 -#define SW2__0__HSIOM_MASK 0xF0000000u -#define SW2__0__HSIOM_SHIFT 28u -#define SW2__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG -#define SW2__0__INTR CYREG_GPIO_PRT2_INTR -#define SW2__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG -#define SW2__0__INTSTAT CYREG_GPIO_PRT2_INTR -#define SW2__0__MASK 0x80u -#define SW2__0__PA__CFG0 CYREG_UDB_PA2_CFG0 -#define SW2__0__PA__CFG1 CYREG_UDB_PA2_CFG1 -#define SW2__0__PA__CFG10 CYREG_UDB_PA2_CFG10 -#define SW2__0__PA__CFG11 CYREG_UDB_PA2_CFG11 -#define SW2__0__PA__CFG12 CYREG_UDB_PA2_CFG12 -#define SW2__0__PA__CFG13 CYREG_UDB_PA2_CFG13 -#define SW2__0__PA__CFG14 CYREG_UDB_PA2_CFG14 -#define SW2__0__PA__CFG2 CYREG_UDB_PA2_CFG2 -#define SW2__0__PA__CFG3 CYREG_UDB_PA2_CFG3 -#define SW2__0__PA__CFG4 CYREG_UDB_PA2_CFG4 -#define SW2__0__PA__CFG5 CYREG_UDB_PA2_CFG5 -#define SW2__0__PA__CFG6 CYREG_UDB_PA2_CFG6 -#define SW2__0__PA__CFG7 CYREG_UDB_PA2_CFG7 -#define SW2__0__PA__CFG8 CYREG_UDB_PA2_CFG8 -#define SW2__0__PA__CFG9 CYREG_UDB_PA2_CFG9 -#define SW2__0__PC CYREG_GPIO_PRT2_PC -#define SW2__0__PC2 CYREG_GPIO_PRT2_PC2 -#define SW2__0__PORT 2u -#define SW2__0__PS CYREG_GPIO_PRT2_PS -#define SW2__0__SHIFT 7u -#define SW2__DR CYREG_GPIO_PRT2_DR -#define SW2__DR_CLR CYREG_GPIO_PRT2_DR_CLR -#define SW2__DR_INV CYREG_GPIO_PRT2_DR_INV -#define SW2__DR_SET CYREG_GPIO_PRT2_DR_SET -#define SW2__INTCFG CYREG_GPIO_PRT2_INTR_CFG -#define SW2__INTR CYREG_GPIO_PRT2_INTR -#define SW2__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG -#define SW2__INTSTAT CYREG_GPIO_PRT2_INTR -#define SW2__MASK 0x80u -#define SW2__PA__CFG0 CYREG_UDB_PA2_CFG0 -#define SW2__PA__CFG1 CYREG_UDB_PA2_CFG1 -#define SW2__PA__CFG10 CYREG_UDB_PA2_CFG10 -#define SW2__PA__CFG11 CYREG_UDB_PA2_CFG11 -#define SW2__PA__CFG12 CYREG_UDB_PA2_CFG12 -#define SW2__PA__CFG13 CYREG_UDB_PA2_CFG13 -#define SW2__PA__CFG14 CYREG_UDB_PA2_CFG14 -#define SW2__PA__CFG2 CYREG_UDB_PA2_CFG2 -#define SW2__PA__CFG3 CYREG_UDB_PA2_CFG3 -#define SW2__PA__CFG4 CYREG_UDB_PA2_CFG4 -#define SW2__PA__CFG5 CYREG_UDB_PA2_CFG5 -#define SW2__PA__CFG6 CYREG_UDB_PA2_CFG6 -#define SW2__PA__CFG7 CYREG_UDB_PA2_CFG7 -#define SW2__PA__CFG8 CYREG_UDB_PA2_CFG8 -#define SW2__PA__CFG9 CYREG_UDB_PA2_CFG9 -#define SW2__PC CYREG_GPIO_PRT2_PC -#define SW2__PC2 CYREG_GPIO_PRT2_PC2 -#define SW2__PORT 2u -#define SW2__PS CYREG_GPIO_PRT2_PS -#define SW2__SHIFT 7u -#define SW2__SNAP CYREG_GPIO_PRT2_INTR - -/* LED_BLU */ -#define LED_BLU__0__DR CYREG_GPIO_PRT3_DR -#define LED_BLU__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR -#define LED_BLU__0__DR_INV CYREG_GPIO_PRT3_DR_INV -#define LED_BLU__0__DR_SET CYREG_GPIO_PRT3_DR_SET -#define LED_BLU__0__HSIOM CYREG_HSIOM_PORT_SEL3 -#define LED_BLU__0__HSIOM_MASK 0xF0000000u -#define LED_BLU__0__HSIOM_SHIFT 28u -#define LED_BLU__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_BLU__0__INTR CYREG_GPIO_PRT3_INTR -#define LED_BLU__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_BLU__0__INTSTAT CYREG_GPIO_PRT3_INTR -#define LED_BLU__0__MASK 0x80u -#define LED_BLU__0__PA__CFG0 CYREG_UDB_PA3_CFG0 -#define LED_BLU__0__PA__CFG1 CYREG_UDB_PA3_CFG1 -#define LED_BLU__0__PA__CFG10 CYREG_UDB_PA3_CFG10 -#define LED_BLU__0__PA__CFG11 CYREG_UDB_PA3_CFG11 -#define LED_BLU__0__PA__CFG12 CYREG_UDB_PA3_CFG12 -#define LED_BLU__0__PA__CFG13 CYREG_UDB_PA3_CFG13 -#define LED_BLU__0__PA__CFG14 CYREG_UDB_PA3_CFG14 -#define LED_BLU__0__PA__CFG2 CYREG_UDB_PA3_CFG2 -#define LED_BLU__0__PA__CFG3 CYREG_UDB_PA3_CFG3 -#define LED_BLU__0__PA__CFG4 CYREG_UDB_PA3_CFG4 -#define LED_BLU__0__PA__CFG5 CYREG_UDB_PA3_CFG5 -#define LED_BLU__0__PA__CFG6 CYREG_UDB_PA3_CFG6 -#define LED_BLU__0__PA__CFG7 CYREG_UDB_PA3_CFG7 -#define LED_BLU__0__PA__CFG8 CYREG_UDB_PA3_CFG8 -#define LED_BLU__0__PA__CFG9 CYREG_UDB_PA3_CFG9 -#define LED_BLU__0__PC CYREG_GPIO_PRT3_PC -#define LED_BLU__0__PC2 CYREG_GPIO_PRT3_PC2 -#define LED_BLU__0__PORT 3u -#define LED_BLU__0__PS CYREG_GPIO_PRT3_PS -#define LED_BLU__0__SHIFT 7u -#define LED_BLU__DR CYREG_GPIO_PRT3_DR -#define LED_BLU__DR_CLR CYREG_GPIO_PRT3_DR_CLR -#define LED_BLU__DR_INV CYREG_GPIO_PRT3_DR_INV -#define LED_BLU__DR_SET CYREG_GPIO_PRT3_DR_SET -#define LED_BLU__INTCFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_BLU__INTR CYREG_GPIO_PRT3_INTR -#define LED_BLU__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_BLU__INTSTAT CYREG_GPIO_PRT3_INTR -#define LED_BLU__MASK 0x80u -#define LED_BLU__PA__CFG0 CYREG_UDB_PA3_CFG0 -#define LED_BLU__PA__CFG1 CYREG_UDB_PA3_CFG1 -#define LED_BLU__PA__CFG10 CYREG_UDB_PA3_CFG10 -#define LED_BLU__PA__CFG11 CYREG_UDB_PA3_CFG11 -#define LED_BLU__PA__CFG12 CYREG_UDB_PA3_CFG12 -#define LED_BLU__PA__CFG13 CYREG_UDB_PA3_CFG13 -#define LED_BLU__PA__CFG14 CYREG_UDB_PA3_CFG14 -#define LED_BLU__PA__CFG2 CYREG_UDB_PA3_CFG2 -#define LED_BLU__PA__CFG3 CYREG_UDB_PA3_CFG3 -#define LED_BLU__PA__CFG4 CYREG_UDB_PA3_CFG4 -#define LED_BLU__PA__CFG5 CYREG_UDB_PA3_CFG5 -#define LED_BLU__PA__CFG6 CYREG_UDB_PA3_CFG6 -#define LED_BLU__PA__CFG7 CYREG_UDB_PA3_CFG7 -#define LED_BLU__PA__CFG8 CYREG_UDB_PA3_CFG8 -#define LED_BLU__PA__CFG9 CYREG_UDB_PA3_CFG9 -#define LED_BLU__PC CYREG_GPIO_PRT3_PC -#define LED_BLU__PC2 CYREG_GPIO_PRT3_PC2 -#define LED_BLU__PORT 3u -#define LED_BLU__PS CYREG_GPIO_PRT3_PS -#define LED_BLU__SHIFT 7u - -/* LED_GRN */ -#define LED_GRN__0__DR CYREG_GPIO_PRT3_DR -#define LED_GRN__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR -#define LED_GRN__0__DR_INV CYREG_GPIO_PRT3_DR_INV -#define LED_GRN__0__DR_SET CYREG_GPIO_PRT3_DR_SET -#define LED_GRN__0__HSIOM CYREG_HSIOM_PORT_SEL3 -#define LED_GRN__0__HSIOM_MASK 0x0F000000u -#define LED_GRN__0__HSIOM_SHIFT 24u -#define LED_GRN__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_GRN__0__INTR CYREG_GPIO_PRT3_INTR -#define LED_GRN__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_GRN__0__INTSTAT CYREG_GPIO_PRT3_INTR -#define LED_GRN__0__MASK 0x40u -#define LED_GRN__0__PA__CFG0 CYREG_UDB_PA3_CFG0 -#define LED_GRN__0__PA__CFG1 CYREG_UDB_PA3_CFG1 -#define LED_GRN__0__PA__CFG10 CYREG_UDB_PA3_CFG10 -#define LED_GRN__0__PA__CFG11 CYREG_UDB_PA3_CFG11 -#define LED_GRN__0__PA__CFG12 CYREG_UDB_PA3_CFG12 -#define LED_GRN__0__PA__CFG13 CYREG_UDB_PA3_CFG13 -#define LED_GRN__0__PA__CFG14 CYREG_UDB_PA3_CFG14 -#define LED_GRN__0__PA__CFG2 CYREG_UDB_PA3_CFG2 -#define LED_GRN__0__PA__CFG3 CYREG_UDB_PA3_CFG3 -#define LED_GRN__0__PA__CFG4 CYREG_UDB_PA3_CFG4 -#define LED_GRN__0__PA__CFG5 CYREG_UDB_PA3_CFG5 -#define LED_GRN__0__PA__CFG6 CYREG_UDB_PA3_CFG6 -#define LED_GRN__0__PA__CFG7 CYREG_UDB_PA3_CFG7 -#define LED_GRN__0__PA__CFG8 CYREG_UDB_PA3_CFG8 -#define LED_GRN__0__PA__CFG9 CYREG_UDB_PA3_CFG9 -#define LED_GRN__0__PC CYREG_GPIO_PRT3_PC -#define LED_GRN__0__PC2 CYREG_GPIO_PRT3_PC2 -#define LED_GRN__0__PORT 3u -#define LED_GRN__0__PS CYREG_GPIO_PRT3_PS -#define LED_GRN__0__SHIFT 6u -#define LED_GRN__DR CYREG_GPIO_PRT3_DR -#define LED_GRN__DR_CLR CYREG_GPIO_PRT3_DR_CLR -#define LED_GRN__DR_INV CYREG_GPIO_PRT3_DR_INV -#define LED_GRN__DR_SET CYREG_GPIO_PRT3_DR_SET -#define LED_GRN__INTCFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_GRN__INTR CYREG_GPIO_PRT3_INTR -#define LED_GRN__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG -#define LED_GRN__INTSTAT CYREG_GPIO_PRT3_INTR -#define LED_GRN__MASK 0x40u -#define LED_GRN__PA__CFG0 CYREG_UDB_PA3_CFG0 -#define LED_GRN__PA__CFG1 CYREG_UDB_PA3_CFG1 -#define LED_GRN__PA__CFG10 CYREG_UDB_PA3_CFG10 -#define LED_GRN__PA__CFG11 CYREG_UDB_PA3_CFG11 -#define LED_GRN__PA__CFG12 CYREG_UDB_PA3_CFG12 -#define LED_GRN__PA__CFG13 CYREG_UDB_PA3_CFG13 -#define LED_GRN__PA__CFG14 CYREG_UDB_PA3_CFG14 -#define LED_GRN__PA__CFG2 CYREG_UDB_PA3_CFG2 -#define LED_GRN__PA__CFG3 CYREG_UDB_PA3_CFG3 -#define LED_GRN__PA__CFG4 CYREG_UDB_PA3_CFG4 -#define LED_GRN__PA__CFG5 CYREG_UDB_PA3_CFG5 -#define LED_GRN__PA__CFG6 CYREG_UDB_PA3_CFG6 -#define LED_GRN__PA__CFG7 CYREG_UDB_PA3_CFG7 -#define LED_GRN__PA__CFG8 CYREG_UDB_PA3_CFG8 -#define LED_GRN__PA__CFG9 CYREG_UDB_PA3_CFG9 -#define LED_GRN__PC CYREG_GPIO_PRT3_PC -#define LED_GRN__PC2 CYREG_GPIO_PRT3_PC2 -#define LED_GRN__PORT 3u -#define LED_GRN__PS CYREG_GPIO_PRT3_PS -#define LED_GRN__SHIFT 6u - -/* LED_RED */ -#define LED_RED__0__DR CYREG_GPIO_PRT2_DR -#define LED_RED__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR -#define LED_RED__0__DR_INV CYREG_GPIO_PRT2_DR_INV -#define LED_RED__0__DR_SET CYREG_GPIO_PRT2_DR_SET -#define LED_RED__0__HSIOM CYREG_HSIOM_PORT_SEL2 -#define LED_RED__0__HSIOM_MASK 0x0F000000u -#define LED_RED__0__HSIOM_SHIFT 24u -#define LED_RED__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG -#define LED_RED__0__INTR CYREG_GPIO_PRT2_INTR -#define LED_RED__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG -#define LED_RED__0__INTSTAT CYREG_GPIO_PRT2_INTR -#define LED_RED__0__MASK 0x40u -#define LED_RED__0__PA__CFG0 CYREG_UDB_PA2_CFG0 -#define LED_RED__0__PA__CFG1 CYREG_UDB_PA2_CFG1 -#define LED_RED__0__PA__CFG10 CYREG_UDB_PA2_CFG10 -#define LED_RED__0__PA__CFG11 CYREG_UDB_PA2_CFG11 -#define LED_RED__0__PA__CFG12 CYREG_UDB_PA2_CFG12 -#define LED_RED__0__PA__CFG13 CYREG_UDB_PA2_CFG13 -#define LED_RED__0__PA__CFG14 CYREG_UDB_PA2_CFG14 -#define LED_RED__0__PA__CFG2 CYREG_UDB_PA2_CFG2 -#define LED_RED__0__PA__CFG3 CYREG_UDB_PA2_CFG3 -#define LED_RED__0__PA__CFG4 CYREG_UDB_PA2_CFG4 -#define LED_RED__0__PA__CFG5 CYREG_UDB_PA2_CFG5 -#define LED_RED__0__PA__CFG6 CYREG_UDB_PA2_CFG6 -#define LED_RED__0__PA__CFG7 CYREG_UDB_PA2_CFG7 -#define LED_RED__0__PA__CFG8 CYREG_UDB_PA2_CFG8 -#define LED_RED__0__PA__CFG9 CYREG_UDB_PA2_CFG9 -#define LED_RED__0__PC CYREG_GPIO_PRT2_PC -#define LED_RED__0__PC2 CYREG_GPIO_PRT2_PC2 -#define LED_RED__0__PORT 2u -#define LED_RED__0__PS CYREG_GPIO_PRT2_PS -#define LED_RED__0__SHIFT 6u -#define LED_RED__DR CYREG_GPIO_PRT2_DR -#define LED_RED__DR_CLR CYREG_GPIO_PRT2_DR_CLR -#define LED_RED__DR_INV CYREG_GPIO_PRT2_DR_INV -#define LED_RED__DR_SET CYREG_GPIO_PRT2_DR_SET -#define LED_RED__INTCFG CYREG_GPIO_PRT2_INTR_CFG -#define LED_RED__INTR CYREG_GPIO_PRT2_INTR -#define LED_RED__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG -#define LED_RED__INTSTAT CYREG_GPIO_PRT2_INTR -#define LED_RED__MASK 0x40u -#define LED_RED__PA__CFG0 CYREG_UDB_PA2_CFG0 -#define LED_RED__PA__CFG1 CYREG_UDB_PA2_CFG1 -#define LED_RED__PA__CFG10 CYREG_UDB_PA2_CFG10 -#define LED_RED__PA__CFG11 CYREG_UDB_PA2_CFG11 -#define LED_RED__PA__CFG12 CYREG_UDB_PA2_CFG12 -#define LED_RED__PA__CFG13 CYREG_UDB_PA2_CFG13 -#define LED_RED__PA__CFG14 CYREG_UDB_PA2_CFG14 -#define LED_RED__PA__CFG2 CYREG_UDB_PA2_CFG2 -#define LED_RED__PA__CFG3 CYREG_UDB_PA2_CFG3 -#define LED_RED__PA__CFG4 CYREG_UDB_PA2_CFG4 -#define LED_RED__PA__CFG5 CYREG_UDB_PA2_CFG5 -#define LED_RED__PA__CFG6 CYREG_UDB_PA2_CFG6 -#define LED_RED__PA__CFG7 CYREG_UDB_PA2_CFG7 -#define LED_RED__PA__CFG8 CYREG_UDB_PA2_CFG8 -#define LED_RED__PA__CFG9 CYREG_UDB_PA2_CFG9 -#define LED_RED__PC CYREG_GPIO_PRT2_PC -#define LED_RED__PC2 CYREG_GPIO_PRT2_PC2 -#define LED_RED__PORT 2u -#define LED_RED__PS CYREG_GPIO_PRT2_PS -#define LED_RED__SHIFT 6u +#define SW2__0__DR CYREG_GPIO_PRT0_DR +#define SW2__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR +#define SW2__0__DR_INV CYREG_GPIO_PRT0_DR_INV +#define SW2__0__DR_SET CYREG_GPIO_PRT0_DR_SET +#define SW2__0__HSIOM CYREG_HSIOM_PORT_SEL0 +#define SW2__0__HSIOM_MASK 0x000000F0u +#define SW2__0__HSIOM_SHIFT 4u +#define SW2__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG +#define SW2__0__INTR CYREG_GPIO_PRT0_INTR +#define SW2__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG +#define SW2__0__INTSTAT CYREG_GPIO_PRT0_INTR +#define SW2__0__MASK 0x02u +#define SW2__0__PA__CFG0 CYREG_UDB_PA0_CFG0 +#define SW2__0__PA__CFG1 CYREG_UDB_PA0_CFG1 +#define SW2__0__PA__CFG10 CYREG_UDB_PA0_CFG10 +#define SW2__0__PA__CFG11 CYREG_UDB_PA0_CFG11 +#define SW2__0__PA__CFG12 CYREG_UDB_PA0_CFG12 +#define SW2__0__PA__CFG13 CYREG_UDB_PA0_CFG13 +#define SW2__0__PA__CFG14 CYREG_UDB_PA0_CFG14 +#define SW2__0__PA__CFG2 CYREG_UDB_PA0_CFG2 +#define SW2__0__PA__CFG3 CYREG_UDB_PA0_CFG3 +#define SW2__0__PA__CFG4 CYREG_UDB_PA0_CFG4 +#define SW2__0__PA__CFG5 CYREG_UDB_PA0_CFG5 +#define SW2__0__PA__CFG6 CYREG_UDB_PA0_CFG6 +#define SW2__0__PA__CFG7 CYREG_UDB_PA0_CFG7 +#define SW2__0__PA__CFG8 CYREG_UDB_PA0_CFG8 +#define SW2__0__PA__CFG9 CYREG_UDB_PA0_CFG9 +#define SW2__0__PC CYREG_GPIO_PRT0_PC +#define SW2__0__PC2 CYREG_GPIO_PRT0_PC2 +#define SW2__0__PORT 0u +#define SW2__0__PS CYREG_GPIO_PRT0_PS +#define SW2__0__SHIFT 1u +#define SW2__DR CYREG_GPIO_PRT0_DR +#define SW2__DR_CLR CYREG_GPIO_PRT0_DR_CLR +#define SW2__DR_INV CYREG_GPIO_PRT0_DR_INV +#define SW2__DR_SET CYREG_GPIO_PRT0_DR_SET +#define SW2__INTCFG CYREG_GPIO_PRT0_INTR_CFG +#define SW2__INTR CYREG_GPIO_PRT0_INTR +#define SW2__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG +#define SW2__INTSTAT CYREG_GPIO_PRT0_INTR +#define SW2__MASK 0x02u +#define SW2__PA__CFG0 CYREG_UDB_PA0_CFG0 +#define SW2__PA__CFG1 CYREG_UDB_PA0_CFG1 +#define SW2__PA__CFG10 CYREG_UDB_PA0_CFG10 +#define SW2__PA__CFG11 CYREG_UDB_PA0_CFG11 +#define SW2__PA__CFG12 CYREG_UDB_PA0_CFG12 +#define SW2__PA__CFG13 CYREG_UDB_PA0_CFG13 +#define SW2__PA__CFG14 CYREG_UDB_PA0_CFG14 +#define SW2__PA__CFG2 CYREG_UDB_PA0_CFG2 +#define SW2__PA__CFG3 CYREG_UDB_PA0_CFG3 +#define SW2__PA__CFG4 CYREG_UDB_PA0_CFG4 +#define SW2__PA__CFG5 CYREG_UDB_PA0_CFG5 +#define SW2__PA__CFG6 CYREG_UDB_PA0_CFG6 +#define SW2__PA__CFG7 CYREG_UDB_PA0_CFG7 +#define SW2__PA__CFG8 CYREG_UDB_PA0_CFG8 +#define SW2__PA__CFG9 CYREG_UDB_PA0_CFG9 +#define SW2__PC CYREG_GPIO_PRT0_PC +#define SW2__PC2 CYREG_GPIO_PRT0_PC2 +#define SW2__PORT 0u +#define SW2__PS CYREG_GPIO_PRT0_PS +#define SW2__SHIFT 1u +#define SW2__SNAP CYREG_GPIO_PRT0_INTR /* UART_DEB */ #define UART_DEB_rx__0__DR CYREG_GPIO_PRT1_DR @@ -992,9 +780,9 @@ /* Wakeup_Interrupt */ #define Wakeup_Interrupt__INTC_CLR_EN_REG CYREG_CM0_ICER #define Wakeup_Interrupt__INTC_CLR_PD_REG CYREG_CM0_ICPR -#define Wakeup_Interrupt__INTC_MASK 0x04u -#define Wakeup_Interrupt__INTC_NUMBER 2u -#define Wakeup_Interrupt__INTC_PRIOR_MASK 0xC00000u +#define Wakeup_Interrupt__INTC_MASK 0x01u +#define Wakeup_Interrupt__INTC_NUMBER 0u +#define Wakeup_Interrupt__INTC_PRIOR_MASK 0xC0u #define Wakeup_Interrupt__INTC_PRIOR_NUM 3u #define Wakeup_Interrupt__INTC_PRIOR_REG CYREG_CM0_IPR0 #define Wakeup_Interrupt__INTC_SET_EN_REG CYREG_CM0_ISER @@ -1025,7 +813,7 @@ #define CYDEV_CHIP_FAMILY_PSOC6 4u #define CYDEV_CHIP_FAMILY_UNKNOWN 0u #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4 -#define CYDEV_CHIP_JTAG_ID 0x1A1711AAu +#define CYDEV_CHIP_JTAG_ID 0x0E49119Eu #define CYDEV_CHIP_MEMBER_3A 1u #define CYDEV_CHIP_MEMBER_4A 18u #define CYDEV_CHIP_MEMBER_4D 13u @@ -1116,7 +904,7 @@ #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u -#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4F_PRODUCTION #define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED #define CYDEV_CONFIG_READ_ACCELERATOR 1 #define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 @@ -1138,11 +926,9 @@ #define CYDEV_DEBUGGING_ENABLE 1 #define CYDEV_DFT_SELECT_CLK0 10u #define CYDEV_DFT_SELECT_CLK1 11u -#define CYDEV_DMA_CHANNELS_AVAILABLE 8 #define CYDEV_HEAP_SIZE 0x400 #define CYDEV_IMO_TRIMMED_BY_USB 0u #define CYDEV_IMO_TRIMMED_BY_WCO 0u -#define CYDEV_INTR_NUMBER_DMA 21u #define CYDEV_IS_EXPORTING_CODE 0 #define CYDEV_IS_IMPORTING_CODE 0 #define CYDEV_PROJ_TYPE 0 @@ -1155,14 +941,14 @@ #define CYDEV_STACK_SIZE 0x0800 #define CYDEV_USE_BUNDLED_CMSIS 1 #define CYDEV_VARIABLE_VDDA 1 +#define CYDEV_VDD 3.3 +#define CYDEV_VDD_MV 3300 #define CYDEV_VDDA 3.3 #define CYDEV_VDDA_MV 3300 -#define CYDEV_VDDD 3.3 -#define CYDEV_VDDD_MV 3300 #define CYDEV_VDDR 3.3 #define CYDEV_VDDR_MV 3300 #define CYDEV_WDT_GENERATE_ISR 1u -#define CYIPBLOCK_m0s8bless_VERSION 2 +#define CYIPBLOCK_m0s8bless_VERSION 1 #define CYIPBLOCK_m0s8cpussv2_VERSION 1 #define CYIPBLOCK_m0s8csd_VERSION 1 #define CYIPBLOCK_m0s8ioss_VERSION 1 @@ -1174,7 +960,6 @@ #define CYIPBLOCK_m0s8tcpwm_VERSION 2 #define CYIPBLOCK_m0s8udbif_VERSION 1 #define CYIPBLOCK_s8pass4al_VERSION 1 -#define DMA_CHANNELS_USED__MASK 0u #define CYDEV_BOOTLOADER_ENABLE 0 #endif /* INCLUDED_CYFITTER_H */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c b/BLE.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c index 25e180d..cab2797 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c +++ b/BLE.cydsn/Generated_Source/PSoC4/cyfitter_cfg.c @@ -305,9 +305,6 @@ void cyfitter_cfg(void) /* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */ CY_SET_REG32((void *)(CYDEV_UDB_PA1_BASE), 0x00990000u); - /* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */ - CY_SET_REG32((void *)(CYDEV_UDB_PA2_BASE), 0x00990000u); - /* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */ CY_SET_REG32((void *)(CYDEV_UDB_PA3_BASE), 0x00990000u); @@ -317,21 +314,18 @@ void cyfitter_cfg(void) /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ /* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */ - CY_SET_REG32((void *)(CYREG_GPIO_PRT0_PC), 0x00D80000u); + CY_SET_REG32((void *)(CYDEV_GPIO_PRT0_BASE), 0x00000002u); + CY_SET_REG32((void *)(CYREG_GPIO_PRT0_PC), 0x00D80010u); + CY_SET_REG32((void *)(CYREG_GPIO_PRT0_INTR_CFG), 0x00000008u); /* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */ CY_SET_REG32((void *)(CYDEV_GPIO_PRT1_BASE), 0x00000020u); CY_SET_REG32((void *)(CYREG_GPIO_PRT1_PC), 0x00031000u); CY_SET_REG32((void *)(CYREG_GPIO_PRT1_PC2), 0x00000020u); - /* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */ - CY_SET_REG32((void *)(CYDEV_GPIO_PRT2_BASE), 0x000000C0u); - CY_SET_REG32((void *)(CYREG_GPIO_PRT2_PC), 0x00580000u); - CY_SET_REG32((void *)(CYREG_GPIO_PRT2_INTR_CFG), 0x00008000u); - /* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */ - CY_SET_REG32((void *)(CYDEV_GPIO_PRT3_BASE), 0x000000F0u); - CY_SET_REG32((void *)(CYREG_GPIO_PRT3_PC), 0x00DA4000u); + CY_SET_REG32((void *)(CYDEV_GPIO_PRT3_BASE), 0x00000030u); + CY_SET_REG32((void *)(CYREG_GPIO_PRT3_PC), 0x00024000u); /* Setup clocks based on selections from Clock DWR */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyfittergnu.inc b/BLE.cydsn/Generated_Source/PSoC4/cyfittergnu.inc index f593d70..63710c9 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyfittergnu.inc +++ b/BLE.cydsn/Generated_Source/PSoC4/cyfittergnu.inc @@ -39,8 +39,6 @@ .set BLE_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO, CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO .set BLE_cy_m0s8_ble__ADV_TX_DATA_FIFO, CYREG_BLE_BLELL_ADV_TX_DATA_FIFO .set BLE_cy_m0s8_ble__AGC, CYREG_BLE_BLERD_AGC -.set BLE_cy_m0s8_ble__AGC_GAIN_COMP_1, CYREG_BLE_BLERD_AGC_GAIN_COMP_1 -.set BLE_cy_m0s8_ble__AGC_GAIN_COMP_2, CYREG_BLE_BLERD_AGC_GAIN_COMP_2 .set BLE_cy_m0s8_ble__BALUN, CYREG_BLE_BLERD_BALUN .set BLE_cy_m0s8_ble__BB_BUMP1, CYREG_BLE_BLERD_BB_BUMP1 .set BLE_cy_m0s8_ble__BB_BUMP2, CYREG_BLE_BLERD_BB_BUMP2 @@ -82,10 +80,8 @@ .set BLE_cy_m0s8_ble__CONN_REQ_WORD8, CYREG_BLE_BLELL_CONN_REQ_WORD8 .set BLE_cy_m0s8_ble__CONN_REQ_WORD9, CYREG_BLE_BLELL_CONN_REQ_WORD9 .set BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR, CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR -.set BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR_DLE, CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE .set BLE_cy_m0s8_ble__CONN_STATUS, CYREG_BLE_BLELL_CONN_STATUS .set BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR, CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR -.set BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR_DLE, CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE .set BLE_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL, CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL .set BLE_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY, CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY .set BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL, CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL @@ -125,9 +121,6 @@ .set BLE_cy_m0s8_ble__DBUS, CYREG_BLE_BLERD_DBUS .set BLE_cy_m0s8_ble__DC, CYREG_BLE_BLERD_DC .set BLE_cy_m0s8_ble__DCCAL, CYREG_BLE_BLERD_DCCAL -.set BLE_cy_m0s8_ble__DEV_PA_ADDR_H, CYREG_BLE_BLELL_DEV_PA_ADDR_H -.set BLE_cy_m0s8_ble__DEV_PA_ADDR_L, CYREG_BLE_BLELL_DEV_PA_ADDR_L -.set BLE_cy_m0s8_ble__DEV_PA_ADDR_M, CYREG_BLE_BLELL_DEV_PA_ADDR_M .set BLE_cy_m0s8_ble__DEV_PUB_ADDR_H, CYREG_BLE_BLELL_DEV_PUB_ADDR_H .set BLE_cy_m0s8_ble__DEV_PUB_ADDR_L, CYREG_BLE_BLELL_DEV_PUB_ADDR_L .set BLE_cy_m0s8_ble__DEV_PUB_ADDR_M, CYREG_BLE_BLELL_DEV_PUB_ADDR_M @@ -154,7 +147,6 @@ .set BLE_cy_m0s8_ble__ENC_KEY5, CYREG_BLE_BLELL_ENC_KEY5 .set BLE_cy_m0s8_ble__ENC_KEY6, CYREG_BLE_BLELL_ENC_KEY6 .set BLE_cy_m0s8_ble__ENC_KEY7, CYREG_BLE_BLELL_ENC_KEY7 -.set BLE_cy_m0s8_ble__ENC_MEM_BASE_ADDR, CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR .set BLE_cy_m0s8_ble__ENC_PARAMS, CYREG_BLE_BLELL_ENC_PARAMS .set BLE_cy_m0s8_ble__EVENT_ENABLE, CYREG_BLE_BLELL_EVENT_ENABLE .set BLE_cy_m0s8_ble__EVENT_INTR, CYREG_BLE_BLELL_EVENT_INTR @@ -182,10 +174,8 @@ .set BLE_cy_m0s8_ble__LE_PING_TIMER_OFFSET, CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET .set BLE_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT, CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT .set BLE_cy_m0s8_ble__LE_RF_TEST_MODE, CYREG_BLE_BLELL_LE_RF_TEST_MODE -.set BLE_cy_m0s8_ble__LE_RF_TEST_MODE_EXT, CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT .set BLE_cy_m0s8_ble__LF_CLK_CTRL, CYREG_BLE_BLESS_LF_CLK_CTRL .set BLE_cy_m0s8_ble__LL_CLK_EN, CYREG_BLE_BLESS_LL_CLK_EN -.set BLE_cy_m0s8_ble__LL_CONTROL, CYREG_BLE_BLELL_LL_CONTROL .set BLE_cy_m0s8_ble__LL_DSM_CTRL, CYREG_BLE_BLESS_LL_DSM_CTRL .set BLE_cy_m0s8_ble__LL_DSM_INTR_STAT, CYREG_BLE_BLESS_LL_DSM_INTR_STAT .set BLE_cy_m0s8_ble__LLH_FEATURE_CONFIG, CYREG_BLE_BLELL_LLH_FEATURE_CONFIG @@ -199,7 +189,6 @@ .set BLE_cy_m0s8_ble__NEXT_RESP_TIMER_EXP, CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP .set BLE_cy_m0s8_ble__NEXT_SUP_TO, CYREG_BLE_BLELL_NEXT_SUP_TO .set BLE_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT, CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT -.set BLE_cy_m0s8_ble__PA_RSSI_NEW, CYREG_BLE_BLERD_PA_RSSI_NEW .set BLE_cy_m0s8_ble__PACKET_COUNTER0, CYREG_BLE_BLELL_PACKET_COUNTER0 .set BLE_cy_m0s8_ble__PACKET_COUNTER1, CYREG_BLE_BLELL_PACKET_COUNTER1 .set BLE_cy_m0s8_ble__PACKET_COUNTER2, CYREG_BLE_BLELL_PACKET_COUNTER2 @@ -218,18 +207,6 @@ .set BLE_cy_m0s8_ble__RECEIVE_TRIG_CTRL, CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL .set BLE_cy_m0s8_ble__RF_CONFIG, CYREG_BLE_BLESS_RF_CONFIG .set BLE_cy_m0s8_ble__RMAP, CYREG_BLE_BLERD_RMAP -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE0, CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE1, CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE2, CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE3, CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE4, CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE5, CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE6, CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 -.set BLE_cy_m0s8_ble__RSLV_LIST_ENABLE7, CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 -.set BLE_cy_m0s8_ble__RSLV_LIST_PEER_IDNTT_BASE_ADDR, CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR -.set BLE_cy_m0s8_ble__RSLV_LIST_PEER_RPA_BASE_ADDR, CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR -.set BLE_cy_m0s8_ble__RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR, CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR -.set BLE_cy_m0s8_ble__RSLV_LIST_TX_INIT_RPA_BASE_ADDR, CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR .set BLE_cy_m0s8_ble__RSSI, CYREG_BLE_BLERD_RSSI .set BLE_cy_m0s8_ble__RX, CYREG_BLE_BLERD_RX .set BLE_cy_m0s8_ble__RX_BUMP1, CYREG_BLE_BLERD_RX_BUMP1 @@ -509,257 +486,68 @@ .set SCB_sda__SHIFT, 4 /* SW2 */ -.set SW2__0__DR, CYREG_GPIO_PRT2_DR -.set SW2__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR -.set SW2__0__DR_INV, CYREG_GPIO_PRT2_DR_INV -.set SW2__0__DR_SET, CYREG_GPIO_PRT2_DR_SET -.set SW2__0__HSIOM, CYREG_HSIOM_PORT_SEL2 -.set SW2__0__HSIOM_MASK, 0xF0000000 -.set SW2__0__HSIOM_SHIFT, 28 -.set SW2__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG -.set SW2__0__INTR, CYREG_GPIO_PRT2_INTR -.set SW2__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG -.set SW2__0__INTSTAT, CYREG_GPIO_PRT2_INTR -.set SW2__0__MASK, 0x80 -.set SW2__0__PA__CFG0, CYREG_UDB_PA2_CFG0 -.set SW2__0__PA__CFG1, CYREG_UDB_PA2_CFG1 -.set SW2__0__PA__CFG10, CYREG_UDB_PA2_CFG10 -.set SW2__0__PA__CFG11, CYREG_UDB_PA2_CFG11 -.set SW2__0__PA__CFG12, CYREG_UDB_PA2_CFG12 -.set SW2__0__PA__CFG13, CYREG_UDB_PA2_CFG13 -.set SW2__0__PA__CFG14, CYREG_UDB_PA2_CFG14 -.set SW2__0__PA__CFG2, CYREG_UDB_PA2_CFG2 -.set SW2__0__PA__CFG3, CYREG_UDB_PA2_CFG3 -.set SW2__0__PA__CFG4, CYREG_UDB_PA2_CFG4 -.set SW2__0__PA__CFG5, CYREG_UDB_PA2_CFG5 -.set SW2__0__PA__CFG6, CYREG_UDB_PA2_CFG6 -.set SW2__0__PA__CFG7, CYREG_UDB_PA2_CFG7 -.set SW2__0__PA__CFG8, CYREG_UDB_PA2_CFG8 -.set SW2__0__PA__CFG9, CYREG_UDB_PA2_CFG9 -.set SW2__0__PC, CYREG_GPIO_PRT2_PC -.set SW2__0__PC2, CYREG_GPIO_PRT2_PC2 -.set SW2__0__PORT, 2 -.set SW2__0__PS, CYREG_GPIO_PRT2_PS -.set SW2__0__SHIFT, 7 -.set SW2__DR, CYREG_GPIO_PRT2_DR -.set SW2__DR_CLR, CYREG_GPIO_PRT2_DR_CLR -.set SW2__DR_INV, CYREG_GPIO_PRT2_DR_INV -.set SW2__DR_SET, CYREG_GPIO_PRT2_DR_SET -.set SW2__INTCFG, CYREG_GPIO_PRT2_INTR_CFG -.set SW2__INTR, CYREG_GPIO_PRT2_INTR -.set SW2__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG -.set SW2__INTSTAT, CYREG_GPIO_PRT2_INTR -.set SW2__MASK, 0x80 -.set SW2__PA__CFG0, CYREG_UDB_PA2_CFG0 -.set SW2__PA__CFG1, CYREG_UDB_PA2_CFG1 -.set SW2__PA__CFG10, CYREG_UDB_PA2_CFG10 -.set SW2__PA__CFG11, CYREG_UDB_PA2_CFG11 -.set SW2__PA__CFG12, CYREG_UDB_PA2_CFG12 -.set SW2__PA__CFG13, CYREG_UDB_PA2_CFG13 -.set SW2__PA__CFG14, CYREG_UDB_PA2_CFG14 -.set SW2__PA__CFG2, CYREG_UDB_PA2_CFG2 -.set SW2__PA__CFG3, CYREG_UDB_PA2_CFG3 -.set SW2__PA__CFG4, CYREG_UDB_PA2_CFG4 -.set SW2__PA__CFG5, CYREG_UDB_PA2_CFG5 -.set SW2__PA__CFG6, CYREG_UDB_PA2_CFG6 -.set SW2__PA__CFG7, CYREG_UDB_PA2_CFG7 -.set SW2__PA__CFG8, CYREG_UDB_PA2_CFG8 -.set SW2__PA__CFG9, CYREG_UDB_PA2_CFG9 -.set SW2__PC, CYREG_GPIO_PRT2_PC -.set SW2__PC2, CYREG_GPIO_PRT2_PC2 -.set SW2__PORT, 2 -.set SW2__PS, CYREG_GPIO_PRT2_PS -.set SW2__SHIFT, 7 -.set SW2__SNAP, CYREG_GPIO_PRT2_INTR - -/* LED_BLU */ -.set LED_BLU__0__DR, CYREG_GPIO_PRT3_DR -.set LED_BLU__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR -.set LED_BLU__0__DR_INV, CYREG_GPIO_PRT3_DR_INV -.set LED_BLU__0__DR_SET, CYREG_GPIO_PRT3_DR_SET -.set LED_BLU__0__HSIOM, CYREG_HSIOM_PORT_SEL3 -.set LED_BLU__0__HSIOM_MASK, 0xF0000000 -.set LED_BLU__0__HSIOM_SHIFT, 28 -.set LED_BLU__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_BLU__0__INTR, CYREG_GPIO_PRT3_INTR -.set LED_BLU__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_BLU__0__INTSTAT, CYREG_GPIO_PRT3_INTR -.set LED_BLU__0__MASK, 0x80 -.set LED_BLU__0__PA__CFG0, CYREG_UDB_PA3_CFG0 -.set LED_BLU__0__PA__CFG1, CYREG_UDB_PA3_CFG1 -.set LED_BLU__0__PA__CFG10, CYREG_UDB_PA3_CFG10 -.set LED_BLU__0__PA__CFG11, CYREG_UDB_PA3_CFG11 -.set LED_BLU__0__PA__CFG12, CYREG_UDB_PA3_CFG12 -.set LED_BLU__0__PA__CFG13, CYREG_UDB_PA3_CFG13 -.set LED_BLU__0__PA__CFG14, CYREG_UDB_PA3_CFG14 -.set LED_BLU__0__PA__CFG2, CYREG_UDB_PA3_CFG2 -.set LED_BLU__0__PA__CFG3, CYREG_UDB_PA3_CFG3 -.set LED_BLU__0__PA__CFG4, CYREG_UDB_PA3_CFG4 -.set LED_BLU__0__PA__CFG5, CYREG_UDB_PA3_CFG5 -.set LED_BLU__0__PA__CFG6, CYREG_UDB_PA3_CFG6 -.set LED_BLU__0__PA__CFG7, CYREG_UDB_PA3_CFG7 -.set LED_BLU__0__PA__CFG8, CYREG_UDB_PA3_CFG8 -.set LED_BLU__0__PA__CFG9, CYREG_UDB_PA3_CFG9 -.set LED_BLU__0__PC, CYREG_GPIO_PRT3_PC -.set LED_BLU__0__PC2, CYREG_GPIO_PRT3_PC2 -.set LED_BLU__0__PORT, 3 -.set LED_BLU__0__PS, CYREG_GPIO_PRT3_PS -.set LED_BLU__0__SHIFT, 7 -.set LED_BLU__DR, CYREG_GPIO_PRT3_DR -.set LED_BLU__DR_CLR, CYREG_GPIO_PRT3_DR_CLR -.set LED_BLU__DR_INV, CYREG_GPIO_PRT3_DR_INV -.set LED_BLU__DR_SET, CYREG_GPIO_PRT3_DR_SET -.set LED_BLU__INTCFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_BLU__INTR, CYREG_GPIO_PRT3_INTR -.set LED_BLU__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_BLU__INTSTAT, CYREG_GPIO_PRT3_INTR -.set LED_BLU__MASK, 0x80 -.set LED_BLU__PA__CFG0, CYREG_UDB_PA3_CFG0 -.set LED_BLU__PA__CFG1, CYREG_UDB_PA3_CFG1 -.set LED_BLU__PA__CFG10, CYREG_UDB_PA3_CFG10 -.set LED_BLU__PA__CFG11, CYREG_UDB_PA3_CFG11 -.set LED_BLU__PA__CFG12, CYREG_UDB_PA3_CFG12 -.set LED_BLU__PA__CFG13, CYREG_UDB_PA3_CFG13 -.set LED_BLU__PA__CFG14, CYREG_UDB_PA3_CFG14 -.set LED_BLU__PA__CFG2, CYREG_UDB_PA3_CFG2 -.set LED_BLU__PA__CFG3, CYREG_UDB_PA3_CFG3 -.set LED_BLU__PA__CFG4, CYREG_UDB_PA3_CFG4 -.set LED_BLU__PA__CFG5, CYREG_UDB_PA3_CFG5 -.set LED_BLU__PA__CFG6, CYREG_UDB_PA3_CFG6 -.set LED_BLU__PA__CFG7, CYREG_UDB_PA3_CFG7 -.set LED_BLU__PA__CFG8, CYREG_UDB_PA3_CFG8 -.set LED_BLU__PA__CFG9, CYREG_UDB_PA3_CFG9 -.set LED_BLU__PC, CYREG_GPIO_PRT3_PC -.set LED_BLU__PC2, CYREG_GPIO_PRT3_PC2 -.set LED_BLU__PORT, 3 -.set LED_BLU__PS, CYREG_GPIO_PRT3_PS -.set LED_BLU__SHIFT, 7 - -/* LED_GRN */ -.set LED_GRN__0__DR, CYREG_GPIO_PRT3_DR -.set LED_GRN__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR -.set LED_GRN__0__DR_INV, CYREG_GPIO_PRT3_DR_INV -.set LED_GRN__0__DR_SET, CYREG_GPIO_PRT3_DR_SET -.set LED_GRN__0__HSIOM, CYREG_HSIOM_PORT_SEL3 -.set LED_GRN__0__HSIOM_MASK, 0x0F000000 -.set LED_GRN__0__HSIOM_SHIFT, 24 -.set LED_GRN__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_GRN__0__INTR, CYREG_GPIO_PRT3_INTR -.set LED_GRN__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_GRN__0__INTSTAT, CYREG_GPIO_PRT3_INTR -.set LED_GRN__0__MASK, 0x40 -.set LED_GRN__0__PA__CFG0, CYREG_UDB_PA3_CFG0 -.set LED_GRN__0__PA__CFG1, CYREG_UDB_PA3_CFG1 -.set LED_GRN__0__PA__CFG10, CYREG_UDB_PA3_CFG10 -.set LED_GRN__0__PA__CFG11, CYREG_UDB_PA3_CFG11 -.set LED_GRN__0__PA__CFG12, CYREG_UDB_PA3_CFG12 -.set LED_GRN__0__PA__CFG13, CYREG_UDB_PA3_CFG13 -.set LED_GRN__0__PA__CFG14, CYREG_UDB_PA3_CFG14 -.set LED_GRN__0__PA__CFG2, CYREG_UDB_PA3_CFG2 -.set LED_GRN__0__PA__CFG3, CYREG_UDB_PA3_CFG3 -.set LED_GRN__0__PA__CFG4, CYREG_UDB_PA3_CFG4 -.set LED_GRN__0__PA__CFG5, CYREG_UDB_PA3_CFG5 -.set LED_GRN__0__PA__CFG6, CYREG_UDB_PA3_CFG6 -.set LED_GRN__0__PA__CFG7, CYREG_UDB_PA3_CFG7 -.set LED_GRN__0__PA__CFG8, CYREG_UDB_PA3_CFG8 -.set LED_GRN__0__PA__CFG9, CYREG_UDB_PA3_CFG9 -.set LED_GRN__0__PC, CYREG_GPIO_PRT3_PC -.set LED_GRN__0__PC2, CYREG_GPIO_PRT3_PC2 -.set LED_GRN__0__PORT, 3 -.set LED_GRN__0__PS, CYREG_GPIO_PRT3_PS -.set LED_GRN__0__SHIFT, 6 -.set LED_GRN__DR, CYREG_GPIO_PRT3_DR -.set LED_GRN__DR_CLR, CYREG_GPIO_PRT3_DR_CLR -.set LED_GRN__DR_INV, CYREG_GPIO_PRT3_DR_INV -.set LED_GRN__DR_SET, CYREG_GPIO_PRT3_DR_SET -.set LED_GRN__INTCFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_GRN__INTR, CYREG_GPIO_PRT3_INTR -.set LED_GRN__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG -.set LED_GRN__INTSTAT, CYREG_GPIO_PRT3_INTR -.set LED_GRN__MASK, 0x40 -.set LED_GRN__PA__CFG0, CYREG_UDB_PA3_CFG0 -.set LED_GRN__PA__CFG1, CYREG_UDB_PA3_CFG1 -.set LED_GRN__PA__CFG10, CYREG_UDB_PA3_CFG10 -.set LED_GRN__PA__CFG11, CYREG_UDB_PA3_CFG11 -.set LED_GRN__PA__CFG12, CYREG_UDB_PA3_CFG12 -.set LED_GRN__PA__CFG13, CYREG_UDB_PA3_CFG13 -.set LED_GRN__PA__CFG14, CYREG_UDB_PA3_CFG14 -.set LED_GRN__PA__CFG2, CYREG_UDB_PA3_CFG2 -.set LED_GRN__PA__CFG3, CYREG_UDB_PA3_CFG3 -.set LED_GRN__PA__CFG4, CYREG_UDB_PA3_CFG4 -.set LED_GRN__PA__CFG5, CYREG_UDB_PA3_CFG5 -.set LED_GRN__PA__CFG6, CYREG_UDB_PA3_CFG6 -.set LED_GRN__PA__CFG7, CYREG_UDB_PA3_CFG7 -.set LED_GRN__PA__CFG8, CYREG_UDB_PA3_CFG8 -.set LED_GRN__PA__CFG9, CYREG_UDB_PA3_CFG9 -.set LED_GRN__PC, CYREG_GPIO_PRT3_PC -.set LED_GRN__PC2, CYREG_GPIO_PRT3_PC2 -.set LED_GRN__PORT, 3 -.set LED_GRN__PS, CYREG_GPIO_PRT3_PS -.set LED_GRN__SHIFT, 6 - -/* LED_RED */ -.set LED_RED__0__DR, CYREG_GPIO_PRT2_DR -.set LED_RED__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR -.set LED_RED__0__DR_INV, CYREG_GPIO_PRT2_DR_INV -.set LED_RED__0__DR_SET, CYREG_GPIO_PRT2_DR_SET -.set LED_RED__0__HSIOM, CYREG_HSIOM_PORT_SEL2 -.set LED_RED__0__HSIOM_MASK, 0x0F000000 -.set LED_RED__0__HSIOM_SHIFT, 24 -.set LED_RED__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG -.set LED_RED__0__INTR, CYREG_GPIO_PRT2_INTR -.set LED_RED__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG -.set LED_RED__0__INTSTAT, CYREG_GPIO_PRT2_INTR -.set LED_RED__0__MASK, 0x40 -.set LED_RED__0__PA__CFG0, CYREG_UDB_PA2_CFG0 -.set LED_RED__0__PA__CFG1, CYREG_UDB_PA2_CFG1 -.set LED_RED__0__PA__CFG10, CYREG_UDB_PA2_CFG10 -.set LED_RED__0__PA__CFG11, CYREG_UDB_PA2_CFG11 -.set LED_RED__0__PA__CFG12, CYREG_UDB_PA2_CFG12 -.set LED_RED__0__PA__CFG13, CYREG_UDB_PA2_CFG13 -.set LED_RED__0__PA__CFG14, CYREG_UDB_PA2_CFG14 -.set LED_RED__0__PA__CFG2, CYREG_UDB_PA2_CFG2 -.set LED_RED__0__PA__CFG3, CYREG_UDB_PA2_CFG3 -.set LED_RED__0__PA__CFG4, CYREG_UDB_PA2_CFG4 -.set LED_RED__0__PA__CFG5, CYREG_UDB_PA2_CFG5 -.set LED_RED__0__PA__CFG6, CYREG_UDB_PA2_CFG6 -.set LED_RED__0__PA__CFG7, CYREG_UDB_PA2_CFG7 -.set LED_RED__0__PA__CFG8, CYREG_UDB_PA2_CFG8 -.set LED_RED__0__PA__CFG9, CYREG_UDB_PA2_CFG9 -.set LED_RED__0__PC, CYREG_GPIO_PRT2_PC -.set LED_RED__0__PC2, CYREG_GPIO_PRT2_PC2 -.set LED_RED__0__PORT, 2 -.set LED_RED__0__PS, CYREG_GPIO_PRT2_PS -.set LED_RED__0__SHIFT, 6 -.set LED_RED__DR, CYREG_GPIO_PRT2_DR -.set LED_RED__DR_CLR, CYREG_GPIO_PRT2_DR_CLR -.set LED_RED__DR_INV, CYREG_GPIO_PRT2_DR_INV -.set LED_RED__DR_SET, CYREG_GPIO_PRT2_DR_SET -.set LED_RED__INTCFG, CYREG_GPIO_PRT2_INTR_CFG -.set LED_RED__INTR, CYREG_GPIO_PRT2_INTR -.set LED_RED__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG -.set LED_RED__INTSTAT, CYREG_GPIO_PRT2_INTR -.set LED_RED__MASK, 0x40 -.set LED_RED__PA__CFG0, CYREG_UDB_PA2_CFG0 -.set LED_RED__PA__CFG1, CYREG_UDB_PA2_CFG1 -.set LED_RED__PA__CFG10, CYREG_UDB_PA2_CFG10 -.set LED_RED__PA__CFG11, CYREG_UDB_PA2_CFG11 -.set LED_RED__PA__CFG12, CYREG_UDB_PA2_CFG12 -.set LED_RED__PA__CFG13, CYREG_UDB_PA2_CFG13 -.set LED_RED__PA__CFG14, CYREG_UDB_PA2_CFG14 -.set LED_RED__PA__CFG2, CYREG_UDB_PA2_CFG2 -.set LED_RED__PA__CFG3, CYREG_UDB_PA2_CFG3 -.set LED_RED__PA__CFG4, CYREG_UDB_PA2_CFG4 -.set LED_RED__PA__CFG5, CYREG_UDB_PA2_CFG5 -.set LED_RED__PA__CFG6, CYREG_UDB_PA2_CFG6 -.set LED_RED__PA__CFG7, CYREG_UDB_PA2_CFG7 -.set LED_RED__PA__CFG8, CYREG_UDB_PA2_CFG8 -.set LED_RED__PA__CFG9, CYREG_UDB_PA2_CFG9 -.set LED_RED__PC, CYREG_GPIO_PRT2_PC -.set LED_RED__PC2, CYREG_GPIO_PRT2_PC2 -.set LED_RED__PORT, 2 -.set LED_RED__PS, CYREG_GPIO_PRT2_PS -.set LED_RED__SHIFT, 6 +.set SW2__0__DR, CYREG_GPIO_PRT0_DR +.set SW2__0__DR_CLR, CYREG_GPIO_PRT0_DR_CLR +.set SW2__0__DR_INV, CYREG_GPIO_PRT0_DR_INV +.set SW2__0__DR_SET, CYREG_GPIO_PRT0_DR_SET +.set SW2__0__HSIOM, CYREG_HSIOM_PORT_SEL0 +.set SW2__0__HSIOM_MASK, 0x000000F0 +.set SW2__0__HSIOM_SHIFT, 4 +.set SW2__0__INTCFG, CYREG_GPIO_PRT0_INTR_CFG +.set SW2__0__INTR, CYREG_GPIO_PRT0_INTR +.set SW2__0__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG +.set SW2__0__INTSTAT, CYREG_GPIO_PRT0_INTR +.set SW2__0__MASK, 0x02 +.set SW2__0__PA__CFG0, CYREG_UDB_PA0_CFG0 +.set SW2__0__PA__CFG1, CYREG_UDB_PA0_CFG1 +.set SW2__0__PA__CFG10, CYREG_UDB_PA0_CFG10 +.set SW2__0__PA__CFG11, CYREG_UDB_PA0_CFG11 +.set SW2__0__PA__CFG12, CYREG_UDB_PA0_CFG12 +.set SW2__0__PA__CFG13, CYREG_UDB_PA0_CFG13 +.set SW2__0__PA__CFG14, CYREG_UDB_PA0_CFG14 +.set SW2__0__PA__CFG2, CYREG_UDB_PA0_CFG2 +.set SW2__0__PA__CFG3, CYREG_UDB_PA0_CFG3 +.set SW2__0__PA__CFG4, CYREG_UDB_PA0_CFG4 +.set SW2__0__PA__CFG5, CYREG_UDB_PA0_CFG5 +.set SW2__0__PA__CFG6, CYREG_UDB_PA0_CFG6 +.set SW2__0__PA__CFG7, CYREG_UDB_PA0_CFG7 +.set SW2__0__PA__CFG8, CYREG_UDB_PA0_CFG8 +.set SW2__0__PA__CFG9, CYREG_UDB_PA0_CFG9 +.set SW2__0__PC, CYREG_GPIO_PRT0_PC +.set SW2__0__PC2, CYREG_GPIO_PRT0_PC2 +.set SW2__0__PORT, 0 +.set SW2__0__PS, CYREG_GPIO_PRT0_PS +.set SW2__0__SHIFT, 1 +.set SW2__DR, CYREG_GPIO_PRT0_DR +.set SW2__DR_CLR, CYREG_GPIO_PRT0_DR_CLR +.set SW2__DR_INV, CYREG_GPIO_PRT0_DR_INV +.set SW2__DR_SET, CYREG_GPIO_PRT0_DR_SET +.set SW2__INTCFG, CYREG_GPIO_PRT0_INTR_CFG +.set SW2__INTR, CYREG_GPIO_PRT0_INTR +.set SW2__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG +.set SW2__INTSTAT, CYREG_GPIO_PRT0_INTR +.set SW2__MASK, 0x02 +.set SW2__PA__CFG0, CYREG_UDB_PA0_CFG0 +.set SW2__PA__CFG1, CYREG_UDB_PA0_CFG1 +.set SW2__PA__CFG10, CYREG_UDB_PA0_CFG10 +.set SW2__PA__CFG11, CYREG_UDB_PA0_CFG11 +.set SW2__PA__CFG12, CYREG_UDB_PA0_CFG12 +.set SW2__PA__CFG13, CYREG_UDB_PA0_CFG13 +.set SW2__PA__CFG14, CYREG_UDB_PA0_CFG14 +.set SW2__PA__CFG2, CYREG_UDB_PA0_CFG2 +.set SW2__PA__CFG3, CYREG_UDB_PA0_CFG3 +.set SW2__PA__CFG4, CYREG_UDB_PA0_CFG4 +.set SW2__PA__CFG5, CYREG_UDB_PA0_CFG5 +.set SW2__PA__CFG6, CYREG_UDB_PA0_CFG6 +.set SW2__PA__CFG7, CYREG_UDB_PA0_CFG7 +.set SW2__PA__CFG8, CYREG_UDB_PA0_CFG8 +.set SW2__PA__CFG9, CYREG_UDB_PA0_CFG9 +.set SW2__PC, CYREG_GPIO_PRT0_PC +.set SW2__PC2, CYREG_GPIO_PRT0_PC2 +.set SW2__PORT, 0 +.set SW2__PS, CYREG_GPIO_PRT0_PS +.set SW2__SHIFT, 1 +.set SW2__SNAP, CYREG_GPIO_PRT0_INTR /* UART_DEB */ .set UART_DEB_rx__0__DR, CYREG_GPIO_PRT1_DR @@ -992,9 +780,9 @@ /* Wakeup_Interrupt */ .set Wakeup_Interrupt__INTC_CLR_EN_REG, CYREG_CM0_ICER .set Wakeup_Interrupt__INTC_CLR_PD_REG, CYREG_CM0_ICPR -.set Wakeup_Interrupt__INTC_MASK, 0x04 -.set Wakeup_Interrupt__INTC_NUMBER, 2 -.set Wakeup_Interrupt__INTC_PRIOR_MASK, 0xC00000 +.set Wakeup_Interrupt__INTC_MASK, 0x01 +.set Wakeup_Interrupt__INTC_NUMBER, 0 +.set Wakeup_Interrupt__INTC_PRIOR_MASK, 0xC0 .set Wakeup_Interrupt__INTC_PRIOR_NUM, 3 .set Wakeup_Interrupt__INTC_PRIOR_REG, CYREG_CM0_IPR0 .set Wakeup_Interrupt__INTC_SET_EN_REG, CYREG_CM0_ISER @@ -1022,7 +810,7 @@ .set CYDEV_CHIP_FAMILY_PSOC6, 4 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4 -.set CYDEV_CHIP_JTAG_ID, 0x1A1711AA +.set CYDEV_CHIP_JTAG_ID, 0x0E49119E .set CYDEV_CHIP_MEMBER_3A, 1 .set CYDEV_CHIP_MEMBER_4A, 18 .set CYDEV_CHIP_MEMBER_4D, 13 @@ -1113,7 +901,7 @@ .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 -.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4F_PRODUCTION .set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED .set CYDEV_CONFIG_READ_ACCELERATOR, 1 .set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 @@ -1135,11 +923,9 @@ .set CYDEV_DEBUGGING_ENABLE, 1 .set CYDEV_DFT_SELECT_CLK0, 10 .set CYDEV_DFT_SELECT_CLK1, 11 -.set CYDEV_DMA_CHANNELS_AVAILABLE, 8 .set CYDEV_HEAP_SIZE, 0x400 .set CYDEV_IMO_TRIMMED_BY_USB, 0 .set CYDEV_IMO_TRIMMED_BY_WCO, 0 -.set CYDEV_INTR_NUMBER_DMA, 21 .set CYDEV_IS_EXPORTING_CODE, 0 .set CYDEV_IS_IMPORTING_CODE, 0 .set CYDEV_PROJ_TYPE, 0 @@ -1152,11 +938,11 @@ .set CYDEV_STACK_SIZE, 0x0800 .set CYDEV_USE_BUNDLED_CMSIS, 1 .set CYDEV_VARIABLE_VDDA, 1 +.set CYDEV_VDD_MV, 3300 .set CYDEV_VDDA_MV, 3300 -.set CYDEV_VDDD_MV, 3300 .set CYDEV_VDDR_MV, 3300 .set CYDEV_WDT_GENERATE_ISR, 1 -.set CYIPBLOCK_m0s8bless_VERSION, 2 +.set CYIPBLOCK_m0s8bless_VERSION, 1 .set CYIPBLOCK_m0s8cpussv2_VERSION, 1 .set CYIPBLOCK_m0s8csd_VERSION, 1 .set CYIPBLOCK_m0s8ioss_VERSION, 1 @@ -1168,6 +954,5 @@ .set CYIPBLOCK_m0s8tcpwm_VERSION, 2 .set CYIPBLOCK_m0s8udbif_VERSION, 1 .set CYIPBLOCK_s8pass4al_VERSION, 1 -.set DMA_CHANNELS_USED__MASK, 0 .set CYDEV_BOOTLOADER_ENABLE, 0 .endif diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyfitteriar.inc b/BLE.cydsn/Generated_Source/PSoC4/cyfitteriar.inc index 527474d..72ca0de 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyfitteriar.inc +++ b/BLE.cydsn/Generated_Source/PSoC4/cyfitteriar.inc @@ -38,8 +38,6 @@ BLE_cy_m0s8_ble__ADV_PARAMS EQU CYREG_BLE_BLELL_ADV_PARAMS BLE_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO EQU CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO BLE_cy_m0s8_ble__ADV_TX_DATA_FIFO EQU CYREG_BLE_BLELL_ADV_TX_DATA_FIFO BLE_cy_m0s8_ble__AGC EQU CYREG_BLE_BLERD_AGC -BLE_cy_m0s8_ble__AGC_GAIN_COMP_1 EQU CYREG_BLE_BLERD_AGC_GAIN_COMP_1 -BLE_cy_m0s8_ble__AGC_GAIN_COMP_2 EQU CYREG_BLE_BLERD_AGC_GAIN_COMP_2 BLE_cy_m0s8_ble__BALUN EQU CYREG_BLE_BLERD_BALUN BLE_cy_m0s8_ble__BB_BUMP1 EQU CYREG_BLE_BLERD_BB_BUMP1 BLE_cy_m0s8_ble__BB_BUMP2 EQU CYREG_BLE_BLERD_BB_BUMP2 @@ -81,10 +79,8 @@ BLE_cy_m0s8_ble__CONN_REQ_WORD7 EQU CYREG_BLE_BLELL_CONN_REQ_WORD7 BLE_cy_m0s8_ble__CONN_REQ_WORD8 EQU CYREG_BLE_BLELL_CONN_REQ_WORD8 BLE_cy_m0s8_ble__CONN_REQ_WORD9 EQU CYREG_BLE_BLELL_CONN_REQ_WORD9 BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR EQU CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR -BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR_DLE EQU CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE BLE_cy_m0s8_ble__CONN_STATUS EQU CYREG_BLE_BLELL_CONN_STATUS BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR EQU CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR -BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR_DLE EQU CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE BLE_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL BLE_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL @@ -124,9 +120,6 @@ BLE_cy_m0s8_ble__DBG_BB EQU CYREG_BLE_BLERD_DBG_BB BLE_cy_m0s8_ble__DBUS EQU CYREG_BLE_BLERD_DBUS BLE_cy_m0s8_ble__DC EQU CYREG_BLE_BLERD_DC BLE_cy_m0s8_ble__DCCAL EQU CYREG_BLE_BLERD_DCCAL -BLE_cy_m0s8_ble__DEV_PA_ADDR_H EQU CYREG_BLE_BLELL_DEV_PA_ADDR_H -BLE_cy_m0s8_ble__DEV_PA_ADDR_L EQU CYREG_BLE_BLELL_DEV_PA_ADDR_L -BLE_cy_m0s8_ble__DEV_PA_ADDR_M EQU CYREG_BLE_BLELL_DEV_PA_ADDR_M BLE_cy_m0s8_ble__DEV_PUB_ADDR_H EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_H BLE_cy_m0s8_ble__DEV_PUB_ADDR_L EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_L BLE_cy_m0s8_ble__DEV_PUB_ADDR_M EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_M @@ -153,7 +146,6 @@ BLE_cy_m0s8_ble__ENC_KEY4 EQU CYREG_BLE_BLELL_ENC_KEY4 BLE_cy_m0s8_ble__ENC_KEY5 EQU CYREG_BLE_BLELL_ENC_KEY5 BLE_cy_m0s8_ble__ENC_KEY6 EQU CYREG_BLE_BLELL_ENC_KEY6 BLE_cy_m0s8_ble__ENC_KEY7 EQU CYREG_BLE_BLELL_ENC_KEY7 -BLE_cy_m0s8_ble__ENC_MEM_BASE_ADDR EQU CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR BLE_cy_m0s8_ble__ENC_PARAMS EQU CYREG_BLE_BLELL_ENC_PARAMS BLE_cy_m0s8_ble__EVENT_ENABLE EQU CYREG_BLE_BLELL_EVENT_ENABLE BLE_cy_m0s8_ble__EVENT_INTR EQU CYREG_BLE_BLELL_EVENT_INTR @@ -181,10 +173,8 @@ BLE_cy_m0s8_ble__LE_PING_TIMER_NEXT_EXP EQU CYREG_BLE_BLELL_LE_PING_TIMER_NEXT_E BLE_cy_m0s8_ble__LE_PING_TIMER_OFFSET EQU CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET BLE_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT EQU CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT BLE_cy_m0s8_ble__LE_RF_TEST_MODE EQU CYREG_BLE_BLELL_LE_RF_TEST_MODE -BLE_cy_m0s8_ble__LE_RF_TEST_MODE_EXT EQU CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT BLE_cy_m0s8_ble__LF_CLK_CTRL EQU CYREG_BLE_BLESS_LF_CLK_CTRL BLE_cy_m0s8_ble__LL_CLK_EN EQU CYREG_BLE_BLESS_LL_CLK_EN -BLE_cy_m0s8_ble__LL_CONTROL EQU CYREG_BLE_BLELL_LL_CONTROL BLE_cy_m0s8_ble__LL_DSM_CTRL EQU CYREG_BLE_BLESS_LL_DSM_CTRL BLE_cy_m0s8_ble__LL_DSM_INTR_STAT EQU CYREG_BLE_BLESS_LL_DSM_INTR_STAT BLE_cy_m0s8_ble__LLH_FEATURE_CONFIG EQU CYREG_BLE_BLELL_LLH_FEATURE_CONFIG @@ -198,7 +188,6 @@ BLE_cy_m0s8_ble__NEXT_CE_INSTANT EQU CYREG_BLE_BLELL_NEXT_CE_INSTANT BLE_cy_m0s8_ble__NEXT_RESP_TIMER_EXP EQU CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP BLE_cy_m0s8_ble__NEXT_SUP_TO EQU CYREG_BLE_BLELL_NEXT_SUP_TO BLE_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT EQU CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT -BLE_cy_m0s8_ble__PA_RSSI_NEW EQU CYREG_BLE_BLERD_PA_RSSI_NEW BLE_cy_m0s8_ble__PACKET_COUNTER0 EQU CYREG_BLE_BLELL_PACKET_COUNTER0 BLE_cy_m0s8_ble__PACKET_COUNTER1 EQU CYREG_BLE_BLELL_PACKET_COUNTER1 BLE_cy_m0s8_ble__PACKET_COUNTER2 EQU CYREG_BLE_BLELL_PACKET_COUNTER2 @@ -217,18 +206,6 @@ BLE_cy_m0s8_ble__READ_IQ_4 EQU CYREG_BLE_BLERD_READ_IQ_4 BLE_cy_m0s8_ble__RECEIVE_TRIG_CTRL EQU CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL BLE_cy_m0s8_ble__RF_CONFIG EQU CYREG_BLE_BLESS_RF_CONFIG BLE_cy_m0s8_ble__RMAP EQU CYREG_BLE_BLERD_RMAP -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE0 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE1 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE2 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE3 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE4 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE5 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE6 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE7 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 -BLE_cy_m0s8_ble__RSLV_LIST_PEER_IDNTT_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR -BLE_cy_m0s8_ble__RSLV_LIST_PEER_RPA_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR -BLE_cy_m0s8_ble__RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR -BLE_cy_m0s8_ble__RSLV_LIST_TX_INIT_RPA_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR BLE_cy_m0s8_ble__RSSI EQU CYREG_BLE_BLERD_RSSI BLE_cy_m0s8_ble__RX EQU CYREG_BLE_BLERD_RX BLE_cy_m0s8_ble__RX_BUMP1 EQU CYREG_BLE_BLERD_RX_BUMP1 @@ -508,257 +485,68 @@ SCB_sda__PS EQU CYREG_GPIO_PRT3_PS SCB_sda__SHIFT EQU 4 /* SW2 */ -SW2__0__DR EQU CYREG_GPIO_PRT2_DR -SW2__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -SW2__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -SW2__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -SW2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 -SW2__0__HSIOM_MASK EQU 0xF0000000 -SW2__0__HSIOM_SHIFT EQU 28 -SW2__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__0__INTR EQU CYREG_GPIO_PRT2_INTR -SW2__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR -SW2__0__MASK EQU 0x80 -SW2__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -SW2__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -SW2__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -SW2__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -SW2__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -SW2__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -SW2__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -SW2__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -SW2__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -SW2__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -SW2__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -SW2__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -SW2__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -SW2__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -SW2__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -SW2__0__PC EQU CYREG_GPIO_PRT2_PC -SW2__0__PC2 EQU CYREG_GPIO_PRT2_PC2 -SW2__0__PORT EQU 2 -SW2__0__PS EQU CYREG_GPIO_PRT2_PS -SW2__0__SHIFT EQU 7 -SW2__DR EQU CYREG_GPIO_PRT2_DR -SW2__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -SW2__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -SW2__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -SW2__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__INTR EQU CYREG_GPIO_PRT2_INTR -SW2__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__INTSTAT EQU CYREG_GPIO_PRT2_INTR -SW2__MASK EQU 0x80 -SW2__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -SW2__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -SW2__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -SW2__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -SW2__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -SW2__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -SW2__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -SW2__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -SW2__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -SW2__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -SW2__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -SW2__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -SW2__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -SW2__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -SW2__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -SW2__PC EQU CYREG_GPIO_PRT2_PC -SW2__PC2 EQU CYREG_GPIO_PRT2_PC2 -SW2__PORT EQU 2 -SW2__PS EQU CYREG_GPIO_PRT2_PS -SW2__SHIFT EQU 7 -SW2__SNAP EQU CYREG_GPIO_PRT2_INTR - -/* LED_BLU */ -LED_BLU__0__DR EQU CYREG_GPIO_PRT3_DR -LED_BLU__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_BLU__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_BLU__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_BLU__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 -LED_BLU__0__HSIOM_MASK EQU 0xF0000000 -LED_BLU__0__HSIOM_SHIFT EQU 28 -LED_BLU__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__0__INTR EQU CYREG_GPIO_PRT3_INTR -LED_BLU__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_BLU__0__MASK EQU 0x80 -LED_BLU__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_BLU__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_BLU__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_BLU__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_BLU__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_BLU__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_BLU__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_BLU__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_BLU__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_BLU__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_BLU__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_BLU__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_BLU__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_BLU__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_BLU__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_BLU__0__PC EQU CYREG_GPIO_PRT3_PC -LED_BLU__0__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_BLU__0__PORT EQU 3 -LED_BLU__0__PS EQU CYREG_GPIO_PRT3_PS -LED_BLU__0__SHIFT EQU 7 -LED_BLU__DR EQU CYREG_GPIO_PRT3_DR -LED_BLU__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_BLU__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_BLU__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_BLU__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__INTR EQU CYREG_GPIO_PRT3_INTR -LED_BLU__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_BLU__MASK EQU 0x80 -LED_BLU__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_BLU__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_BLU__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_BLU__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_BLU__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_BLU__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_BLU__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_BLU__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_BLU__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_BLU__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_BLU__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_BLU__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_BLU__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_BLU__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_BLU__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_BLU__PC EQU CYREG_GPIO_PRT3_PC -LED_BLU__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_BLU__PORT EQU 3 -LED_BLU__PS EQU CYREG_GPIO_PRT3_PS -LED_BLU__SHIFT EQU 7 - -/* LED_GRN */ -LED_GRN__0__DR EQU CYREG_GPIO_PRT3_DR -LED_GRN__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_GRN__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_GRN__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_GRN__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 -LED_GRN__0__HSIOM_MASK EQU 0x0F000000 -LED_GRN__0__HSIOM_SHIFT EQU 24 -LED_GRN__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__0__INTR EQU CYREG_GPIO_PRT3_INTR -LED_GRN__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_GRN__0__MASK EQU 0x40 -LED_GRN__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_GRN__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_GRN__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_GRN__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_GRN__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_GRN__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_GRN__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_GRN__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_GRN__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_GRN__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_GRN__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_GRN__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_GRN__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_GRN__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_GRN__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_GRN__0__PC EQU CYREG_GPIO_PRT3_PC -LED_GRN__0__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_GRN__0__PORT EQU 3 -LED_GRN__0__PS EQU CYREG_GPIO_PRT3_PS -LED_GRN__0__SHIFT EQU 6 -LED_GRN__DR EQU CYREG_GPIO_PRT3_DR -LED_GRN__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_GRN__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_GRN__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_GRN__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__INTR EQU CYREG_GPIO_PRT3_INTR -LED_GRN__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_GRN__MASK EQU 0x40 -LED_GRN__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_GRN__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_GRN__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_GRN__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_GRN__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_GRN__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_GRN__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_GRN__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_GRN__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_GRN__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_GRN__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_GRN__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_GRN__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_GRN__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_GRN__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_GRN__PC EQU CYREG_GPIO_PRT3_PC -LED_GRN__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_GRN__PORT EQU 3 -LED_GRN__PS EQU CYREG_GPIO_PRT3_PS -LED_GRN__SHIFT EQU 6 - -/* LED_RED */ -LED_RED__0__DR EQU CYREG_GPIO_PRT2_DR -LED_RED__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -LED_RED__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -LED_RED__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -LED_RED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 -LED_RED__0__HSIOM_MASK EQU 0x0F000000 -LED_RED__0__HSIOM_SHIFT EQU 24 -LED_RED__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__0__INTR EQU CYREG_GPIO_PRT2_INTR -LED_RED__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR -LED_RED__0__MASK EQU 0x40 -LED_RED__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -LED_RED__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -LED_RED__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -LED_RED__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -LED_RED__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -LED_RED__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -LED_RED__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -LED_RED__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -LED_RED__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -LED_RED__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -LED_RED__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -LED_RED__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -LED_RED__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -LED_RED__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -LED_RED__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -LED_RED__0__PC EQU CYREG_GPIO_PRT2_PC -LED_RED__0__PC2 EQU CYREG_GPIO_PRT2_PC2 -LED_RED__0__PORT EQU 2 -LED_RED__0__PS EQU CYREG_GPIO_PRT2_PS -LED_RED__0__SHIFT EQU 6 -LED_RED__DR EQU CYREG_GPIO_PRT2_DR -LED_RED__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -LED_RED__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -LED_RED__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -LED_RED__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__INTR EQU CYREG_GPIO_PRT2_INTR -LED_RED__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__INTSTAT EQU CYREG_GPIO_PRT2_INTR -LED_RED__MASK EQU 0x40 -LED_RED__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -LED_RED__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -LED_RED__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -LED_RED__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -LED_RED__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -LED_RED__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -LED_RED__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -LED_RED__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -LED_RED__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -LED_RED__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -LED_RED__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -LED_RED__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -LED_RED__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -LED_RED__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -LED_RED__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -LED_RED__PC EQU CYREG_GPIO_PRT2_PC -LED_RED__PC2 EQU CYREG_GPIO_PRT2_PC2 -LED_RED__PORT EQU 2 -LED_RED__PS EQU CYREG_GPIO_PRT2_PS -LED_RED__SHIFT EQU 6 +SW2__0__DR EQU CYREG_GPIO_PRT0_DR +SW2__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR +SW2__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV +SW2__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET +SW2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0 +SW2__0__HSIOM_MASK EQU 0x000000F0 +SW2__0__HSIOM_SHIFT EQU 4 +SW2__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__0__INTR EQU CYREG_GPIO_PRT0_INTR +SW2__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR +SW2__0__MASK EQU 0x02 +SW2__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0 +SW2__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1 +SW2__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10 +SW2__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11 +SW2__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12 +SW2__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13 +SW2__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14 +SW2__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2 +SW2__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3 +SW2__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4 +SW2__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5 +SW2__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6 +SW2__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7 +SW2__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8 +SW2__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9 +SW2__0__PC EQU CYREG_GPIO_PRT0_PC +SW2__0__PC2 EQU CYREG_GPIO_PRT0_PC2 +SW2__0__PORT EQU 0 +SW2__0__PS EQU CYREG_GPIO_PRT0_PS +SW2__0__SHIFT EQU 1 +SW2__DR EQU CYREG_GPIO_PRT0_DR +SW2__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR +SW2__DR_INV EQU CYREG_GPIO_PRT0_DR_INV +SW2__DR_SET EQU CYREG_GPIO_PRT0_DR_SET +SW2__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__INTR EQU CYREG_GPIO_PRT0_INTR +SW2__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__INTSTAT EQU CYREG_GPIO_PRT0_INTR +SW2__MASK EQU 0x02 +SW2__PA__CFG0 EQU CYREG_UDB_PA0_CFG0 +SW2__PA__CFG1 EQU CYREG_UDB_PA0_CFG1 +SW2__PA__CFG10 EQU CYREG_UDB_PA0_CFG10 +SW2__PA__CFG11 EQU CYREG_UDB_PA0_CFG11 +SW2__PA__CFG12 EQU CYREG_UDB_PA0_CFG12 +SW2__PA__CFG13 EQU CYREG_UDB_PA0_CFG13 +SW2__PA__CFG14 EQU CYREG_UDB_PA0_CFG14 +SW2__PA__CFG2 EQU CYREG_UDB_PA0_CFG2 +SW2__PA__CFG3 EQU CYREG_UDB_PA0_CFG3 +SW2__PA__CFG4 EQU CYREG_UDB_PA0_CFG4 +SW2__PA__CFG5 EQU CYREG_UDB_PA0_CFG5 +SW2__PA__CFG6 EQU CYREG_UDB_PA0_CFG6 +SW2__PA__CFG7 EQU CYREG_UDB_PA0_CFG7 +SW2__PA__CFG8 EQU CYREG_UDB_PA0_CFG8 +SW2__PA__CFG9 EQU CYREG_UDB_PA0_CFG9 +SW2__PC EQU CYREG_GPIO_PRT0_PC +SW2__PC2 EQU CYREG_GPIO_PRT0_PC2 +SW2__PORT EQU 0 +SW2__PS EQU CYREG_GPIO_PRT0_PS +SW2__SHIFT EQU 1 +SW2__SNAP EQU CYREG_GPIO_PRT0_INTR /* UART_DEB */ UART_DEB_rx__0__DR EQU CYREG_GPIO_PRT1_DR @@ -991,9 +779,9 @@ UART_DEB_tx__SHIFT EQU 5 /* Wakeup_Interrupt */ Wakeup_Interrupt__INTC_CLR_EN_REG EQU CYREG_CM0_ICER Wakeup_Interrupt__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR -Wakeup_Interrupt__INTC_MASK EQU 0x04 -Wakeup_Interrupt__INTC_NUMBER EQU 2 -Wakeup_Interrupt__INTC_PRIOR_MASK EQU 0xC00000 +Wakeup_Interrupt__INTC_MASK EQU 0x01 +Wakeup_Interrupt__INTC_NUMBER EQU 0 +Wakeup_Interrupt__INTC_PRIOR_MASK EQU 0xC0 Wakeup_Interrupt__INTC_PRIOR_NUM EQU 3 Wakeup_Interrupt__INTC_PRIOR_REG EQU CYREG_CM0_IPR0 Wakeup_Interrupt__INTC_SET_EN_REG EQU CYREG_CM0_ISER @@ -1021,7 +809,7 @@ CYDEV_CHIP_FAMILY_PSOC5 EQU 3 CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 -CYDEV_CHIP_JTAG_ID EQU 0x1A1711AA +CYDEV_CHIP_JTAG_ID EQU 0x0E49119E CYDEV_CHIP_MEMBER_3A EQU 1 CYDEV_CHIP_MEMBER_4A EQU 18 CYDEV_CHIP_MEMBER_4D EQU 13 @@ -1112,7 +900,7 @@ CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4F_PRODUCTION CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED CYDEV_CONFIG_READ_ACCELERATOR EQU 1 CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 @@ -1134,11 +922,9 @@ CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD CYDEV_DEBUGGING_ENABLE EQU 1 CYDEV_DFT_SELECT_CLK0 EQU 10 CYDEV_DFT_SELECT_CLK1 EQU 11 -CYDEV_DMA_CHANNELS_AVAILABLE EQU 8 CYDEV_HEAP_SIZE EQU 0x400 CYDEV_IMO_TRIMMED_BY_USB EQU 0 CYDEV_IMO_TRIMMED_BY_WCO EQU 0 -CYDEV_INTR_NUMBER_DMA EQU 21 CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 0 @@ -1151,11 +937,11 @@ CYDEV_PROJ_TYPE_STANDARD EQU 0 CYDEV_STACK_SIZE EQU 0x0800 CYDEV_USE_BUNDLED_CMSIS EQU 1 CYDEV_VARIABLE_VDDA EQU 1 +CYDEV_VDD_MV EQU 3300 CYDEV_VDDA_MV EQU 3300 -CYDEV_VDDD_MV EQU 3300 CYDEV_VDDR_MV EQU 3300 CYDEV_WDT_GENERATE_ISR EQU 1 -CYIPBLOCK_m0s8bless_VERSION EQU 2 +CYIPBLOCK_m0s8bless_VERSION EQU 1 CYIPBLOCK_m0s8cpussv2_VERSION EQU 1 CYIPBLOCK_m0s8csd_VERSION EQU 1 CYIPBLOCK_m0s8ioss_VERSION EQU 1 @@ -1167,7 +953,6 @@ CYIPBLOCK_m0s8srssv2_VERSION EQU 1 CYIPBLOCK_m0s8tcpwm_VERSION EQU 2 CYIPBLOCK_m0s8udbif_VERSION EQU 1 CYIPBLOCK_s8pass4al_VERSION EQU 1 -DMA_CHANNELS_USED__MASK EQU 0 CYDEV_BOOTLOADER_ENABLE EQU 0 #endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyfitterrv.inc b/BLE.cydsn/Generated_Source/PSoC4/cyfitterrv.inc index 37988fa..887a709 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyfitterrv.inc +++ b/BLE.cydsn/Generated_Source/PSoC4/cyfitterrv.inc @@ -38,8 +38,6 @@ BLE_cy_m0s8_ble__ADV_PARAMS EQU CYREG_BLE_BLELL_ADV_PARAMS BLE_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO EQU CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO BLE_cy_m0s8_ble__ADV_TX_DATA_FIFO EQU CYREG_BLE_BLELL_ADV_TX_DATA_FIFO BLE_cy_m0s8_ble__AGC EQU CYREG_BLE_BLERD_AGC -BLE_cy_m0s8_ble__AGC_GAIN_COMP_1 EQU CYREG_BLE_BLERD_AGC_GAIN_COMP_1 -BLE_cy_m0s8_ble__AGC_GAIN_COMP_2 EQU CYREG_BLE_BLERD_AGC_GAIN_COMP_2 BLE_cy_m0s8_ble__BALUN EQU CYREG_BLE_BLERD_BALUN BLE_cy_m0s8_ble__BB_BUMP1 EQU CYREG_BLE_BLERD_BB_BUMP1 BLE_cy_m0s8_ble__BB_BUMP2 EQU CYREG_BLE_BLERD_BB_BUMP2 @@ -81,10 +79,8 @@ BLE_cy_m0s8_ble__CONN_REQ_WORD7 EQU CYREG_BLE_BLELL_CONN_REQ_WORD7 BLE_cy_m0s8_ble__CONN_REQ_WORD8 EQU CYREG_BLE_BLELL_CONN_REQ_WORD8 BLE_cy_m0s8_ble__CONN_REQ_WORD9 EQU CYREG_BLE_BLELL_CONN_REQ_WORD9 BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR EQU CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR -BLE_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR_DLE EQU CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE BLE_cy_m0s8_ble__CONN_STATUS EQU CYREG_BLE_BLELL_CONN_STATUS BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR EQU CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR -BLE_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR_DLE EQU CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE BLE_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL BLE_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY BLE_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL EQU CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL @@ -124,9 +120,6 @@ BLE_cy_m0s8_ble__DBG_BB EQU CYREG_BLE_BLERD_DBG_BB BLE_cy_m0s8_ble__DBUS EQU CYREG_BLE_BLERD_DBUS BLE_cy_m0s8_ble__DC EQU CYREG_BLE_BLERD_DC BLE_cy_m0s8_ble__DCCAL EQU CYREG_BLE_BLERD_DCCAL -BLE_cy_m0s8_ble__DEV_PA_ADDR_H EQU CYREG_BLE_BLELL_DEV_PA_ADDR_H -BLE_cy_m0s8_ble__DEV_PA_ADDR_L EQU CYREG_BLE_BLELL_DEV_PA_ADDR_L -BLE_cy_m0s8_ble__DEV_PA_ADDR_M EQU CYREG_BLE_BLELL_DEV_PA_ADDR_M BLE_cy_m0s8_ble__DEV_PUB_ADDR_H EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_H BLE_cy_m0s8_ble__DEV_PUB_ADDR_L EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_L BLE_cy_m0s8_ble__DEV_PUB_ADDR_M EQU CYREG_BLE_BLELL_DEV_PUB_ADDR_M @@ -153,7 +146,6 @@ BLE_cy_m0s8_ble__ENC_KEY4 EQU CYREG_BLE_BLELL_ENC_KEY4 BLE_cy_m0s8_ble__ENC_KEY5 EQU CYREG_BLE_BLELL_ENC_KEY5 BLE_cy_m0s8_ble__ENC_KEY6 EQU CYREG_BLE_BLELL_ENC_KEY6 BLE_cy_m0s8_ble__ENC_KEY7 EQU CYREG_BLE_BLELL_ENC_KEY7 -BLE_cy_m0s8_ble__ENC_MEM_BASE_ADDR EQU CYREG_BLE_BLELL_ENC_MEM_BASE_ADDR BLE_cy_m0s8_ble__ENC_PARAMS EQU CYREG_BLE_BLELL_ENC_PARAMS BLE_cy_m0s8_ble__EVENT_ENABLE EQU CYREG_BLE_BLELL_EVENT_ENABLE BLE_cy_m0s8_ble__EVENT_INTR EQU CYREG_BLE_BLELL_EVENT_INTR @@ -181,10 +173,8 @@ BLE_cy_m0s8_ble__LE_PING_TIMER_NEXT_EXP EQU CYREG_BLE_BLELL_LE_PING_TIMER_NEXT_E BLE_cy_m0s8_ble__LE_PING_TIMER_OFFSET EQU CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET BLE_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT EQU CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT BLE_cy_m0s8_ble__LE_RF_TEST_MODE EQU CYREG_BLE_BLELL_LE_RF_TEST_MODE -BLE_cy_m0s8_ble__LE_RF_TEST_MODE_EXT EQU CYREG_BLE_BLELL_LE_RF_TEST_MODE_EXT BLE_cy_m0s8_ble__LF_CLK_CTRL EQU CYREG_BLE_BLESS_LF_CLK_CTRL BLE_cy_m0s8_ble__LL_CLK_EN EQU CYREG_BLE_BLESS_LL_CLK_EN -BLE_cy_m0s8_ble__LL_CONTROL EQU CYREG_BLE_BLELL_LL_CONTROL BLE_cy_m0s8_ble__LL_DSM_CTRL EQU CYREG_BLE_BLESS_LL_DSM_CTRL BLE_cy_m0s8_ble__LL_DSM_INTR_STAT EQU CYREG_BLE_BLESS_LL_DSM_INTR_STAT BLE_cy_m0s8_ble__LLH_FEATURE_CONFIG EQU CYREG_BLE_BLELL_LLH_FEATURE_CONFIG @@ -198,7 +188,6 @@ BLE_cy_m0s8_ble__NEXT_CE_INSTANT EQU CYREG_BLE_BLELL_NEXT_CE_INSTANT BLE_cy_m0s8_ble__NEXT_RESP_TIMER_EXP EQU CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP BLE_cy_m0s8_ble__NEXT_SUP_TO EQU CYREG_BLE_BLELL_NEXT_SUP_TO BLE_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT EQU CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT -BLE_cy_m0s8_ble__PA_RSSI_NEW EQU CYREG_BLE_BLERD_PA_RSSI_NEW BLE_cy_m0s8_ble__PACKET_COUNTER0 EQU CYREG_BLE_BLELL_PACKET_COUNTER0 BLE_cy_m0s8_ble__PACKET_COUNTER1 EQU CYREG_BLE_BLELL_PACKET_COUNTER1 BLE_cy_m0s8_ble__PACKET_COUNTER2 EQU CYREG_BLE_BLELL_PACKET_COUNTER2 @@ -217,18 +206,6 @@ BLE_cy_m0s8_ble__READ_IQ_4 EQU CYREG_BLE_BLERD_READ_IQ_4 BLE_cy_m0s8_ble__RECEIVE_TRIG_CTRL EQU CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL BLE_cy_m0s8_ble__RF_CONFIG EQU CYREG_BLE_BLESS_RF_CONFIG BLE_cy_m0s8_ble__RMAP EQU CYREG_BLE_BLERD_RMAP -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE0 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE0 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE1 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE1 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE2 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE2 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE3 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE3 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE4 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE4 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE5 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE5 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE6 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE6 -BLE_cy_m0s8_ble__RSLV_LIST_ENABLE7 EQU CYREG_BLE_BLELL_RSLV_LIST_ENABLE7 -BLE_cy_m0s8_ble__RSLV_LIST_PEER_IDNTT_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR -BLE_cy_m0s8_ble__RSLV_LIST_PEER_RPA_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR -BLE_cy_m0s8_ble__RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR -BLE_cy_m0s8_ble__RSLV_LIST_TX_INIT_RPA_BASE_ADDR EQU CYREG_BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR BLE_cy_m0s8_ble__RSSI EQU CYREG_BLE_BLERD_RSSI BLE_cy_m0s8_ble__RX EQU CYREG_BLE_BLERD_RX BLE_cy_m0s8_ble__RX_BUMP1 EQU CYREG_BLE_BLERD_RX_BUMP1 @@ -508,257 +485,68 @@ SCB_sda__PS EQU CYREG_GPIO_PRT3_PS SCB_sda__SHIFT EQU 4 ; SW2 -SW2__0__DR EQU CYREG_GPIO_PRT2_DR -SW2__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -SW2__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -SW2__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -SW2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 -SW2__0__HSIOM_MASK EQU 0xF0000000 -SW2__0__HSIOM_SHIFT EQU 28 -SW2__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__0__INTR EQU CYREG_GPIO_PRT2_INTR -SW2__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR -SW2__0__MASK EQU 0x80 -SW2__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -SW2__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -SW2__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -SW2__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -SW2__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -SW2__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -SW2__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -SW2__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -SW2__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -SW2__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -SW2__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -SW2__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -SW2__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -SW2__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -SW2__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -SW2__0__PC EQU CYREG_GPIO_PRT2_PC -SW2__0__PC2 EQU CYREG_GPIO_PRT2_PC2 -SW2__0__PORT EQU 2 -SW2__0__PS EQU CYREG_GPIO_PRT2_PS -SW2__0__SHIFT EQU 7 -SW2__DR EQU CYREG_GPIO_PRT2_DR -SW2__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -SW2__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -SW2__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -SW2__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__INTR EQU CYREG_GPIO_PRT2_INTR -SW2__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -SW2__INTSTAT EQU CYREG_GPIO_PRT2_INTR -SW2__MASK EQU 0x80 -SW2__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -SW2__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -SW2__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -SW2__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -SW2__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -SW2__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -SW2__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -SW2__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -SW2__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -SW2__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -SW2__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -SW2__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -SW2__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -SW2__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -SW2__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -SW2__PC EQU CYREG_GPIO_PRT2_PC -SW2__PC2 EQU CYREG_GPIO_PRT2_PC2 -SW2__PORT EQU 2 -SW2__PS EQU CYREG_GPIO_PRT2_PS -SW2__SHIFT EQU 7 -SW2__SNAP EQU CYREG_GPIO_PRT2_INTR - -; LED_BLU -LED_BLU__0__DR EQU CYREG_GPIO_PRT3_DR -LED_BLU__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_BLU__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_BLU__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_BLU__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 -LED_BLU__0__HSIOM_MASK EQU 0xF0000000 -LED_BLU__0__HSIOM_SHIFT EQU 28 -LED_BLU__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__0__INTR EQU CYREG_GPIO_PRT3_INTR -LED_BLU__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_BLU__0__MASK EQU 0x80 -LED_BLU__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_BLU__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_BLU__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_BLU__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_BLU__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_BLU__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_BLU__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_BLU__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_BLU__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_BLU__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_BLU__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_BLU__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_BLU__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_BLU__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_BLU__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_BLU__0__PC EQU CYREG_GPIO_PRT3_PC -LED_BLU__0__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_BLU__0__PORT EQU 3 -LED_BLU__0__PS EQU CYREG_GPIO_PRT3_PS -LED_BLU__0__SHIFT EQU 7 -LED_BLU__DR EQU CYREG_GPIO_PRT3_DR -LED_BLU__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_BLU__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_BLU__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_BLU__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__INTR EQU CYREG_GPIO_PRT3_INTR -LED_BLU__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_BLU__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_BLU__MASK EQU 0x80 -LED_BLU__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_BLU__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_BLU__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_BLU__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_BLU__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_BLU__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_BLU__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_BLU__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_BLU__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_BLU__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_BLU__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_BLU__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_BLU__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_BLU__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_BLU__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_BLU__PC EQU CYREG_GPIO_PRT3_PC -LED_BLU__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_BLU__PORT EQU 3 -LED_BLU__PS EQU CYREG_GPIO_PRT3_PS -LED_BLU__SHIFT EQU 7 - -; LED_GRN -LED_GRN__0__DR EQU CYREG_GPIO_PRT3_DR -LED_GRN__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_GRN__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_GRN__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_GRN__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3 -LED_GRN__0__HSIOM_MASK EQU 0x0F000000 -LED_GRN__0__HSIOM_SHIFT EQU 24 -LED_GRN__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__0__INTR EQU CYREG_GPIO_PRT3_INTR -LED_GRN__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_GRN__0__MASK EQU 0x40 -LED_GRN__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_GRN__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_GRN__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_GRN__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_GRN__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_GRN__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_GRN__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_GRN__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_GRN__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_GRN__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_GRN__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_GRN__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_GRN__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_GRN__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_GRN__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_GRN__0__PC EQU CYREG_GPIO_PRT3_PC -LED_GRN__0__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_GRN__0__PORT EQU 3 -LED_GRN__0__PS EQU CYREG_GPIO_PRT3_PS -LED_GRN__0__SHIFT EQU 6 -LED_GRN__DR EQU CYREG_GPIO_PRT3_DR -LED_GRN__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR -LED_GRN__DR_INV EQU CYREG_GPIO_PRT3_DR_INV -LED_GRN__DR_SET EQU CYREG_GPIO_PRT3_DR_SET -LED_GRN__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__INTR EQU CYREG_GPIO_PRT3_INTR -LED_GRN__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG -LED_GRN__INTSTAT EQU CYREG_GPIO_PRT3_INTR -LED_GRN__MASK EQU 0x40 -LED_GRN__PA__CFG0 EQU CYREG_UDB_PA3_CFG0 -LED_GRN__PA__CFG1 EQU CYREG_UDB_PA3_CFG1 -LED_GRN__PA__CFG10 EQU CYREG_UDB_PA3_CFG10 -LED_GRN__PA__CFG11 EQU CYREG_UDB_PA3_CFG11 -LED_GRN__PA__CFG12 EQU CYREG_UDB_PA3_CFG12 -LED_GRN__PA__CFG13 EQU CYREG_UDB_PA3_CFG13 -LED_GRN__PA__CFG14 EQU CYREG_UDB_PA3_CFG14 -LED_GRN__PA__CFG2 EQU CYREG_UDB_PA3_CFG2 -LED_GRN__PA__CFG3 EQU CYREG_UDB_PA3_CFG3 -LED_GRN__PA__CFG4 EQU CYREG_UDB_PA3_CFG4 -LED_GRN__PA__CFG5 EQU CYREG_UDB_PA3_CFG5 -LED_GRN__PA__CFG6 EQU CYREG_UDB_PA3_CFG6 -LED_GRN__PA__CFG7 EQU CYREG_UDB_PA3_CFG7 -LED_GRN__PA__CFG8 EQU CYREG_UDB_PA3_CFG8 -LED_GRN__PA__CFG9 EQU CYREG_UDB_PA3_CFG9 -LED_GRN__PC EQU CYREG_GPIO_PRT3_PC -LED_GRN__PC2 EQU CYREG_GPIO_PRT3_PC2 -LED_GRN__PORT EQU 3 -LED_GRN__PS EQU CYREG_GPIO_PRT3_PS -LED_GRN__SHIFT EQU 6 - -; LED_RED -LED_RED__0__DR EQU CYREG_GPIO_PRT2_DR -LED_RED__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -LED_RED__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -LED_RED__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -LED_RED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2 -LED_RED__0__HSIOM_MASK EQU 0x0F000000 -LED_RED__0__HSIOM_SHIFT EQU 24 -LED_RED__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__0__INTR EQU CYREG_GPIO_PRT2_INTR -LED_RED__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR -LED_RED__0__MASK EQU 0x40 -LED_RED__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -LED_RED__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -LED_RED__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -LED_RED__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -LED_RED__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -LED_RED__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -LED_RED__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -LED_RED__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -LED_RED__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -LED_RED__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -LED_RED__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -LED_RED__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -LED_RED__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -LED_RED__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -LED_RED__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -LED_RED__0__PC EQU CYREG_GPIO_PRT2_PC -LED_RED__0__PC2 EQU CYREG_GPIO_PRT2_PC2 -LED_RED__0__PORT EQU 2 -LED_RED__0__PS EQU CYREG_GPIO_PRT2_PS -LED_RED__0__SHIFT EQU 6 -LED_RED__DR EQU CYREG_GPIO_PRT2_DR -LED_RED__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR -LED_RED__DR_INV EQU CYREG_GPIO_PRT2_DR_INV -LED_RED__DR_SET EQU CYREG_GPIO_PRT2_DR_SET -LED_RED__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__INTR EQU CYREG_GPIO_PRT2_INTR -LED_RED__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG -LED_RED__INTSTAT EQU CYREG_GPIO_PRT2_INTR -LED_RED__MASK EQU 0x40 -LED_RED__PA__CFG0 EQU CYREG_UDB_PA2_CFG0 -LED_RED__PA__CFG1 EQU CYREG_UDB_PA2_CFG1 -LED_RED__PA__CFG10 EQU CYREG_UDB_PA2_CFG10 -LED_RED__PA__CFG11 EQU CYREG_UDB_PA2_CFG11 -LED_RED__PA__CFG12 EQU CYREG_UDB_PA2_CFG12 -LED_RED__PA__CFG13 EQU CYREG_UDB_PA2_CFG13 -LED_RED__PA__CFG14 EQU CYREG_UDB_PA2_CFG14 -LED_RED__PA__CFG2 EQU CYREG_UDB_PA2_CFG2 -LED_RED__PA__CFG3 EQU CYREG_UDB_PA2_CFG3 -LED_RED__PA__CFG4 EQU CYREG_UDB_PA2_CFG4 -LED_RED__PA__CFG5 EQU CYREG_UDB_PA2_CFG5 -LED_RED__PA__CFG6 EQU CYREG_UDB_PA2_CFG6 -LED_RED__PA__CFG7 EQU CYREG_UDB_PA2_CFG7 -LED_RED__PA__CFG8 EQU CYREG_UDB_PA2_CFG8 -LED_RED__PA__CFG9 EQU CYREG_UDB_PA2_CFG9 -LED_RED__PC EQU CYREG_GPIO_PRT2_PC -LED_RED__PC2 EQU CYREG_GPIO_PRT2_PC2 -LED_RED__PORT EQU 2 -LED_RED__PS EQU CYREG_GPIO_PRT2_PS -LED_RED__SHIFT EQU 6 +SW2__0__DR EQU CYREG_GPIO_PRT0_DR +SW2__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR +SW2__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV +SW2__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET +SW2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0 +SW2__0__HSIOM_MASK EQU 0x000000F0 +SW2__0__HSIOM_SHIFT EQU 4 +SW2__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__0__INTR EQU CYREG_GPIO_PRT0_INTR +SW2__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR +SW2__0__MASK EQU 0x02 +SW2__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0 +SW2__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1 +SW2__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10 +SW2__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11 +SW2__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12 +SW2__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13 +SW2__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14 +SW2__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2 +SW2__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3 +SW2__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4 +SW2__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5 +SW2__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6 +SW2__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7 +SW2__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8 +SW2__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9 +SW2__0__PC EQU CYREG_GPIO_PRT0_PC +SW2__0__PC2 EQU CYREG_GPIO_PRT0_PC2 +SW2__0__PORT EQU 0 +SW2__0__PS EQU CYREG_GPIO_PRT0_PS +SW2__0__SHIFT EQU 1 +SW2__DR EQU CYREG_GPIO_PRT0_DR +SW2__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR +SW2__DR_INV EQU CYREG_GPIO_PRT0_DR_INV +SW2__DR_SET EQU CYREG_GPIO_PRT0_DR_SET +SW2__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__INTR EQU CYREG_GPIO_PRT0_INTR +SW2__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG +SW2__INTSTAT EQU CYREG_GPIO_PRT0_INTR +SW2__MASK EQU 0x02 +SW2__PA__CFG0 EQU CYREG_UDB_PA0_CFG0 +SW2__PA__CFG1 EQU CYREG_UDB_PA0_CFG1 +SW2__PA__CFG10 EQU CYREG_UDB_PA0_CFG10 +SW2__PA__CFG11 EQU CYREG_UDB_PA0_CFG11 +SW2__PA__CFG12 EQU CYREG_UDB_PA0_CFG12 +SW2__PA__CFG13 EQU CYREG_UDB_PA0_CFG13 +SW2__PA__CFG14 EQU CYREG_UDB_PA0_CFG14 +SW2__PA__CFG2 EQU CYREG_UDB_PA0_CFG2 +SW2__PA__CFG3 EQU CYREG_UDB_PA0_CFG3 +SW2__PA__CFG4 EQU CYREG_UDB_PA0_CFG4 +SW2__PA__CFG5 EQU CYREG_UDB_PA0_CFG5 +SW2__PA__CFG6 EQU CYREG_UDB_PA0_CFG6 +SW2__PA__CFG7 EQU CYREG_UDB_PA0_CFG7 +SW2__PA__CFG8 EQU CYREG_UDB_PA0_CFG8 +SW2__PA__CFG9 EQU CYREG_UDB_PA0_CFG9 +SW2__PC EQU CYREG_GPIO_PRT0_PC +SW2__PC2 EQU CYREG_GPIO_PRT0_PC2 +SW2__PORT EQU 0 +SW2__PS EQU CYREG_GPIO_PRT0_PS +SW2__SHIFT EQU 1 +SW2__SNAP EQU CYREG_GPIO_PRT0_INTR ; UART_DEB UART_DEB_rx__0__DR EQU CYREG_GPIO_PRT1_DR @@ -991,9 +779,9 @@ UART_DEB_tx__SHIFT EQU 5 ; Wakeup_Interrupt Wakeup_Interrupt__INTC_CLR_EN_REG EQU CYREG_CM0_ICER Wakeup_Interrupt__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR -Wakeup_Interrupt__INTC_MASK EQU 0x04 -Wakeup_Interrupt__INTC_NUMBER EQU 2 -Wakeup_Interrupt__INTC_PRIOR_MASK EQU 0xC00000 +Wakeup_Interrupt__INTC_MASK EQU 0x01 +Wakeup_Interrupt__INTC_NUMBER EQU 0 +Wakeup_Interrupt__INTC_PRIOR_MASK EQU 0xC0 Wakeup_Interrupt__INTC_PRIOR_NUM EQU 3 Wakeup_Interrupt__INTC_PRIOR_REG EQU CYREG_CM0_IPR0 Wakeup_Interrupt__INTC_SET_EN_REG EQU CYREG_CM0_ISER @@ -1021,7 +809,7 @@ CYDEV_CHIP_FAMILY_PSOC5 EQU 3 CYDEV_CHIP_FAMILY_PSOC6 EQU 4 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4 -CYDEV_CHIP_JTAG_ID EQU 0x1A1711AA +CYDEV_CHIP_JTAG_ID EQU 0x0E49119E CYDEV_CHIP_MEMBER_3A EQU 1 CYDEV_CHIP_MEMBER_4A EQU 18 CYDEV_CHIP_MEMBER_4D EQU 13 @@ -1112,7 +900,7 @@ CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4F_PRODUCTION CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED CYDEV_CONFIG_READ_ACCELERATOR EQU 1 CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 @@ -1134,11 +922,9 @@ CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD CYDEV_DEBUGGING_ENABLE EQU 1 CYDEV_DFT_SELECT_CLK0 EQU 10 CYDEV_DFT_SELECT_CLK1 EQU 11 -CYDEV_DMA_CHANNELS_AVAILABLE EQU 8 CYDEV_HEAP_SIZE EQU 0x400 CYDEV_IMO_TRIMMED_BY_USB EQU 0 CYDEV_IMO_TRIMMED_BY_WCO EQU 0 -CYDEV_INTR_NUMBER_DMA EQU 21 CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 0 @@ -1151,11 +937,11 @@ CYDEV_PROJ_TYPE_STANDARD EQU 0 CYDEV_STACK_SIZE EQU 0x0800 CYDEV_USE_BUNDLED_CMSIS EQU 1 CYDEV_VARIABLE_VDDA EQU 1 +CYDEV_VDD_MV EQU 3300 CYDEV_VDDA_MV EQU 3300 -CYDEV_VDDD_MV EQU 3300 CYDEV_VDDR_MV EQU 3300 CYDEV_WDT_GENERATE_ISR EQU 1 -CYIPBLOCK_m0s8bless_VERSION EQU 2 +CYIPBLOCK_m0s8bless_VERSION EQU 1 CYIPBLOCK_m0s8cpussv2_VERSION EQU 1 CYIPBLOCK_m0s8csd_VERSION EQU 1 CYIPBLOCK_m0s8ioss_VERSION EQU 1 @@ -1167,7 +953,6 @@ CYIPBLOCK_m0s8srssv2_VERSION EQU 1 CYIPBLOCK_m0s8tcpwm_VERSION EQU 2 CYIPBLOCK_m0s8udbif_VERSION EQU 1 CYIPBLOCK_s8pass4al_VERSION EQU 1 -DMA_CHANNELS_USED__MASK EQU 0 CYDEV_BOOTLOADER_ENABLE EQU 0 ENDIF END diff --git a/BLE.cydsn/Generated_Source/PSoC4/cymetadata.c b/BLE.cydsn/Generated_Source/PSoC4/cymetadata.c index 28616cc..00305ff 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cymetadata.c +++ b/BLE.cydsn/Generated_Source/PSoC4/cymetadata.c @@ -58,7 +58,7 @@ CY_META_SECTION #error "Unsupported toolchain" #endif const uint8_t cy_metadata[] = { - 0x00u, 0x02u, 0x1Au, 0x17u, 0x11u, 0xAAu, 0x00u, 0x01u, + 0x00u, 0x02u, 0x0Eu, 0x49u, 0x11u, 0x9Eu, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u }; diff --git a/BLE.cydsn/Generated_Source/PSoC4/cypins.h b/BLE.cydsn/Generated_Source/PSoC4/cypins.h index 53a0b29..ba01b3d 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cypins.h +++ b/BLE.cydsn/Generated_Source/PSoC4/cypins.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for * port/pin in access and control. diff --git a/BLE.cydsn/Generated_Source/PSoC4/cytypes.h b/BLE.cydsn/Generated_Source/PSoC4/cytypes.h index d137563..3ae543c 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cytypes.h +++ b/BLE.cydsn/Generated_Source/PSoC4/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. @@ -219,10 +219,10 @@ /* Product uses FLASH-Lite or regular FLASH */ #if (CY_IP_HOBTO_DEVICE) #if (CY_IP_CPUSSV2) - #define CY_IP_FM (3 == 0) - #define CY_IP_FMLT (3 == 1) - #define CY_IP_FS (3 == 2) - #define CY_IP_FSLT (3 == 3) + #define CY_IP_FM (1 == 0) + #define CY_IP_FMLT (1 == 1) + #define CY_IP_FS (1 == 2) + #define CY_IP_FSLT (1 == 3) #else /* CY_IP_CPUSSV3 */ #define CY_IP_FM (-1 == 0) #define CY_IP_FMLT (-1 == 1) @@ -240,7 +240,7 @@ /* Enable simultaneous execution/programming in multi-macro devices */ #if (CY_IP_HOBTO_DEVICE) #if (CY_IP_CPUSSV2) - #define CY_IP_FLASH_PARALLEL_PGM_EN (0 == 1) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) #else /* CY_IP_CPUSSV3 */ #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) #endif /* (CY_IP_CPUSSV2) */ @@ -296,7 +296,7 @@ ***************************************************************************/ #if (CY_IP_HOBTO_DEVICE) #if (CY_IP_CPUSSV2) - #define CY_IP_SPCIF_SYNCHRONOUS (0 == 1) + #define CY_IP_SPCIF_SYNCHRONOUS (1 == 1) #else /* CY_IP_CPUSSV3 */ #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) #endif /* (CY_IP_CPUSSV2) */ @@ -423,7 +423,7 @@ /* DW/DMA Controller present (0=No, 1=Yes) */ #if (CY_IP_HOBTO_DEVICE) #if (CY_IP_CPUSSV2) - #define CY_IP_DMAC_PRESENT (1 == 1) + #define CY_IP_DMAC_PRESENT (0 == 1) #else #define CY_IP_DMAC_PRESENT (-1 == 1) #endif /* (CY_IP_CPUSSV2) */ diff --git a/BLE.cydsn/Generated_Source/PSoC4/cyutils.c b/BLE.cydsn/Generated_Source/PSoC4/cyutils.c index a9eb657..d66c618 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/cyutils.c +++ b/BLE.cydsn/Generated_Source/PSoC4/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/BLE.cydsn/Generated_Source/PSoC4/project.h b/BLE.cydsn/Generated_Source/PSoC4/project.h index 5739aca..228727e 100644 --- a/BLE.cydsn/Generated_Source/PSoC4/project.h +++ b/BLE.cydsn/Generated_Source/PSoC4/project.h @@ -47,12 +47,6 @@ #include "UART_DEB_SPI_UART_PVT.h" #include "UART_DEB_PVT.h" #include "UART_DEB_BOOT.h" -#include "LED_BLU.h" -#include "LED_BLU_aliases.h" -#include "LED_RED.h" -#include "LED_RED_aliases.h" -#include "LED_GRN.h" -#include "LED_GRN_aliases.h" #include "Wakeup_Interrupt.h" #include "SW2.h" #include "SW2_aliases.h" @@ -75,7 +69,6 @@ #include "cyPm.h" #include "cytypes.h" #include "cypins.h" -#include "CyDMA.h" #include "CyLFClk.h" /*[]*/ diff --git a/BLE.cydsn/TopDesign/TopDesign.cysch b/BLE.cydsn/TopDesign/TopDesign.cysch index ee8820a82612249ca251f55fafc409428377b949..1af4579d1530282252b807b94b01c4e0996627ee 100644 GIT binary patch delta 9582 zcmc(jX?Rpcy2nq|3EAibI^BdoLZ?HT#oPc1NW^XAA}Wk{l~o6>-~h_V1P0u$1SScf zA_ESA5=vx%2s5CANU%|mku4AcVMz!98alGeq97yc$UqY2t+%?mi>JQbxzBUIoKxrb z{{QvXcD9=3cWijaQ8p-@Y++Mrn*Vp{U!})<+~K>!ms%b54}NHK3v!P?@ySo^X3Z?i zYUZyP)R64Y{_R@YVu)>7ne`TFvV1`(vyusJf5U|NlsU#{va(6T*qh_K_IA|G5sPb^(W0rmyghOax|^_TLR6~^^vEnkjj&;4OtVn6gBg@`Zs zqs`jQ@ww(})r+z(xPT3rlSg*3Idf8DC=%Phc22h_;%8sYD`@edW`HuwsBG&mF6l$b zRR7KeS174sWeW$n&S)x8_65(fR*S~ORAG4&`##IX7A#6ixTNVWvGt46Vy~d$Y830X zy|ce@kxgSlgvBhrKQR$jlbWx@W@4nm27lID;|S}vFxr3m{RBHf)ni%Bf3(=t0Um$K zvVRhq+l-x@7cntX(kWa6%PDEa3QCh&bkwpyS@bdOj{2J2gfWJO^u(dAf|=~#5(3pU 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S(7D&q?%MzO%pG0NH1qETXhaeK diff --git a/BLE.cydsn/debug.c b/BLE.cydsn/debug.c index 684f1b4..5ba6c22 100644 --- a/BLE.cydsn/debug.c +++ b/BLE.cydsn/debug.c @@ -23,14 +23,14 @@ /* For GCC compiler revise _write() function for printf functionality */ int _write(int file, char *ptr, int len) { - LED_GRN_Write(LED_ON); +// LED_GRN_Write(LED_ON); int i; file = file; for (i = 0; i < len; i++) { UART_DEB_UartPutChar(*ptr++); } - LED_GRN_Write(LED_OFF); +// LED_GRN_Write(LED_OFF); return len; } @@ -65,9 +65,9 @@ void Set32ByPtr(uint8 ptr[], uint32 value) *******************************************************************************/ void ShowError(void) { - LED_RED_Write(LED_ON); - LED_GRN_Write(LED_ON); - LED_BLU_Write(LED_ON); +// LED_RED_Write(LED_ON); +// LED_GRN_Write(LED_ON); +// LED_BLU_Write(LED_ON); /* Halt CPU in Debug mode */ CYASSERT(0u != 0u); } diff --git a/BLE.cydsn/main.c b/BLE.cydsn/main.c index 2514633..72e6fe4 100644 --- a/BLE.cydsn/main.c +++ b/BLE.cydsn/main.c @@ -190,8 +190,8 @@ void AppCallBack(uint32 event, void* eventParam) * mode (Hibernate mode) and wait for an external * user event to wake up the device again */ DBG_PRINTF("Hibernate \r\n"); - LED_RED_Write(LED_OFF); - LED_GRN_Write(LED_ON); +// LED_RED_Write(LED_OFF); +// LED_GRN_Write(LED_ON); SW2_ClearInterrupt(); Wakeup_Interrupt_ClearPending(); Wakeup_Interrupt_Start(); @@ -204,7 +204,7 @@ void AppCallBack(uint32 event, void* eventParam) break; case CYBLE_EVT_GAP_DEVICE_CONNECTED: DBG_PRINTF("CYBLE_EVT_GAP_DEVICE_CONNECTED \r\n"); - LED_RED_Write(LED_OFF); +// LED_RED_Write(LED_OFF); break; case CYBLE_EVT_GAP_DEVICE_DISCONNECTED: DBG_PRINTF("CYBLE_EVT_GAP_DEVICE_DISCONNECTED\r\n"); @@ -438,7 +438,7 @@ void process_i2c() { Sup_Pdu_t i2c_inbox; uint8_t buf; uint32_t result = SCB_I2CMasterReadBuf(8, &buf, 1, SCB_I2C_MODE_COMPLETE_XFER); - LED_RED_Write(LED_ON); +// LED_RED_Write(LED_ON); if (0 == (result & SCB_I2C_MSTR_NOT_READY)) { uint16 i2c_counter = 0; while (--i2c_counter && 0 == (SCB_I2CMasterStatus() & SCB_I2C_MSTAT_RD_CMPLT)) {} @@ -482,9 +482,9 @@ int main() UART_DEB_Start(); DBG_PRINTF("CS BLE Project \r\n"); - LED_RED_Write(LED_OFF); - LED_GRN_Write(LED_OFF); - LED_BLU_Write(LED_OFF); +// LED_RED_Write(LED_OFF); +// LED_GRN_Write(LED_OFF); +// LED_BLU_Write(LED_OFF); /* Start CYBLE component and register generic event handler */ CyBle_Start(AppCallBack); @@ -494,7 +494,7 @@ int main() /* CyBle_ProcessEvents() allows BLE stack to process pending events */ CyBle_ProcessEvents(); process_i2c(); - LED_RED_Write(LED_OFF); +// LED_RED_Write(LED_OFF); /* To achieve low power in the device */ LowPowerImplementation(); diff --git a/BLE01_USB.cydsn/BLE01_USB.cydwr b/BLE01_USB.cydsn/BLE01_USB.cydwr index fdd4aa3..3c0652f 100644 --- a/BLE01_USB.cydsn/BLE01_USB.cydwr +++ b/BLE01_USB.cydsn/BLE01_USB.cydwr @@ -597,9 +597,9 @@ - + - + diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index 4678f1b..c27262c 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm3RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief ;* This Linker Descriptor file describes the memory layout of the PSoC5 diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3Start.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3Start.c index e212b6f..08339f6 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm3Start.c -* \version 5.70 +* \version 5.80 * * \brief * Startup code for the ARM CM3. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 8d69bbc..76dbdfd 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief * Assembly routines for GNU as. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s index 7bec1ab..9930057 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 6cf8bfc..d7a44db 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for RealView. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.c index 2b506a6..4395a21 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.c -* \version 5.70 +* \version 5.80 * * \brief * Provides an API for the DMAC component. The API includes functions for the diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.h index 071f489..1e44fc7 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the DMA Controller. * diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.c index efa7a67..f6ea8a5 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH/EEPROM. * diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.h index b3a05b4..9864d31 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH/EEPROM. * diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.c index af74c2c..705fb74 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, interrupts and watchdog timer. * diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.h index 49d23b3..e76a099 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the system, clocking, interrupts * and watchdog timer API. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.c index 7ba9fe3..f512f49 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the System Performance Component. * The SPC functions are not meant to be called directly by the user diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.h index 71b05e4..6feac37 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index dd1fd7b..1d8cb8c 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm3_psoc5.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSoC5. This includes types * necessary for core_cm3.h. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.c index dbf18a1..144ffdd 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.h index 1faee7a..ec05b4d 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/cypins.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/cypins.h index 0a3db2a..2a87f36 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/cypins.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for a * port/pin in access and control. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/cytypes.h b/BLE01_USB.cydsn/Generated_Source/PSoC5/cytypes.h index 52706aa..e135b5b 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. diff --git a/BLE01_USB.cydsn/Generated_Source/PSoC5/cyutils.c b/BLE01_USB.cydsn/Generated_Source/PSoC5/cyutils.c index 3345099..dadbd9f 100644 --- a/BLE01_USB.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/BLE01_USB.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/Bootloader.cydsn/Bootloader.cydwr b/Bootloader.cydsn/Bootloader.cydwr index efe8ec8..f066cd1 100644 --- a/Bootloader.cydsn/Bootloader.cydwr +++ b/Bootloader.cydsn/Bootloader.cydwr @@ -234,9 +234,9 @@ - + - + diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index f75fade..7e55785 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm3RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief ;* This Linker Descriptor file describes the memory layout of the PSoC5 diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c b/Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c index e212b6f..08339f6 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm3Start.c -* \version 5.70 +* \version 5.80 * * \brief * Startup code for the ARM CM3. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 8d69bbc..76dbdfd 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief * Assembly routines for GNU as. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s index 7bec1ab..9930057 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 6cf8bfc..d7a44db 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for RealView. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c b/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c index 2b506a6..4395a21 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.c -* \version 5.70 +* \version 5.80 * * \brief * Provides an API for the DMAC component. The API includes functions for the diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h b/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h index 071f489..1e44fc7 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the DMA Controller. * diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c b/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c index efa7a67..f6ea8a5 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH/EEPROM. * diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h b/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h index b3a05b4..9864d31 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH/EEPROM. * diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c b/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c index af74c2c..705fb74 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, interrupts and watchdog timer. * diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h b/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h index 49d23b3..e76a099 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the system, clocking, interrupts * and watchdog timer API. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c b/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c index 7ba9fe3..f512f49 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the System Performance Component. * The SPC functions are not meant to be called directly by the user diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h b/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h index 71b05e4..6feac37 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index dd1fd7b..1d8cb8c 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm3_psoc5.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSoC5. This includes types * necessary for core_cm3.h. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c b/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c index dbf18a1..144ffdd 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h b/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h index 1faee7a..ec05b4d 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/cypins.h b/Bootloader.cydsn/Generated_Source/PSoC5/cypins.h index 0a3db2a..2a87f36 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/cypins.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for a * port/pin in access and control. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h b/Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h index 52706aa..e135b5b 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. diff --git a/Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c b/Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c index 3345099..dadbd9f 100644 --- a/Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/CSSK.cydsn/CSSK.cydwr b/CSSK.cydsn/CSSK.cydwr index 1b328a8..3e2e255 100644 --- a/CSSK.cydsn/CSSK.cydwr +++ b/CSSK.cydsn/CSSK.cydwr @@ -597,9 +597,9 @@ - + - + diff --git a/CSSK.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/CSSK.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index 4678f1b..c27262c 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/CSSK.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm3RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief ;* This Linker Descriptor file describes the memory layout of the PSoC5 diff --git a/CSSK.cydsn/Generated_Source/PSoC5/Cm3Start.c b/CSSK.cydsn/Generated_Source/PSoC5/Cm3Start.c index e212b6f..08339f6 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm3Start.c -* \version 5.70 +* \version 5.80 * * \brief * Startup code for the ARM CM3. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 8d69bbc..76dbdfd 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief * Assembly routines for GNU as. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s index 7bec1ab..9930057 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 6cf8bfc..d7a44db 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for RealView. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.c b/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.c index 2b506a6..4395a21 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.c -* \version 5.70 +* \version 5.80 * * \brief * Provides an API for the DMAC component. The API includes functions for the diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.h b/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.h index 071f489..1e44fc7 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the DMA Controller. * diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.c b/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.c index efa7a67..f6ea8a5 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH/EEPROM. * diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.h b/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.h index b3a05b4..9864d31 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH/EEPROM. * diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyLib.c b/CSSK.cydsn/Generated_Source/PSoC5/CyLib.c index af74c2c..705fb74 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, interrupts and watchdog timer. * diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CyLib.h b/CSSK.cydsn/Generated_Source/PSoC5/CyLib.h index 49d23b3..e76a099 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the system, clocking, interrupts * and watchdog timer API. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CySpc.c b/CSSK.cydsn/Generated_Source/PSoC5/CySpc.c index 7ba9fe3..f512f49 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the System Performance Component. * The SPC functions are not meant to be called directly by the user diff --git a/CSSK.cydsn/Generated_Source/PSoC5/CySpc.h b/CSSK.cydsn/Generated_Source/PSoC5/CySpc.h index 71b05e4..6feac37 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user diff --git a/CSSK.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/CSSK.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index dd1fd7b..1d8cb8c 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm3_psoc5.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSoC5. This includes types * necessary for core_cm3.h. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/cyPm.c b/CSSK.cydsn/Generated_Source/PSoC5/cyPm.c index dbf18a1..144ffdd 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * diff --git a/CSSK.cydsn/Generated_Source/PSoC5/cyPm.h b/CSSK.cydsn/Generated_Source/PSoC5/cyPm.h index 1faee7a..ec05b4d 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * diff --git a/CSSK.cydsn/Generated_Source/PSoC5/cypins.h b/CSSK.cydsn/Generated_Source/PSoC5/cypins.h index 0a3db2a..2a87f36 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/cypins.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for a * port/pin in access and control. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/cytypes.h b/CSSK.cydsn/Generated_Source/PSoC5/cytypes.h index 52706aa..e135b5b 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/CSSK.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. diff --git a/CSSK.cydsn/Generated_Source/PSoC5/cyutils.c b/CSSK.cydsn/Generated_Source/PSoC5/cyutils.c index 3345099..dadbd9f 100644 --- a/CSSK.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/CSSK.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/CommonSense.cywrk b/CommonSense.cywrk index 0b0c42a..1f221e6 100644 --- a/CommonSense.cywrk +++ b/CommonSense.cywrk @@ -3,7 +3,7 @@ - + diff --git a/Firmware.cydsn/Firmware.cydwr b/Firmware.cydsn/Firmware.cydwr index f2dc7de..644cbd8 100644 --- a/Firmware.cydsn/Firmware.cydwr +++ b/Firmware.cydsn/Firmware.cydwr @@ -597,9 +597,9 @@ - + - + diff --git a/Firmware.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/Firmware.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index 1e1236d..678df8e 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/Firmware.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm3RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief ;* This Linker Descriptor file describes the memory layout of the PSoC5 diff --git a/Firmware.cydsn/Generated_Source/PSoC5/Cm3Start.c b/Firmware.cydsn/Generated_Source/PSoC5/Cm3Start.c index e212b6f..08339f6 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm3Start.c -* \version 5.70 +* \version 5.80 * * \brief * Startup code for the ARM CM3. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 8d69bbc..76dbdfd 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief * Assembly routines for GNU as. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s index 7bec1ab..9930057 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 6cf8bfc..d7a44db 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for RealView. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.c b/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.c index 2b506a6..4395a21 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.c -* \version 5.70 +* \version 5.80 * * \brief * Provides an API for the DMAC component. The API includes functions for the diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.h b/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.h index 071f489..1e44fc7 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the DMA Controller. * diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.c b/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.c index efa7a67..f6ea8a5 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH/EEPROM. * diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.h b/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.h index b3a05b4..9864d31 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH/EEPROM. * diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyLib.c b/Firmware.cydsn/Generated_Source/PSoC5/CyLib.c index af74c2c..705fb74 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, interrupts and watchdog timer. * diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CyLib.h b/Firmware.cydsn/Generated_Source/PSoC5/CyLib.h index 49d23b3..e76a099 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the system, clocking, interrupts * and watchdog timer API. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CySpc.c b/Firmware.cydsn/Generated_Source/PSoC5/CySpc.c index 7ba9fe3..f512f49 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the System Performance Component. * The SPC functions are not meant to be called directly by the user diff --git a/Firmware.cydsn/Generated_Source/PSoC5/CySpc.h b/Firmware.cydsn/Generated_Source/PSoC5/CySpc.h index 71b05e4..6feac37 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user diff --git a/Firmware.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/Firmware.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index dd1fd7b..1d8cb8c 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm3_psoc5.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSoC5. This includes types * necessary for core_cm3.h. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/cyPm.c b/Firmware.cydsn/Generated_Source/PSoC5/cyPm.c index dbf18a1..144ffdd 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * diff --git a/Firmware.cydsn/Generated_Source/PSoC5/cyPm.h b/Firmware.cydsn/Generated_Source/PSoC5/cyPm.h index 1faee7a..ec05b4d 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * diff --git a/Firmware.cydsn/Generated_Source/PSoC5/cypins.h b/Firmware.cydsn/Generated_Source/PSoC5/cypins.h index 0a3db2a..2a87f36 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/cypins.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for a * port/pin in access and control. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/cytypes.h b/Firmware.cydsn/Generated_Source/PSoC5/cytypes.h index 52706aa..e135b5b 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/Firmware.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. diff --git a/Firmware.cydsn/Generated_Source/PSoC5/cyutils.c b/Firmware.cydsn/Generated_Source/PSoC5/cyutils.c index 3345099..dadbd9f 100644 --- a/Firmware.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/Firmware.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index 05c1f17..92a9954 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm3RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief ;* This Linker Descriptor file describes the memory layout of the PSoC5 diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3Start.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3Start.c index e212b6f..08339f6 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm3Start.c -* \version 5.70 +* \version 5.80 * * \brief * Startup code for the ARM CM3. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 8d69bbc..76dbdfd 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief * Assembly routines for GNU as. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s index 7bec1ab..9930057 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 6cf8bfc..d7a44db 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for RealView. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.c index 2b506a6..4395a21 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.c -* \version 5.70 +* \version 5.80 * * \brief * Provides an API for the DMAC component. The API includes functions for the diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.h index 071f489..1e44fc7 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the DMA Controller. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.c index efa7a67..f6ea8a5 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH/EEPROM. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.h index b3a05b4..9864d31 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH/EEPROM. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.c index af74c2c..705fb74 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, interrupts and watchdog timer. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.h index 49d23b3..e76a099 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the system, clocking, interrupts * and watchdog timer API. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.c index 7ba9fe3..f512f49 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the System Performance Component. * The SPC functions are not meant to be called directly by the user diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.h index 71b05e4..6feac37 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index dd1fd7b..1d8cb8c 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm3_psoc5.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSoC5. This includes types * necessary for core_cm3.h. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.c index dbf18a1..144ffdd 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.h index 1faee7a..ec05b4d 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/cypins.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/cypins.h index 0a3db2a..2a87f36 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/cypins.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for a * port/pin in access and control. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/cytypes.h b/KitProgConverter.cydsn/Generated_Source/PSoC5/cytypes.h index 52706aa..e135b5b 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. diff --git a/KitProgConverter.cydsn/Generated_Source/PSoC5/cyutils.c b/KitProgConverter.cydsn/Generated_Source/PSoC5/cyutils.c index 3345099..dadbd9f 100644 --- a/KitProgConverter.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/KitProgConverter.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/KitProgConverter.cydsn/KitProgConverter.cydwr b/KitProgConverter.cydsn/KitProgConverter.cydwr index bcb41ec..4ddc646 100644 --- a/KitProgConverter.cydsn/KitProgConverter.cydwr +++ b/KitProgConverter.cydsn/KitProgConverter.cydwr @@ -386,9 +386,9 @@ - + - + diff --git a/KitProgConverter.cydsn/KitProgConverter.cyfit b/KitProgConverter.cydsn/KitProgConverter.cyfit index cc8a3ed920bc4b16c89288f694b329ee299e5a98..23376dae404a0d7039f95d7ed41c87cd59d066f5 100644 GIT binary patch delta 386 zcmZ3#kZ=7$KE42NW)=|!1_lm>{H8B{8~N6Yv49wp4~jhnGd8ahpUucp02JEnDLJ2& zr5MC|BX^A%!aAn3oe9EfRCQy6uuf|`LRkVv8SD_T8q50-9h2j2O~69U({0`?^IDlJm?6wp9n8s$5N2Q(vkw#4 zvC|j!Fq=SFH+z^JAS~HlW^1qqrpNR$TY!z9KBJe}7{WT=%d87#P3vRUhX@(>F`GeH zxqVQ{>GS%S4IyHe`?V*H$ko%|^)p*SSlSbSP63N$O<;Bf E09X~AOaK4? delta 386 zcmZ3#kZ=7$KE42NW)=|!1_lm>+-1CSalF>9+0DZ5g*u zw`H=s1{T?VQF$+b43nI2GHK^d9BP9%n;_Q4(4P=2s5yY*@p@2 z*y#&Ex^W4pV7-~3}Kz`W!43=ru8xFLxha`n9U%p z+&-w}^m%>Eh7hsKeaxm17EeD+*0vvJaAiMCb`wYpCNR4K E00UBXzyJUM diff --git a/XTant.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/XTant.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index 1e1236d..678df8e 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/XTant.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -4,7 +4,7 @@ ;******************************************************************************** ;* \file Cm3RealView.scat -;* \version 5.70 +;* \version 5.80 ;* ;* \brief ;* This Linker Descriptor file describes the memory layout of the PSoC5 diff --git a/XTant.cydsn/Generated_Source/PSoC5/Cm3Start.c b/XTant.cydsn/Generated_Source/PSoC5/Cm3Start.c index e212b6f..08339f6 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/XTant.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file Cm3Start.c -* \version 5.70 +* \version 5.80 * * \brief * Startup code for the ARM CM3. diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 8d69bbc..76dbdfd 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyBootAsmGnu.s -* \version 5.70 +* \version 5.80 * * \brief * Assembly routines for GNU as. diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s index 7bec1ab..9930057 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 6cf8bfc..d7a44db 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/XTant.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 5.70 +; Version 5.80 ; ; DESCRIPTION: ; Assembly routines for RealView. diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyDmac.c b/XTant.cydsn/Generated_Source/PSoC5/CyDmac.c index 2b506a6..4395a21 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/XTant.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.c -* \version 5.70 +* \version 5.80 * * \brief * Provides an API for the DMAC component. The API includes functions for the diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyDmac.h b/XTant.cydsn/Generated_Source/PSoC5/CyDmac.h index 071f489..1e44fc7 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/XTant.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyDmac.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the DMA Controller. * diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyFlash.c b/XTant.cydsn/Generated_Source/PSoC5/CyFlash.c index efa7a67..f6ea8a5 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/XTant.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the FLASH/EEPROM. * diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyFlash.h b/XTant.cydsn/Generated_Source/PSoC5/CyFlash.h index b3a05b4..9864d31 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/XTant.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyFlash.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the FLASH/EEPROM. * diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyLib.c b/XTant.cydsn/Generated_Source/PSoC5/CyLib.c index af74c2c..705fb74 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/XTant.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.c -* \version 5.70 +* \version 5.80 * * \brief Provides a system API for the clocking, interrupts and watchdog timer. * diff --git a/XTant.cydsn/Generated_Source/PSoC5/CyLib.h b/XTant.cydsn/Generated_Source/PSoC5/CyLib.h index 49d23b3..e76a099 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/XTant.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CyLib.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the system, clocking, interrupts * and watchdog timer API. diff --git a/XTant.cydsn/Generated_Source/PSoC5/CySpc.c b/XTant.cydsn/Generated_Source/PSoC5/CySpc.c index 7ba9fe3..f512f49 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/XTant.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the System Performance Component. * The SPC functions are not meant to be called directly by the user diff --git a/XTant.cydsn/Generated_Source/PSoC5/CySpc.h b/XTant.cydsn/Generated_Source/PSoC5/CySpc.h index 71b05e4..6feac37 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/XTant.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file CySpc.c -* \version 5.70 +* \version 5.80 * * \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user diff --git a/XTant.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/XTant.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index dd1fd7b..1d8cb8c 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/XTant.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * \file core_cm3_psoc5.h -* \version 5.70 +* \version 5.80 * * \brief Provides important type information for the PSoC5. This includes types * necessary for core_cm3.h. diff --git a/XTant.cydsn/Generated_Source/PSoC5/cyPm.c b/XTant.cydsn/Generated_Source/PSoC5/cyPm.c index dbf18a1..144ffdd 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/XTant.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.c -* \version 5.70 +* \version 5.80 * * \brief Provides an API for the power management. * diff --git a/XTant.cydsn/Generated_Source/PSoC5/cyPm.h b/XTant.cydsn/Generated_Source/PSoC5/cyPm.h index 1faee7a..ec05b4d 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/XTant.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyPm.h -* \version 5.70 +* \version 5.80 * * \brief Provides the function definitions for the power management API. * diff --git a/XTant.cydsn/Generated_Source/PSoC5/cypins.h b/XTant.cydsn/Generated_Source/PSoC5/cypins.h index 0a3db2a..2a87f36 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/cypins.h +++ b/XTant.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cypins.h -* \version 5.70 +* \version 5.80 * * \brief This file contains the function prototypes and constants used for a * port/pin in access and control. diff --git a/XTant.cydsn/Generated_Source/PSoC5/cytypes.h b/XTant.cydsn/Generated_Source/PSoC5/cytypes.h index 52706aa..e135b5b 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/XTant.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cytypes.h -* \version 5.70 +* \version 5.80 * * \brief CyTypes provides register access macros and approved types for use in * firmware. diff --git a/XTant.cydsn/Generated_Source/PSoC5/cyutils.c b/XTant.cydsn/Generated_Source/PSoC5/cyutils.c index 3345099..dadbd9f 100644 --- a/XTant.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/XTant.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyutils.c -* \version 5.70 +* \version 5.80 * * \brief Provides a function to handle 24-bit value writes. * diff --git a/XTant.cydsn/XTant.cydwr b/XTant.cydsn/XTant.cydwr index 1fd0824..9ddd528 100644 --- a/XTant.cydsn/XTant.cydwr +++ b/XTant.cydsn/XTant.cydwr @@ -597,9 +597,9 @@ - + - + diff --git a/XTant.cydsn/XTant.cyprj b/XTant.cydsn/XTant.cyprj index 2fb840c..93487b1 100644 --- a/XTant.cydsn/XTant.cyprj +++ b/XTant.cydsn/XTant.cyprj @@ -190,6 +190,13 @@ + + + + + + + diff --git a/dma_core/globals.h b/dma_core/globals.h index 3aa1727..6ecf1e0 100644 --- a/dma_core/globals.h +++ b/dma_core/globals.h @@ -26,10 +26,12 @@ #define BUCKLING_SPRING 1 #define ADB 2 #define SUN 3 +#define CORTRON 4 #define SCANNER_CS 0 #define SCANNER_ADB 1 #define SCANNER_SUN 2 +#define SCANNER_CORTRON 3 // Do not touch above definitions. To change switch type change config.h #include "config.h" @@ -144,6 +146,9 @@ void xprintf(const char *format_p, ...); #elif SWITCH_TYPE == SUN #define SCANNER_TYPE SCANNER_SUN #define NORMALLY_LOW 0 +#elif SWITCH_TYPE == CORTRON +#define SCANNER_TYPE CORTRON +#define NORMALLY_LOW 1 #else #error "Unknown switch type" #endif