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lines changed Original file line number Diff line number Diff line change @@ -7,7 +7,7 @@ The documentation is available here: https://danodus.github.io/xgsoc/
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# Features
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- RISC-V (RV32IM)
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- - UART (2000000 -N-8-1)
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+ - UART (1000000 -N-8-1)
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- SDRAM (32MiB shared between CPU and video)
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- Set associative cache (4-way with LRU replacement policy)
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- VGA (60 Hz), 480p (60Hz), 720p (60Hz) or 1080p (30Hz) HDMI video output with framebuffer (RGB565)
@@ -57,7 +57,7 @@ cd rtl/ulx3s
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make clean; make VIDEO=< video mode> prog
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cd ../../src/test_graphite
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make run SERIAL=< serial device>
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- picocom -b 2000000 < serial device>
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+ picocom -b 1000000 < serial device>
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```
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and press 'h' for help.
@@ -86,7 +86,7 @@ To upload and run the program to the FPGA platform:
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``` bash
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cd src/< program name>
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make run SERIAL=< serial device>
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- picocom -b 2000000 < serial device>
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+ picocom -b 1000000 < serial device>
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```
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The following programs are available:
Original file line number Diff line number Diff line change 5
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module pll_cpu
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(
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input clkin, // 25 MHz, 0 deg
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- output clkout0, // 48 MHz, 0 deg
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+ output clkout0, // 30 MHz, 0 deg
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output locked
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);
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- wire clkfb;
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(* FREQUENCY_PIN_CLKI= "25" * )
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- (* FREQUENCY_PIN_CLKOS = "48 " * )
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+ (* FREQUENCY_PIN_CLKOP = "30 " * )
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(* ICP_CURRENT= "12" * ) (* LPF_RESISTOR= "8" * ) (* MFG_ENABLE_FILTEROPAMP= "1" * ) (* MFG_GMCREF_SEL= "2" * )
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EHXPLLL #(
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.PLLRST_ENA("DISABLED" ),
@@ -23,22 +22,17 @@ EHXPLLL #(
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.OUTDIVIDER_MUXD("DIVD" ),
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.CLKI_DIV(5 ),
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.CLKOP_ENABLE("ENABLED" ),
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- .CLKOP_DIV(48 ),
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+ .CLKOP_DIV(20 ),
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.CLKOP_CPHASE(9 ),
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.CLKOP_FPHASE(0 ),
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- .CLKOS_ENABLE("ENABLED" ),
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- .CLKOS_DIV(10 ),
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- .CLKOS_CPHASE(0 ),
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- .CLKOS_FPHASE(0 ),
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.FEEDBK_PATH("CLKOP" ),
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- .CLKFB_DIV(2 )
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+ .CLKFB_DIV(6 )
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) pll_i (
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.RST(1'b0 ),
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.STDBY(1'b0 ),
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.CLKI(clkin),
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- .CLKOP(clkfb),
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- .CLKOS(clkout0),
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- .CLKFB(clkfb),
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+ .CLKOP(clkout0),
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+ .CLKFB(clkout0),
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.CLKINTFB(),
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.PHASESEL0(1'b0 ),
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.PHASESEL1(1'b0 ),
Original file line number Diff line number Diff line change 5
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module pll_sdram
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(
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input clkin, // 25 MHz, 0 deg
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- output clkout0, // 96 MHz, 0 deg
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+ output clkout0, // 90 MHz, 0 deg
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output locked
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);
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- wire clkfb;
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(* FREQUENCY_PIN_CLKI= "25" * )
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- (* FREQUENCY_PIN_CLKOS = "96 " * )
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+ (* FREQUENCY_PIN_CLKOP = "90 " * )
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(* ICP_CURRENT= "12" * ) (* LPF_RESISTOR= "8" * ) (* MFG_ENABLE_FILTEROPAMP= "1" * ) (* MFG_GMCREF_SEL= "2" * )
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EHXPLLL #(
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.PLLRST_ENA("DISABLED" ),
@@ -23,22 +22,17 @@ EHXPLLL #(
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.OUTDIVIDER_MUXD("DIVD" ),
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.CLKI_DIV(5 ),
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.CLKOP_ENABLE("ENABLED" ),
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- .CLKOP_DIV(48 ),
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- .CLKOP_CPHASE(9 ),
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+ .CLKOP_DIV(7 ),
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+ .CLKOP_CPHASE(3 ),
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.CLKOP_FPHASE(0 ),
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- .CLKOS_ENABLE("ENABLED" ),
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- .CLKOS_DIV(5 ),
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- .CLKOS_CPHASE(0 ),
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- .CLKOS_FPHASE(0 ),
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.FEEDBK_PATH("CLKOP" ),
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- .CLKFB_DIV(2 )
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+ .CLKFB_DIV(18 )
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) pll_i (
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.RST(1'b0 ),
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.STDBY(1'b0 ),
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.CLKI(clkin),
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- .CLKOP(clkfb),
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- .CLKOS(clkout0),
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- .CLKFB(clkfb),
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+ .CLKOP(clkout0),
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+ .CLKFB(clkout0),
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.CLKINTFB(),
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.PHASESEL0(1'b0 ),
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.PHASESEL1(1'b0 ),
Original file line number Diff line number Diff line change @@ -102,8 +102,8 @@ module ulx3s_v31_top(
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assign pll_locked = pll_cpu_locked & pll_sdram_locked & pll_video_locked;
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soc_top # (
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- .FREQ_HZ (48_000_000 ),
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- .BAUD_RATE (2_000_000 )
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+ .FREQ_HZ (30_000_000 ),
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+ .BAUD_RATE (1_000_000 )
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) soc_top (
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.clk_cpu (clk_cpu),
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.clk_sdram (clk_sdram),
Original file line number Diff line number Diff line change @@ -27,7 +27,7 @@ def main(argv):
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exit (0 )
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else :
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try :
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- ser = serial .Serial (argv [0 ], baudrate = 230400 )
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+ ser = serial .Serial (argv [0 ], baudrate = 1000000 )
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except serial .serialutil .SerialException :
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print ("Unable to open the serial device {0}" .format (argv [0 ]))
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exit (1 )
Original file line number Diff line number Diff line change @@ -23,7 +23,7 @@ def main(argv):
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delay_block = float (argv [3 ])
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try :
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- ser = serial .Serial (argv [0 ], baudrate = 2000000 )
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+ ser = serial .Serial (argv [0 ], baudrate = 1000000 )
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except serial .serialutil .SerialException :
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print ("Unable to open the serial device {0}" .format (argv [0 ]))
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exit (1 )
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