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Commit 8b9bca6

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Daniel Cliche
committed
Frequencies adjusted
1 parent af67a65 commit 8b9bca6

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-32
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6 files changed

+20
-32
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README.md

+3-3
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ The documentation is available here: https://danodus.github.io/xgsoc/
77
# Features
88

99
- RISC-V (RV32IM)
10-
- UART (2000000-N-8-1)
10+
- UART (1000000-N-8-1)
1111
- SDRAM (32MiB shared between CPU and video)
1212
- Set associative cache (4-way with LRU replacement policy)
1313
- VGA (60 Hz), 480p (60Hz), 720p (60Hz) or 1080p (30Hz) HDMI video output with framebuffer (RGB565)
@@ -57,7 +57,7 @@ cd rtl/ulx3s
5757
make clean;make VIDEO=<video mode> prog
5858
cd ../../src/test_graphite
5959
make run SERIAL=<serial device>
60-
picocom -b 2000000 <serial device>
60+
picocom -b 1000000 <serial device>
6161
```
6262

6363
and press 'h' for help.
@@ -86,7 +86,7 @@ To upload and run the program to the FPGA platform:
8686
```bash
8787
cd src/<program name>
8888
make run SERIAL=<serial device>
89-
picocom -b 2000000 <serial device>
89+
picocom -b 1000000 <serial device>
9090
```
9191

9292
The following programs are available:

rtl/ulx3s/pll_cpu.v

+6-12
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,11 @@
55
module pll_cpu
66
(
77
input clkin, // 25 MHz, 0 deg
8-
output clkout0, // 48 MHz, 0 deg
8+
output clkout0, // 30 MHz, 0 deg
99
output locked
1010
);
11-
wire clkfb;
1211
(* FREQUENCY_PIN_CLKI="25" *)
13-
(* FREQUENCY_PIN_CLKOS="48" *)
12+
(* FREQUENCY_PIN_CLKOP="30" *)
1413
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
1514
EHXPLLL #(
1615
.PLLRST_ENA("DISABLED"),
@@ -23,22 +22,17 @@ EHXPLLL #(
2322
.OUTDIVIDER_MUXD("DIVD"),
2423
.CLKI_DIV(5),
2524
.CLKOP_ENABLE("ENABLED"),
26-
.CLKOP_DIV(48),
25+
.CLKOP_DIV(20),
2726
.CLKOP_CPHASE(9),
2827
.CLKOP_FPHASE(0),
29-
.CLKOS_ENABLE("ENABLED"),
30-
.CLKOS_DIV(10),
31-
.CLKOS_CPHASE(0),
32-
.CLKOS_FPHASE(0),
3328
.FEEDBK_PATH("CLKOP"),
34-
.CLKFB_DIV(2)
29+
.CLKFB_DIV(6)
3530
) pll_i (
3631
.RST(1'b0),
3732
.STDBY(1'b0),
3833
.CLKI(clkin),
39-
.CLKOP(clkfb),
40-
.CLKOS(clkout0),
41-
.CLKFB(clkfb),
34+
.CLKOP(clkout0),
35+
.CLKFB(clkout0),
4236
.CLKINTFB(),
4337
.PHASESEL0(1'b0),
4438
.PHASESEL1(1'b0),

rtl/ulx3s/pll_sdram.v

+7-13
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,11 @@
55
module pll_sdram
66
(
77
input clkin, // 25 MHz, 0 deg
8-
output clkout0, // 96 MHz, 0 deg
8+
output clkout0, // 90 MHz, 0 deg
99
output locked
1010
);
11-
wire clkfb;
1211
(* FREQUENCY_PIN_CLKI="25" *)
13-
(* FREQUENCY_PIN_CLKOS="96" *)
12+
(* FREQUENCY_PIN_CLKOP="90" *)
1413
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
1514
EHXPLLL #(
1615
.PLLRST_ENA("DISABLED"),
@@ -23,22 +22,17 @@ EHXPLLL #(
2322
.OUTDIVIDER_MUXD("DIVD"),
2423
.CLKI_DIV(5),
2524
.CLKOP_ENABLE("ENABLED"),
26-
.CLKOP_DIV(48),
27-
.CLKOP_CPHASE(9),
25+
.CLKOP_DIV(7),
26+
.CLKOP_CPHASE(3),
2827
.CLKOP_FPHASE(0),
29-
.CLKOS_ENABLE("ENABLED"),
30-
.CLKOS_DIV(5),
31-
.CLKOS_CPHASE(0),
32-
.CLKOS_FPHASE(0),
3328
.FEEDBK_PATH("CLKOP"),
34-
.CLKFB_DIV(2)
29+
.CLKFB_DIV(18)
3530
) pll_i (
3631
.RST(1'b0),
3732
.STDBY(1'b0),
3833
.CLKI(clkin),
39-
.CLKOP(clkfb),
40-
.CLKOS(clkout0),
41-
.CLKFB(clkfb),
34+
.CLKOP(clkout0),
35+
.CLKFB(clkout0),
4236
.CLKINTFB(),
4337
.PHASESEL0(1'b0),
4438
.PHASESEL1(1'b0),

rtl/ulx3s/ulx3s_v31_top.sv

+2-2
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,8 @@ module ulx3s_v31_top(
102102
assign pll_locked = pll_cpu_locked & pll_sdram_locked & pll_video_locked;
103103

104104
soc_top #(
105-
.FREQ_HZ(48_000_000),
106-
.BAUD_RATE(2_000_000)
105+
.FREQ_HZ(30_000_000),
106+
.BAUD_RATE(1_000_000)
107107
) soc_top(
108108
.clk_cpu(clk_cpu),
109109
.clk_sdram(clk_sdram),

utils/sendbin.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ def main(argv):
2727
exit(0)
2828
else:
2929
try:
30-
ser = serial.Serial(argv[0], baudrate=230400)
30+
ser = serial.Serial(argv[0], baudrate=1000000)
3131
except serial.serialutil.SerialException:
3232
print("Unable to open the serial device {0}".format(argv[0]))
3333
exit(1)

utils/sendhex.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ def main(argv):
2323
delay_block = float(argv[3])
2424

2525
try:
26-
ser = serial.Serial(argv[0], baudrate=2000000)
26+
ser = serial.Serial(argv[0], baudrate=1000000)
2727
except serial.serialutil.SerialException:
2828
print("Unable to open the serial device {0}".format(argv[0]))
2929
exit(1)

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