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Daniel Cliche
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Preliminary zoom support
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README.md

+2
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,8 @@ The following video modes are available:
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By default, the video mode is `vga`.
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85+
For a 2x zoom, add `2x` at the end of the video mode (for example: `480p2x`).
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## System Simulation
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```bash

rtl/sim/Makefile

+1-1
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@@ -38,7 +38,7 @@ clean:
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rm -rf obj_dir
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sim: top.sv sim_main.cpp $(PROGRAM)
41-
$(VERILATOR) -cc --exe $(CFLAGS) $(LDFLAGS) --trace --top-module top -DVIDEO top.sv sdl_ps2.cpp sim_main.cpp -I.. -I../riscv -I../usb -I../../external/graphite/rtl $(SRC) -Wno-PINMISSING -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-TIMESCALEMOD -Wno-NULLPORT -Wno-MULTIDRIVEN -Wno-UNOPTFLAT
41+
$(VERILATOR) -cc --exe $(CFLAGS) $(LDFLAGS) --trace --top-module top -DVIDEO -DVIDEO_480P -DZOOM top.sv sdl_ps2.cpp sim_main.cpp -I.. -I../riscv -I../usb -I../../external/graphite/rtl $(SRC) -Wno-PINMISSING -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-TIMESCALEMOD -Wno-NULLPORT -Wno-MULTIDRIVEN -Wno-UNOPTFLAT
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$(MAKE) -j 4 -C obj_dir -f Vtop.mk
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run: sim

rtl/sim/sim_main.cpp

+6-2
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,12 @@ const int screen_width = 1024;
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const int screen_height = 768;
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// 640x480
27-
const int vga_width = 800;
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const int vga_height = 525;
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//const int vga_width = 800;
28+
//const int vga_height = 525;
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30+
// 848x480
31+
const int vga_width = 1088;
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const int vga_height = 517;
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double sc_time_stamp()
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{

rtl/soc_top.sv

+41
Original file line numberDiff line numberDiff line change
@@ -406,8 +406,13 @@ module soc_top #(
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graphite #(
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.FB_ADDRESS(DEFAULT_FB_ADDRESS >> 'd1),
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`ifdef ZOOM
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.FB_WIDTH(H_RES/2),
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.FB_HEIGHT(V_RES/2)
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`else
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.FB_WIDTH(H_RES),
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.FB_HEIGHT(V_RES)
415+
`endif
411416
) graphite(
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.clk(clk_cpu),
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.reset_i(~rst_n),
@@ -449,7 +454,11 @@ module soc_top #(
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`endif // PS2_KBD
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`ifdef VIDEO
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(iowadr == 8) ? {31'b0, graphite_cmd_axis_tready} :
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`ifdef ZOOM
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(iowadr == 9) ? {16'(H_RES/2), 16'(V_RES/2)} :
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`else // ZOOM
452460
(iowadr == 9) ? {16'(H_RES), 16'(V_RES)} :
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`endif // ZOOM
453462
(iowadr == 10) ? fb_addr :
454463
(iowadr == 11) ? {31'b0, vga_vsync} :
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`else // VIDEO
@@ -677,6 +686,19 @@ module soc_top #(
677686
.Reset(),
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.RPReset()
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);
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`ifdef ZOOM
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logic [10:0] col_counter = 11'd0;
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logic [10:0] line_counter = 11'd0;
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logic [19:0] line_vidadr = 20'd0;
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logic line_dup;
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logic end_of_frame, end_of_line;
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assign end_of_frame = line_counter == V_RES - 1;
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assign end_of_line = col_counter == 11'(H_RES / 32 - 1);
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assign line_dup = end_of_line && !line_counter[0];
700+
`endif
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680702
`endif // VIDEO
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logic nop;
@@ -694,8 +716,27 @@ module soc_top #(
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`ifdef VIDEO
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2'b10: begin
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crw <= 1'b0; // VGA read
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`ifdef ZOOM
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if (col_counter == 11'd0)
721+
line_vidadr <= vidadr;
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723+
if (end_of_line) begin
724+
col_counter <= 11'd0;
725+
line_counter <= line_counter + 11'd1;
726+
end else begin
727+
col_counter <= col_counter + 11'd1;
728+
end
729+
if (end_of_frame && end_of_line) begin
730+
vidadr <= 20'd0;
731+
col_counter <= 11'd0;
732+
line_counter <= 11'd0;
733+
end else begin
734+
vidadr <= line_dup ? line_vidadr : vidadr + 20'd1;
735+
end
736+
`else // ZOOM
697737
if(vidadr == 20'(H_RES*V_RES*2/32-1)) vidadr <= 20'd0;
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else vidadr <= vidadr + 20'b1;
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`endif // ZOOM
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end
700741
`endif // VIDEO
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2'b01, 2'b11: crw <= 1'b1; // cache read/write

rtl/ulx3s/Makefile

+7-3
Original file line numberDiff line numberDiff line change
@@ -53,17 +53,21 @@ DEFINES =
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ifneq (,$(findstring v,$(CONF)))
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DEFINES += -DVIDEO
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56-
ifeq ($(VIDEO),480p)
56+
ifneq (,$(findstring 480p,$(VIDEO)))
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DEFINES += -DVIDEO_480P
5858
endif
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60-
ifeq ($(VIDEO),720p)
60+
ifneq (,$(findstring 720p,$(VIDEO)))
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DEFINES += -DVIDEO_720P
6262
endif
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64-
ifeq ($(VIDEO),1080p)
64+
ifneq (,$(findstring 1080p,$(VIDEO)))
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DEFINES += -DVIDEO_1080P
6666
endif
67+
68+
ifneq (,$(findstring 2x,$(VIDEO)))
69+
DEFINES += -DZOOM
70+
endif
6771
endif
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6973
ifneq (,$(findstring k,$(CONF)))

rtl/video.v

+10-2
Original file line numberDiff line numberDiff line change
@@ -60,20 +60,28 @@ assign hend = (hcnt == H_TOTAL-1), vend = (vcnt == V_TOTAL-1);
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assign vblank = (vcnt >= V_RES);
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assign hsync = (hcnt >= H_RES+H_FP) & (hcnt < H_RES+H_FP+H_BP);
6262
assign vsync = (vcnt >= V_RES+V_FP) & (vcnt < V_RES+V_FP+V_BP);
63-
assign xfer = hcnt[0]; // data delay > hcnt cycle + req cycle
63+
`ifdef ZOOM
64+
assign xfer = hcnt[1:0] == 2'b11;
65+
`else
66+
assign xfer = hcnt[0];
67+
`endif
6468
assign vid = (~hblank & ~vblank) ? pixbuf[15:0] : 16'd0;
6569
assign RGB = vid;
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6771
always @(posedge pclk) if(ce && init_req_counter == 2'd0) begin // pixel clock domain
6872
hcnt <= hend ? 0 : hcnt+1;
6973
vcnt <= hend ? (vend ? 0 : (vcnt+1)) : vcnt;
7074
hblank <= xfer ? (hcnt >= H_RES) : hblank;
75+
`ifdef ZOOM
76+
pixbuf <= hcnt[1] ? vidbuf : {pixbuf[31:16], pixbuf[31:16]};
77+
`else
7178
pixbuf <= xfer ? vidbuf : {16'd0, pixbuf[31:16]};
79+
`endif
7280
end
7381

7482
always @(posedge pclk) if(ce) begin // CPU (SRAM) clock domain
7583
if (init_req_counter == 2'd0) begin
76-
hword <= hcnt[0];
84+
hword <= xfer;
7785
req <= ~vblank & (hcnt < H_RES) & hword; // i.e. adr changed
7886
vidbuf <= req ? viddata : vidbuf;
7987
end else begin

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