From 8ba323ec6139bd98caed53bfed796b1546090b43 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 18 Jan 2021 14:23:13 -0800 Subject: [PATCH 1/2] Don't attempt to cover non-existent U-mode counters --- src/main/scala/rocket/CSR.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 032ac424a9b..83fe596cd9b 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -855,7 +855,10 @@ class CSRFile( io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register - read_mapping.foreach( {case (k, v) => { + val coverable_counters = read_mapping.filterNot { case (k, _) => + k >= CSR.firstHPM + nPerfCounters && k < CSR.firstHPM + CSR.nHPM + } + coverable_counters.foreach( {case (k, v) => { when (!k(11,10).andR) { // Cover points for RW CSR registers cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers From 7a9799b78c295934cf2c29f4773f52c92541a2fb Mon Sep 17 00:00:00 2001 From: Umer Imran Date: Wed, 27 Jan 2021 23:34:41 -0800 Subject: [PATCH 2/2] Modification in the logic to not cover non-existent U-mode counters --- src/main/scala/rocket/CSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 83fe596cd9b..609e828f106 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -856,7 +856,7 @@ class CSRFile( // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => - k >= CSR.firstHPM + nPerfCounters && k < CSR.firstHPM + CSR.nHPM + k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k(11,10).andR) { // Cover points for RW CSR registers