From 9eca3c171b28ee9abf3e1612f47cacddedd2461c Mon Sep 17 00:00:00 2001 From: John Ingalls Date: Fri, 9 Apr 2021 11:55:08 -0700 Subject: [PATCH] Core/TLB: cacheable when supportsAcquireB --- src/main/scala/rocket/DCache.scala | 2 +- src/main/scala/rocket/HellaCache.scala | 2 +- src/main/scala/rocket/TLB.scala | 2 +- src/main/scala/rocket/TLBPermissions.scala | 1 + 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index db069ae9bdf..e6d47814a1c 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -1175,7 +1175,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { - if (!edge.manager.anySupportAcquireT) Wire(new TLBundleA(edge.bundle)) + if (!edge.manager.anySupportAcquireB) Wire(new TLBundleA(edge.bundle)) else edge.AcquireBlock(UInt(0), paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes, param)._2 } diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 0b74d23f3de..6fbdec1a847 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -210,7 +210,7 @@ abstract class HellaCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameter val module: HellaCacheModule - def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) + def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index fbb2d148496..765bd3b3cdd 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -198,7 +198,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_) def fastCheck(member: TLManagerParameters => Boolean) = legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b)) - val cacheable = fastCheck(_.supportsAcquireT) && (instruction || !usingDataScratchpad) + val cacheable = fastCheck(_.supportsAcquireB) && (instruction || !usingDataScratchpad) val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous val deny_access_to_debug = mpu_priv <= PRV.M && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false) val prot_r = fastCheck(_.supportsGet) && !deny_access_to_debug && pmp.io.r diff --git a/src/main/scala/rocket/TLBPermissions.scala b/src/main/scala/rocket/TLBPermissions.scala index f838dfc1717..8a6ab987a6e 100644 --- a/src/main/scala/rocket/TLBPermissions.scala +++ b/src/main/scala/rocket/TLBPermissions.scala @@ -66,6 +66,7 @@ object TLBPageLookup require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") + require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers)