From af27f0a56d6c47bbe0585216a7d2aa71d4fc30b6 Mon Sep 17 00:00:00 2001 From: Dhruv Gupta Date: Thu, 25 Jun 2020 04:15:08 -0700 Subject: [PATCH 1/2] Added channel C-D properties --- src/main/scala/tilelink/Monitor.scala | 214 +++++++++++++++++++++----- 1 file changed, 173 insertions(+), 41 deletions(-) diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala index 9a0c8ca57b9..d0f2e16c0d6 100644 --- a/src/main/scala/tilelink/Monitor.scala +++ b/src/main/scala/tilelink/Monitor.scala @@ -165,13 +165,13 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { - monAssert (edge.expectsVipCheckerSlaveToMasterProbe(edge.source(bundle), edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) - monAssert (address_ok, "'B' channel Probe carries unmanaged address" + extra) - monAssert (legal_source, "'B' channel Probe carries source that is not first source" + extra) - monAssert (is_aligned, "'B' channel Probe address not aligned to size" + extra) - monAssert (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) - monAssert (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) - monAssert (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) + assume (edge.expectsVipCheckerSlaveToMasterProbe(edge.source(bundle), edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) + assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) + assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) + assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) + assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) + assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) + assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { @@ -602,87 +602,111 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } def legalizeADSource(bundle: TLBundle, edge: TLEdge) { - val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) - val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything + val a_size_bus_size = edge.bundle.sizeBits + 1 // add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) + val a_opcode_bus_size = 3 + 1 // opcode size is 3, but add so that 0 is not mapped to anything + val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) - val log_a_size_bus_size = log2Ceil(a_size_bus_size) + val log_a_size_bus_size = log2Ceil(a_size_bus_size) + def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits - val inflight = RegInit(0.U(edge.client.endSourceId.W)) - inflight.suggestName("inflight") + val inflight = RegInit(0.U(edge.client.endSourceId.W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) + val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) + inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") - val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire()) - a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire()) + a_first.suggestName("a_first") d_first.suggestName("d_first") - val a_set = WireInit(0.U(edge.client.endSourceId.W)) + val a_set = WireInit(0.U(edge.client.endSourceId.W)) + val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) + val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) + val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_set.suggestName("a_set") - val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) + a_set_wo_ready.suggestName("a_set_wo_ready") a_opcodes_set.suggestName("a_opcodes_set") - val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((1 << log_a_opcode_bus_size).W)) - a_opcode_lookup.suggestName("a_opcode_lookup") + val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U - - val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) + a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U + a_opcode_lookup.suggestName("a_opcode_lookup") a_size_lookup.suggestName("a_size_lookup") - a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U - val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) + val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) + val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") - val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") + when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { + a_set_wo_ready := UIntToOH(bundle.a.bits.source) + } + when (bundle.a.fire() && a_first && edge.isRequest(bundle.a.bits)) { - a_set := UIntToOH(bundle.a.bits.source) + a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U - a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U - a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) - a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) + a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U + a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) + a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } - val d_clr = WireInit(0.U(edge.client.endSourceId.W)) + val d_clr = WireInit(0.U(edge.client.endSourceId.W)) + val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) + val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) + val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_clr.suggestName("d_clr") - val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) + d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") - val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck + when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { + d_clr_wo_ready := UIntToOH(bundle.d.bits.source) + } + when (bundle.d.fire() && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { - d_clr := UIntToOH(bundle.d.bits.source) + d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) - d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) + d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } + when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { - assume(((inflight)(bundle.d.bits.source)) || (bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && (bundle.a.bits.size === bundle.d.bits.size) && a_first), "'D' channel acknowledged for nothing inflight" + extra) - assume(((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup))) - || (bundle.a.valid && ((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)))), - "'D' channel contains improper opcode response" + extra) - assume((bundle.d.bits.size === a_size_lookup) || (bundle.a.valid && (bundle.a.bits.size === bundle.d.bits.size)), "'D' channel contains improper response size" + extra) + val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) + assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) + + when (same_cycle_resp) { + assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || + (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) + assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) + } .otherwise { + assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || + (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) + assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) + } } + when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { - assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) + when (a_set_wo_ready.orR) { + assume(a_set_wo_ready =/= d_clr_wo_ready, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) + } } - inflight := (inflight | a_set) & ~d_clr + inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr - inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr + inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", @@ -690,7 +714,114 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U - when (bundle.a.fire() || bundle.d.fire()) { watchdog := 0.U } + when (bundle.a.fire() || bundle.d.fire()) {watchdog := 0.U} + } + + def legalizeCDSource(bundle: TLBundle, edge: TLEdge) { + val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) + val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything + + val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) + val log_c_size_bus_size = log2Ceil(c_size_bus_size) + def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits + + val inflight = RegInit(0.U(edge.client.endSourceId.W)) + val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) + val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) + inflight.suggestName("inflight") + inflight_opcodes.suggestName("inflight_opcodes") + inflight_sizes.suggestName("inflight_sizes") + + val c_first = edge.first(bundle.c.bits, bundle.c.fire()) + val d_first = edge.first(bundle.d.bits, bundle.d.fire()) + c_first.suggestName("c_first") + d_first.suggestName("d_first") + + val c_set = WireInit(0.U(edge.client.endSourceId.W)) + val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) + val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) + val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) + c_set.suggestName("c_set") + c_set_wo_ready.suggestName("c_set_wo_ready") + c_opcodes_set.suggestName("c_opcodes_set") + c_sizes_set.suggestName("c_sizes_set") + + val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) + val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) + c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U + c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U + c_opcode_lookup.suggestName("c_opcode_lookup") + c_size_lookup.suggestName("c_size_lookup") + + val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) + val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) + c_opcodes_set_interm.suggestName("c_opcodes_set_interm") + c_sizes_set_interm.suggestName("c_sizes_set_interm") + + when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { + c_set_wo_ready := UIntToOH(bundle.c.bits.source) + } + + when (bundle.c.fire() && c_first && edge.isRequest(bundle.c.bits)) { + c_set := UIntToOH(bundle.c.bits.source) + c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U + c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U + c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) + c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) + monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) + } + + val d_clr = WireInit(0.U(edge.client.endSourceId.W)) + val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) + val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) + val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) + d_clr.suggestName("d_clr") + d_clr_wo_ready.suggestName("d_clr_wo_ready") + d_opcodes_clr.suggestName("d_opcodes_clr") + d_sizes_clr.suggestName("d_sizes_clr") + + val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck + when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { + d_clr_wo_ready := UIntToOH(bundle.d.bits.source) + } + + when (bundle.d.fire() && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { + d_clr := UIntToOH(bundle.d.bits.source) + d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) + d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) + } + + when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { + val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) + assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) + when (same_cycle_resp) { + assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) + } .otherwise { + assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) + } + } + + when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack) { + assume((!bundle.d.ready) || bundle.c.ready, "ready check") + } + + if (edge.manager.minLatency > 0) { + when (c_set_wo_ready.orR) { + assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) + } + } + + inflight := (inflight | c_set) & ~d_clr + inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr + inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr + + val watchdog = RegInit(0.U(32.W)) + val limit = PlusArg("tilelink_timeout", + docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") + monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) + + watchdog := watchdog + 1.U + when (bundle.c.fire() || bundle.d.fire()) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge) { @@ -725,6 +856,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) + legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } From 06f18814bc927d5e184bb0d3f963b32108c993a7 Mon Sep 17 00:00:00 2001 From: Dhruv Gupta Date: Fri, 26 Jun 2020 00:56:28 -0700 Subject: [PATCH 2/2] Fixed re-ordering of lines as Wes suggested --- src/main/scala/tilelink/Monitor.scala | 43 ++++++++++++--------------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala index d0f2e16c0d6..40fa5c7a5b5 100644 --- a/src/main/scala/tilelink/Monitor.scala +++ b/src/main/scala/tilelink/Monitor.scala @@ -602,48 +602,47 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec } def legalizeADSource(bundle: TLBundle, edge: TLEdge) { - val a_size_bus_size = edge.bundle.sizeBits + 1 // add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) - val a_opcode_bus_size = 3 + 1 // opcode size is 3, but add so that 0 is not mapped to anything - + val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) + val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) - def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits - val inflight = RegInit(0.U(edge.client.endSourceId.W)) - val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) - val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) + val inflight = RegInit(0.U(edge.client.endSourceId.W)) inflight.suggestName("inflight") + val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") + val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire()) - val d_first = edge.first(bundle.d.bits, bundle.d.fire()) a_first.suggestName("a_first") + val d_first = edge.first(bundle.d.bits, bundle.d.fire()) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) - val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) - val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") + val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") + val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((1 << log_a_opcode_bus_size).W)) - val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) - a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U - a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U a_opcode_lookup.suggestName("a_opcode_lookup") + a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U + + val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") + a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) - val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") + val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { @@ -661,11 +660,11 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) - val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) - val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") + val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") + val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck @@ -678,7 +677,6 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } - when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) @@ -693,20 +691,17 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } - when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { - when (a_set_wo_ready.orR) { - assume(a_set_wo_ready =/= d_clr_wo_ready, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) - } + assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) } - inflight := (inflight | a_set) & ~d_clr + inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr - inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr + inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", @@ -714,7 +709,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U - when (bundle.a.fire() || bundle.d.fire()) {watchdog := 0.U} + when (bundle.a.fire() || bundle.d.fire()) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge) {